Commit | Line | Data |
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7facc2f9 | 1 | /* |
2 | * linux/arch/arm/mach-pxa/mfp-pxa2xx.c | |
3 | * | |
4 | * PXA2xx pin mux configuration support | |
5 | * | |
6 | * The GPIOs on PXA2xx can be configured as one of many alternate | |
7 | * functions, this is by concept samilar to the MFP configuration | |
8 | * on PXA3xx, what's more important, the low power pin state and | |
9 | * wakeup detection are also supported by the same framework. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/module.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/sysdev.h> | |
20 | ||
a09e64fb RK |
21 | #include <mach/hardware.h> |
22 | #include <mach/pxa-regs.h> | |
23 | #include <mach/pxa2xx-regs.h> | |
24 | #include <mach/mfp-pxa2xx.h> | |
7facc2f9 | 25 | |
26 | #include "generic.h" | |
27 | ||
5a3d9651 EM |
28 | #define gpio_to_bank(gpio) ((gpio) >> 5) |
29 | ||
30 | #define PGSR(x) __REG2(0x40F00020, (x) << 2) | |
31 | #define __GAFR(u, x) __REG2((u) ? 0x40E00058 : 0x40E00054, (x) << 3) | |
32 | #define GAFR_L(x) __GAFR(0, x) | |
33 | #define GAFR_U(x) __GAFR(1, x) | |
7facc2f9 | 34 | |
35 | #define PWER_WE35 (1 << 24) | |
36 | ||
c0a596d6 | 37 | struct gpio_desc { |
7facc2f9 | 38 | unsigned valid : 1; |
39 | unsigned can_wakeup : 1; | |
40 | unsigned keypad_gpio : 1; | |
067455aa | 41 | unsigned dir_inverted : 1; |
7facc2f9 | 42 | unsigned int mask; /* bit mask in PWER or PKWR */ |
99687114 | 43 | unsigned int mux_mask; /* bit mask of muxed gpio bits, 0 if no mux */ |
7facc2f9 | 44 | unsigned long config; |
c0a596d6 | 45 | }; |
46 | ||
47 | static struct gpio_desc gpio_desc[MFP_PIN_GPIO127 + 1]; | |
7facc2f9 | 48 | |
5a3d9651 | 49 | static unsigned long gpdr_lpm[4]; |
566b450c | 50 | |
c0a596d6 | 51 | static int __mfp_config_gpio(unsigned gpio, unsigned long c) |
7facc2f9 | 52 | { |
53 | unsigned long gafr, mask = GPIO_bit(gpio); | |
5a3d9651 EM |
54 | int bank = gpio_to_bank(gpio); |
55 | int uorl = !!(gpio & 0x10); /* GAFRx_U or GAFRx_L ? */ | |
56 | int shft = (gpio & 0xf) << 1; | |
57 | int fn = MFP_AF(c); | |
067455aa | 58 | int is_out = (c & MFP_DIR_OUT) ? 1 : 0; |
7facc2f9 | 59 | |
7facc2f9 | 60 | if (fn > 3) |
61 | return -EINVAL; | |
62 | ||
5a3d9651 EM |
63 | /* alternate function and direction at run-time */ |
64 | gafr = (uorl == 0) ? GAFR_L(bank) : GAFR_U(bank); | |
65 | gafr = (gafr & ~(0x3 << shft)) | (fn << shft); | |
7facc2f9 | 66 | |
5a3d9651 EM |
67 | if (uorl == 0) |
68 | GAFR_L(bank) = gafr; | |
69 | else | |
70 | GAFR_U(bank) = gafr; | |
71 | ||
067455aa | 72 | if (is_out ^ gpio_desc[gpio].dir_inverted) |
7facc2f9 | 73 | GPDR(gpio) |= mask; |
74 | else | |
75 | GPDR(gpio) &= ~mask; | |
76 | ||
5a3d9651 EM |
77 | /* alternate function and direction at low power mode */ |
78 | switch (c & MFP_LPM_STATE_MASK) { | |
79 | case MFP_LPM_DRIVE_HIGH: | |
80 | PGSR(bank) |= mask; | |
067455aa | 81 | is_out = 1; |
5a3d9651 EM |
82 | break; |
83 | case MFP_LPM_DRIVE_LOW: | |
84 | PGSR(bank) &= ~mask; | |
067455aa | 85 | is_out = 1; |
5a3d9651 EM |
86 | break; |
87 | case MFP_LPM_DEFAULT: | |
88 | break; | |
89 | default: | |
90 | /* warning and fall through, treat as MFP_LPM_DEFAULT */ | |
91 | pr_warning("%s: GPIO%d: unsupported low power mode\n", | |
92 | __func__, gpio); | |
93 | break; | |
94 | } | |
95 | ||
067455aa | 96 | if (is_out ^ gpio_desc[gpio].dir_inverted) |
5a3d9651 EM |
97 | gpdr_lpm[bank] |= mask; |
98 | else | |
99 | gpdr_lpm[bank] &= ~mask; | |
7facc2f9 | 100 | |
c0a596d6 | 101 | /* give early warning if MFP_LPM_CAN_WAKEUP is set on the |
102 | * configurations of those pins not able to wakeup | |
103 | */ | |
104 | if ((c & MFP_LPM_CAN_WAKEUP) && !gpio_desc[gpio].can_wakeup) { | |
7facc2f9 | 105 | pr_warning("%s: GPIO%d unable to wakeup\n", |
106 | __func__, gpio); | |
107 | return -EINVAL; | |
108 | } | |
109 | ||
067455aa | 110 | if ((c & MFP_LPM_CAN_WAKEUP) && is_out) { |
c0a596d6 | 111 | pr_warning("%s: output GPIO%d unable to wakeup\n", |
112 | __func__, gpio); | |
113 | return -EINVAL; | |
7facc2f9 | 114 | } |
115 | ||
116 | return 0; | |
117 | } | |
118 | ||
0fedb0ca EM |
119 | static inline int __mfp_validate(int mfp) |
120 | { | |
121 | int gpio = mfp_to_gpio(mfp); | |
122 | ||
123 | if ((mfp > MFP_PIN_GPIO127) || !gpio_desc[gpio].valid) { | |
124 | pr_warning("%s: GPIO%d is invalid pin\n", __func__, gpio); | |
125 | return -1; | |
126 | } | |
127 | ||
128 | return gpio; | |
129 | } | |
130 | ||
7facc2f9 | 131 | void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num) |
132 | { | |
133 | unsigned long flags; | |
134 | unsigned long *c; | |
135 | int i, gpio; | |
136 | ||
137 | for (i = 0, c = mfp_cfgs; i < num; i++, c++) { | |
138 | ||
0fedb0ca EM |
139 | gpio = __mfp_validate(MFP_PIN(*c)); |
140 | if (gpio < 0) | |
7facc2f9 | 141 | continue; |
7facc2f9 | 142 | |
143 | local_irq_save(flags); | |
144 | ||
145 | gpio_desc[gpio].config = *c; | |
146 | __mfp_config_gpio(gpio, *c); | |
147 | ||
148 | local_irq_restore(flags); | |
149 | } | |
150 | } | |
151 | ||
566b450c EM |
152 | void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm) |
153 | { | |
5a3d9651 | 154 | unsigned long flags, c; |
566b450c EM |
155 | int gpio; |
156 | ||
157 | gpio = __mfp_validate(mfp); | |
158 | if (gpio < 0) | |
159 | return; | |
160 | ||
161 | local_irq_save(flags); | |
5a3d9651 EM |
162 | |
163 | c = gpio_desc[gpio].config; | |
164 | c = (c & ~MFP_LPM_STATE_MASK) | lpm; | |
165 | __mfp_config_gpio(gpio, c); | |
166 | ||
566b450c EM |
167 | local_irq_restore(flags); |
168 | } | |
169 | ||
c0a596d6 | 170 | int gpio_set_wake(unsigned int gpio, unsigned int on) |
171 | { | |
172 | struct gpio_desc *d; | |
99687114 | 173 | unsigned long c, mux_taken; |
c0a596d6 | 174 | |
175 | if (gpio > mfp_to_gpio(MFP_PIN_GPIO127)) | |
176 | return -EINVAL; | |
177 | ||
178 | d = &gpio_desc[gpio]; | |
179 | c = d->config; | |
180 | ||
181 | if (!d->valid) | |
182 | return -EINVAL; | |
183 | ||
184 | if (d->keypad_gpio) | |
185 | return -EINVAL; | |
186 | ||
99687114 RJ |
187 | mux_taken = (PWER & d->mux_mask) & (~d->mask); |
188 | if (on && mux_taken) | |
189 | return -EBUSY; | |
190 | ||
c0a596d6 | 191 | if (d->can_wakeup && (c & MFP_LPM_CAN_WAKEUP)) { |
192 | if (on) { | |
99687114 | 193 | PWER = (PWER & ~d->mux_mask) | d->mask; |
c0a596d6 | 194 | |
195 | if (c & MFP_LPM_EDGE_RISE) | |
196 | PRER |= d->mask; | |
197 | else | |
198 | PRER &= ~d->mask; | |
199 | ||
200 | if (c & MFP_LPM_EDGE_FALL) | |
201 | PFER |= d->mask; | |
202 | else | |
203 | PFER &= ~d->mask; | |
204 | } else { | |
205 | PWER &= ~d->mask; | |
206 | PRER &= ~d->mask; | |
207 | PFER &= ~d->mask; | |
208 | } | |
209 | } | |
210 | return 0; | |
211 | } | |
212 | ||
7facc2f9 | 213 | #ifdef CONFIG_PXA25x |
5a3d9651 | 214 | static void __init pxa25x_mfp_init(void) |
7facc2f9 | 215 | { |
216 | int i; | |
217 | ||
ddd244dd | 218 | for (i = 0; i <= pxa_last_gpio; i++) |
5a3d9651 | 219 | gpio_desc[i].valid = 1; |
7facc2f9 | 220 | |
5a3d9651 EM |
221 | for (i = 0; i <= 15; i++) { |
222 | gpio_desc[i].can_wakeup = 1; | |
223 | gpio_desc[i].mask = GPIO_bit(i); | |
7facc2f9 | 224 | } |
067455aa EM |
225 | |
226 | /* PXA26x has additional 4 GPIOs (86/87/88/89) which has the | |
227 | * direction bit inverted in GPDR2. See PXA26x DM 4.1.1. | |
228 | */ | |
229 | for (i = 86; i <= pxa_last_gpio; i++) | |
230 | gpio_desc[i].dir_inverted = 1; | |
7facc2f9 | 231 | } |
5a3d9651 EM |
232 | #else |
233 | static inline void pxa25x_mfp_init(void) {} | |
7facc2f9 | 234 | #endif /* CONFIG_PXA25x */ |
235 | ||
236 | #ifdef CONFIG_PXA27x | |
c0a596d6 | 237 | static int pxa27x_pkwr_gpio[] = { |
7facc2f9 | 238 | 13, 16, 17, 34, 36, 37, 38, 39, 90, 91, 93, 94, |
239 | 95, 96, 97, 98, 99, 100, 101, 102 | |
240 | }; | |
241 | ||
c0a596d6 | 242 | int keypad_set_wake(unsigned int on) |
243 | { | |
244 | unsigned int i, gpio, mask = 0; | |
245 | ||
246 | if (!on) { | |
247 | PKWR = 0; | |
248 | return 0; | |
249 | } | |
250 | ||
251 | for (i = 0; i < ARRAY_SIZE(pxa27x_pkwr_gpio); i++) { | |
252 | ||
253 | gpio = pxa27x_pkwr_gpio[i]; | |
254 | ||
255 | if (gpio_desc[gpio].config & MFP_LPM_CAN_WAKEUP) | |
256 | mask |= gpio_desc[gpio].mask; | |
257 | } | |
258 | ||
259 | PKWR = mask; | |
260 | return 0; | |
261 | } | |
262 | ||
99687114 RJ |
263 | #define PWER_WEMUX2_GPIO38 (1 << 16) |
264 | #define PWER_WEMUX2_GPIO53 (2 << 16) | |
265 | #define PWER_WEMUX2_GPIO40 (3 << 16) | |
266 | #define PWER_WEMUX2_GPIO36 (4 << 16) | |
267 | #define PWER_WEMUX2_MASK (7 << 16) | |
268 | #define PWER_WEMUX3_GPIO31 (1 << 19) | |
269 | #define PWER_WEMUX3_GPIO113 (2 << 19) | |
270 | #define PWER_WEMUX3_MASK (3 << 19) | |
271 | ||
272 | #define INIT_GPIO_DESC_MUXED(mux, gpio) \ | |
273 | do { \ | |
274 | gpio_desc[(gpio)].can_wakeup = 1; \ | |
275 | gpio_desc[(gpio)].mask = PWER_ ## mux ## _GPIO ##gpio; \ | |
276 | gpio_desc[(gpio)].mux_mask = PWER_ ## mux ## _MASK; \ | |
277 | } while (0) | |
278 | ||
5a3d9651 | 279 | static void __init pxa27x_mfp_init(void) |
7facc2f9 | 280 | { |
281 | int i, gpio; | |
282 | ||
ddd244dd | 283 | for (i = 0; i <= pxa_last_gpio; i++) { |
5a3d9651 EM |
284 | /* skip GPIO2, 5, 6, 7, 8, they are not |
285 | * valid pins allow configuration | |
286 | */ | |
287 | if (i == 2 || i == 5 || i == 6 || i == 7 || i == 8) | |
288 | continue; | |
7facc2f9 | 289 | |
5a3d9651 EM |
290 | gpio_desc[i].valid = 1; |
291 | } | |
7facc2f9 | 292 | |
5a3d9651 EM |
293 | /* Keypad GPIOs */ |
294 | for (i = 0; i < ARRAY_SIZE(pxa27x_pkwr_gpio); i++) { | |
295 | gpio = pxa27x_pkwr_gpio[i]; | |
296 | gpio_desc[gpio].can_wakeup = 1; | |
297 | gpio_desc[gpio].keypad_gpio = 1; | |
298 | gpio_desc[gpio].mask = 1 << i; | |
299 | } | |
7facc2f9 | 300 | |
5a3d9651 EM |
301 | /* Overwrite GPIO13 as a PWER wakeup source */ |
302 | for (i = 0; i <= 15; i++) { | |
303 | /* skip GPIO2, 5, 6, 7, 8 */ | |
304 | if (GPIO_bit(i) & 0x1e4) | |
305 | continue; | |
7facc2f9 | 306 | |
5a3d9651 EM |
307 | gpio_desc[i].can_wakeup = 1; |
308 | gpio_desc[i].mask = GPIO_bit(i); | |
309 | } | |
310 | ||
311 | gpio_desc[35].can_wakeup = 1; | |
312 | gpio_desc[35].mask = PWER_WE35; | |
313 | ||
99687114 RJ |
314 | INIT_GPIO_DESC_MUXED(WEMUX3, 31); |
315 | INIT_GPIO_DESC_MUXED(WEMUX3, 113); | |
316 | INIT_GPIO_DESC_MUXED(WEMUX2, 38); | |
317 | INIT_GPIO_DESC_MUXED(WEMUX2, 53); | |
318 | INIT_GPIO_DESC_MUXED(WEMUX2, 40); | |
319 | INIT_GPIO_DESC_MUXED(WEMUX2, 36); | |
5a3d9651 EM |
320 | } |
321 | #else | |
322 | static inline void pxa27x_mfp_init(void) {} | |
323 | #endif /* CONFIG_PXA27x */ | |
324 | ||
325 | #ifdef CONFIG_PM | |
326 | static unsigned long saved_gafr[2][4]; | |
327 | static unsigned long saved_gpdr[4]; | |
328 | ||
329 | static int pxa2xx_mfp_suspend(struct sys_device *d, pm_message_t state) | |
330 | { | |
331 | int i; | |
332 | ||
ddd244dd | 333 | for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) { |
7facc2f9 | 334 | |
5a3d9651 EM |
335 | saved_gafr[0][i] = GAFR_L(i); |
336 | saved_gafr[1][i] = GAFR_U(i); | |
337 | saved_gpdr[i] = GPDR(i * 32); | |
338 | ||
339 | GPDR(i * 32) = gpdr_lpm[i]; | |
7facc2f9 | 340 | } |
5a3d9651 EM |
341 | return 0; |
342 | } | |
7facc2f9 | 343 | |
5a3d9651 EM |
344 | static int pxa2xx_mfp_resume(struct sys_device *d) |
345 | { | |
346 | int i; | |
347 | ||
ddd244dd | 348 | for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) { |
5a3d9651 EM |
349 | GAFR_L(i) = saved_gafr[0][i]; |
350 | GAFR_U(i) = saved_gafr[1][i]; | |
351 | GPDR(i * 32) = saved_gpdr[i]; | |
352 | } | |
353 | PSSR = PSSR_RDH | PSSR_PH; | |
7facc2f9 | 354 | return 0; |
355 | } | |
5a3d9651 EM |
356 | #else |
357 | #define pxa2xx_mfp_suspend NULL | |
358 | #define pxa2xx_mfp_resume NULL | |
359 | #endif | |
360 | ||
361 | struct sysdev_class pxa2xx_mfp_sysclass = { | |
362 | .name = "mfp", | |
363 | .suspend = pxa2xx_mfp_suspend, | |
364 | .resume = pxa2xx_mfp_resume, | |
365 | }; | |
366 | ||
367 | static int __init pxa2xx_mfp_init(void) | |
368 | { | |
369 | int i; | |
370 | ||
e7f3c600 EM |
371 | if (!cpu_is_pxa2xx()) |
372 | return 0; | |
373 | ||
5a3d9651 EM |
374 | if (cpu_is_pxa25x()) |
375 | pxa25x_mfp_init(); | |
376 | ||
377 | if (cpu_is_pxa27x()) | |
378 | pxa27x_mfp_init(); | |
379 | ||
380 | /* initialize gafr_run[], pgsr_lpm[] from existing values */ | |
ddd244dd | 381 | for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) |
5a3d9651 EM |
382 | gpdr_lpm[i] = GPDR(i * 32); |
383 | ||
384 | return sysdev_class_register(&pxa2xx_mfp_sysclass); | |
385 | } | |
386 | postcore_initcall(pxa2xx_mfp_init); |