Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * PXA250/210 Power Management Routines | |
3 | * | |
4 | * Original code for the SA11x0: | |
5 | * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com> | |
6 | * | |
7 | * Modified for the PXA250 by Nicolas Pitre: | |
8 | * Copyright (c) 2002 Monta Vista Software, Inc. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License. | |
12 | */ | |
13 | #include <linux/config.h> | |
14 | #include <linux/init.h> | |
756c7b74 | 15 | #include <linux/module.h> |
1da177e4 LT |
16 | #include <linux/suspend.h> |
17 | #include <linux/errno.h> | |
18 | #include <linux/time.h> | |
19 | ||
20 | #include <asm/hardware.h> | |
21 | #include <asm/memory.h> | |
22 | #include <asm/system.h> | |
756c7b74 | 23 | #include <asm/arch/pm.h> |
1da177e4 LT |
24 | #include <asm/arch/pxa-regs.h> |
25 | #include <asm/arch/lubbock.h> | |
26 | #include <asm/mach/time.h> | |
27 | ||
28 | ||
29 | /* | |
30 | * Debug macros | |
31 | */ | |
32 | #undef DEBUG | |
33 | ||
1da177e4 LT |
34 | #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x |
35 | #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] | |
36 | ||
37 | #define RESTORE_GPLEVEL(n) do { \ | |
38 | GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \ | |
39 | GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \ | |
40 | } while (0) | |
41 | ||
42 | /* | |
43 | * List of global PXA peripheral registers to preserve. | |
44 | * More ones like CP and general purpose register values are preserved | |
45 | * with the stack pointer in sleep.S. | |
46 | */ | |
47 | enum { SLEEP_SAVE_START = 0, | |
48 | ||
49 | SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2, SLEEP_SAVE_GPLR3, | |
50 | SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, SLEEP_SAVE_GPDR3, | |
51 | SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, SLEEP_SAVE_GRER3, | |
52 | SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, SLEEP_SAVE_GFER3, | |
53 | SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3, | |
54 | ||
55 | SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U, | |
56 | SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U, | |
57 | SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U, | |
58 | SLEEP_SAVE_GAFR3_L, SLEEP_SAVE_GAFR3_U, | |
59 | ||
60 | SLEEP_SAVE_PSTR, | |
61 | ||
62 | SLEEP_SAVE_ICMR, | |
63 | SLEEP_SAVE_CKEN, | |
64 | ||
8775420d TP |
65 | #ifdef CONFIG_PXA27x |
66 | SLEEP_SAVE_MDREFR, | |
67 | SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER, | |
68 | SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR, | |
69 | #endif | |
70 | ||
1da177e4 LT |
71 | SLEEP_SAVE_CKSUM, |
72 | ||
73 | SLEEP_SAVE_SIZE | |
74 | }; | |
75 | ||
76 | ||
756c7b74 | 77 | int pxa_pm_enter(suspend_state_t state) |
1da177e4 LT |
78 | { |
79 | unsigned long sleep_save[SLEEP_SAVE_SIZE]; | |
80 | unsigned long checksum = 0; | |
81 | struct timespec delta, rtc; | |
82 | int i; | |
8775420d | 83 | extern void pxa_cpu_pm_enter(suspend_state_t state); |
1da177e4 LT |
84 | |
85 | #ifdef CONFIG_IWMMXT | |
86 | /* force any iWMMXt context to ram **/ | |
87 | iwmmxt_task_disable(NULL); | |
88 | #endif | |
89 | ||
90 | /* preserve current time */ | |
91 | rtc.tv_sec = RCNR; | |
92 | rtc.tv_nsec = 0; | |
93 | save_time_delta(&delta, &rtc); | |
94 | ||
95 | SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2); | |
96 | SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2); | |
97 | SAVE(GRER0); SAVE(GRER1); SAVE(GRER2); | |
98 | SAVE(GFER0); SAVE(GFER1); SAVE(GFER2); | |
99 | SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); | |
100 | ||
101 | SAVE(GAFR0_L); SAVE(GAFR0_U); | |
102 | SAVE(GAFR1_L); SAVE(GAFR1_U); | |
103 | SAVE(GAFR2_L); SAVE(GAFR2_U); | |
104 | ||
105 | #ifdef CONFIG_PXA27x | |
8775420d | 106 | SAVE(MDREFR); |
1da177e4 LT |
107 | SAVE(GPLR3); SAVE(GPDR3); SAVE(GRER3); SAVE(GFER3); SAVE(PGSR3); |
108 | SAVE(GAFR3_L); SAVE(GAFR3_U); | |
8775420d TP |
109 | SAVE(PWER); SAVE(PCFR); SAVE(PRER); |
110 | SAVE(PFER); SAVE(PKWR); | |
1da177e4 LT |
111 | #endif |
112 | ||
113 | SAVE(ICMR); | |
114 | ICMR = 0; | |
115 | ||
116 | SAVE(CKEN); | |
1da177e4 LT |
117 | SAVE(PSTR); |
118 | ||
119 | /* Note: wake up source are set up in each machine specific files */ | |
120 | ||
121 | /* clear GPIO transition detect bits */ | |
122 | GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2; | |
123 | #ifdef CONFIG_PXA27x | |
124 | GEDR3 = GEDR3; | |
125 | #endif | |
126 | ||
127 | /* Clear sleep reset status */ | |
128 | RCSR = RCSR_SMR; | |
129 | ||
1da177e4 LT |
130 | /* before sleeping, calculate and save a checksum */ |
131 | for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++) | |
132 | checksum += sleep_save[i]; | |
133 | sleep_save[SLEEP_SAVE_CKSUM] = checksum; | |
134 | ||
135 | /* *** go zzz *** */ | |
8775420d | 136 | pxa_cpu_pm_enter(state); |
1da177e4 | 137 | |
36c5ed23 RK |
138 | cpu_init(); |
139 | ||
1da177e4 LT |
140 | /* after sleeping, validate the checksum */ |
141 | checksum = 0; | |
142 | for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++) | |
143 | checksum += sleep_save[i]; | |
144 | ||
145 | /* if invalid, display message and wait for a hardware reset */ | |
146 | if (checksum != sleep_save[SLEEP_SAVE_CKSUM]) { | |
147 | #ifdef CONFIG_ARCH_LUBBOCK | |
148 | LUB_HEXLED = 0xbadbadc5; | |
149 | #endif | |
150 | while (1) | |
8775420d | 151 | pxa_cpu_pm_enter(state); |
1da177e4 LT |
152 | } |
153 | ||
154 | /* ensure not to come back here if it wasn't intended */ | |
155 | PSPR = 0; | |
156 | ||
157 | /* restore registers */ | |
158 | RESTORE(GAFR0_L); RESTORE(GAFR0_U); | |
159 | RESTORE(GAFR1_L); RESTORE(GAFR1_U); | |
160 | RESTORE(GAFR2_L); RESTORE(GAFR2_U); | |
161 | RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); RESTORE_GPLEVEL(2); | |
162 | RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2); | |
163 | RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2); | |
164 | RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2); | |
165 | RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); | |
166 | ||
167 | #ifdef CONFIG_PXA27x | |
8775420d | 168 | RESTORE(MDREFR); |
1da177e4 LT |
169 | RESTORE(GAFR3_L); RESTORE(GAFR3_U); RESTORE_GPLEVEL(3); |
170 | RESTORE(GPDR3); RESTORE(GRER3); RESTORE(GFER3); RESTORE(PGSR3); | |
8775420d TP |
171 | RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER); |
172 | RESTORE(PFER); RESTORE(PKWR); | |
1da177e4 LT |
173 | #endif |
174 | ||
175 | PSSR = PSSR_RDH | PSSR_PH; | |
176 | ||
177 | RESTORE(CKEN); | |
178 | ||
179 | ICLR = 0; | |
180 | ICCR = 1; | |
181 | RESTORE(ICMR); | |
182 | ||
183 | RESTORE(PSTR); | |
184 | ||
185 | /* restore current time */ | |
186 | rtc.tv_sec = RCNR; | |
187 | restore_time_delta(&delta, &rtc); | |
188 | ||
189 | #ifdef DEBUG | |
190 | printk(KERN_DEBUG "*** made it back from resume\n"); | |
191 | #endif | |
192 | ||
193 | return 0; | |
194 | } | |
195 | ||
756c7b74 RP |
196 | EXPORT_SYMBOL_GPL(pxa_pm_enter); |
197 | ||
1da177e4 LT |
198 | unsigned long sleep_phys_sp(void *sp) |
199 | { | |
200 | return virt_to_phys(sp); | |
201 | } | |
202 | ||
203 | /* | |
204 | * Called after processes are frozen, but before we shut down devices. | |
205 | */ | |
756c7b74 | 206 | int pxa_pm_prepare(suspend_state_t state) |
1da177e4 | 207 | { |
8775420d TP |
208 | extern int pxa_cpu_pm_prepare(suspend_state_t state); |
209 | ||
210 | return pxa_cpu_pm_prepare(state); | |
1da177e4 LT |
211 | } |
212 | ||
756c7b74 RP |
213 | EXPORT_SYMBOL_GPL(pxa_pm_prepare); |
214 | ||
1da177e4 LT |
215 | /* |
216 | * Called after devices are re-setup, but before processes are thawed. | |
217 | */ | |
756c7b74 | 218 | int pxa_pm_finish(suspend_state_t state) |
1da177e4 LT |
219 | { |
220 | return 0; | |
221 | } | |
222 | ||
756c7b74 RP |
223 | EXPORT_SYMBOL_GPL(pxa_pm_finish); |
224 | ||
1da177e4 LT |
225 | /* |
226 | * Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk. | |
227 | */ | |
228 | static struct pm_ops pxa_pm_ops = { | |
229 | .pm_disk_mode = PM_DISK_FIRMWARE, | |
230 | .prepare = pxa_pm_prepare, | |
231 | .enter = pxa_pm_enter, | |
232 | .finish = pxa_pm_finish, | |
233 | }; | |
234 | ||
235 | static int __init pxa_pm_init(void) | |
236 | { | |
237 | pm_set_ops(&pxa_pm_ops); | |
238 | return 0; | |
239 | } | |
240 | ||
756c7b74 | 241 | device_initcall(pxa_pm_init); |