[deliverable/linux.git] / arch / arm / mach-pxa / pxa25x.c

/*
 *  linux/arch/arm/mach-pxa/pxa25x.c
 *
 *  Author:	Nicolas Pitre
 *  Created:	Jun 15, 2001
 *  Copyright:	MontaVista Software Inc.
 *
 * Code specific to PXA21x/25x/26x variants.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Since this file should be linked before any other machine specific file,
 * the __initcall() here will be executed first.  This serves as default
 * initialization stuff for PXA machines which can be overridden later if
 * need be.
 */
#include <linux/gpio.h>
#include <linux/gpio-pxa.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/suspend.h>
#include <linux/syscore_ops.h>
#include <linux/irq.h>
#include <linux/gpio.h>

#include <asm/mach/map.h>
#include <asm/suspend.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <mach/pxa25x.h>
#include <mach/reset.h>
#include <mach/pm.h>
#include <mach/dma.h>
#include <mach/smemc.h>

#include "generic.h"
#include "devices.h"
#include "clock.h"

/*
 * Various clock factors driven by the CCCR register.
 */

/* Crystal Frequency to Memory Frequency Multiplier (L) */
static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };

/* Memory Frequency to Run Mode Frequency Multiplier (M) */
static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };

/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
/* Note: we store the value N * 2 here. */
static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };

/* Crystal clock */
#define BASE_CLK	3686400

/*
 * Get the clock frequency as reflected by CCCR and the turbo flag.
 * We assume these values have been applied via a fcs.
 * If info is not 0 we also display the current settings.
 */
unsigned int pxa25x_get_clk_frequency_khz(int info)
{
	unsigned long cccr, turbo;
	unsigned int l, L, m, M, n2, N;

	cccr = CCCR;
	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );

	l  =  L_clk_mult[(cccr >> 0) & 0x1f];
	m  =  M_clk_mult[(cccr >> 5) & 0x03];
	n2 = N2_clk_mult[(cccr >> 7) & 0x07];

	L = l * BASE_CLK;
	M = m * L;
	N = n2 * M / 2;

	if(info)
	{
		L += 5000;
		printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
			L / 1000000, (L % 1000000) / 10000, l );
		M += 5000;
		printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
			M / 1000000, (M % 1000000) / 10000, m );
		N += 5000;
		printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
			N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
			(turbo & 1) ? "" : "in" );
	}

	return (turbo & 1) ? (N/1000) : (M/1000);
}

static unsigned long clk_pxa25x_mem_getrate(struct clk *clk)
{
	return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK;
}

static const struct clkops clk_pxa25x_mem_ops = {
	.enable		= clk_dummy_enable,
	.disable	= clk_dummy_disable,
	.getrate	= clk_pxa25x_mem_getrate,
};

static const struct clkops clk_pxa25x_lcd_ops = {
	.enable		= clk_pxa2xx_cken_enable,
	.disable	= clk_pxa2xx_cken_disable,
	.getrate	= clk_pxa25x_mem_getrate,
};

static unsigned long gpio12_config_32k[] = {
	GPIO12_32KHz,
};

static unsigned long gpio12_config_gpio[] = {
	GPIO12_GPIO,
};

static void clk_gpio12_enable(struct clk *clk)
{
	pxa2xx_mfp_config(gpio12_config_32k, 1);
}

static void clk_gpio12_disable(struct clk *clk)
{
	pxa2xx_mfp_config(gpio12_config_gpio, 1);
}

static const struct clkops clk_pxa25x_gpio12_ops = {
	.enable         = clk_gpio12_enable,
	.disable        = clk_gpio12_disable,
};

static unsigned long gpio11_config_3m6[] = {
	GPIO11_3_6MHz,
};

static unsigned long gpio11_config_gpio[] = {
	GPIO11_GPIO,
};

static void clk_gpio11_enable(struct clk *clk)
{
	pxa2xx_mfp_config(gpio11_config_3m6, 1);
}

static void clk_gpio11_disable(struct clk *clk)
{
	pxa2xx_mfp_config(gpio11_config_gpio, 1);
}

static const struct clkops clk_pxa25x_gpio11_ops = {
	.enable         = clk_gpio11_enable,
	.disable        = clk_gpio11_disable,
};

/*
 * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
 * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
 * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
 */

/*
 * PXA 2xx clock declarations.
 */
static DEFINE_PXA2_CKEN(pxa25x_hwuart, HWUART, 14745600, 1);
static DEFINE_PXA2_CKEN(pxa25x_ffuart, FFUART, 14745600, 1);
static DEFINE_PXA2_CKEN(pxa25x_btuart, BTUART, 14745600, 1);
static DEFINE_PXA2_CKEN(pxa25x_stuart, STUART, 14745600, 1);
static DEFINE_PXA2_CKEN(pxa25x_usb, USB, 47923000, 5);
static DEFINE_PXA2_CKEN(pxa25x_mmc, MMC, 19169000, 0);
static DEFINE_PXA2_CKEN(pxa25x_i2c, I2C, 31949000, 0);
static DEFINE_PXA2_CKEN(pxa25x_ssp, SSP, 3686400, 0);
static DEFINE_PXA2_CKEN(pxa25x_nssp, NSSP, 3686400, 0);
static DEFINE_PXA2_CKEN(pxa25x_assp, ASSP, 3686400, 0);
static DEFINE_PXA2_CKEN(pxa25x_pwm0, PWM0, 3686400, 0);
static DEFINE_PXA2_CKEN(pxa25x_pwm1, PWM1, 3686400, 0);
static DEFINE_PXA2_CKEN(pxa25x_ac97, AC97, 24576000, 0);
static DEFINE_PXA2_CKEN(pxa25x_i2s, I2S, 14745600, 0);
static DEFINE_PXA2_CKEN(pxa25x_ficp, FICP, 47923000, 0);

static DEFINE_CK(pxa25x_lcd, LCD, &clk_pxa25x_lcd_ops);
static DEFINE_CLK(pxa25x_gpio11, &clk_pxa25x_gpio11_ops, 3686400, 0);
static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0);
static DEFINE_CLK(pxa25x_mem, &clk_pxa25x_mem_ops, 0, 0);

static struct clk_lookup pxa25x_clkregs[] = {
	INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL),
	INIT_CLKREG(&clk_pxa25x_ffuart, "pxa2xx-uart.0", NULL),
	INIT_CLKREG(&clk_pxa25x_btuart, "pxa2xx-uart.1", NULL),
	INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-uart.2", NULL),
	INIT_CLKREG(&clk_pxa25x_usb, "pxa25x-udc", NULL),
	INIT_CLKREG(&clk_pxa25x_mmc, "pxa2xx-mci.0", NULL),
	INIT_CLKREG(&clk_pxa25x_i2c, "pxa2xx-i2c.0", NULL),
	INIT_CLKREG(&clk_pxa25x_ssp, "pxa25x-ssp.0", NULL),
	INIT_CLKREG(&clk_pxa25x_nssp, "pxa25x-nssp.1", NULL),
	INIT_CLKREG(&clk_pxa25x_assp, "pxa25x-nssp.2", NULL),
	INIT_CLKREG(&clk_pxa25x_pwm0, "pxa25x-pwm.0", NULL),
	INIT_CLKREG(&clk_pxa25x_pwm1, "pxa25x-pwm.1", NULL),
	INIT_CLKREG(&clk_pxa25x_i2s, "pxa2xx-i2s", NULL),
	INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-ir", "UARTCLK"),
	INIT_CLKREG(&clk_pxa25x_ficp, "pxa2xx-ir", "FICPCLK"),
	INIT_CLKREG(&clk_pxa25x_ac97, NULL, "AC97CLK"),
	INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"),
	INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
	INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL),
};

static struct clk_lookup pxa25x_hwuart_clkreg =
	INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL);

#ifdef CONFIG_PM

#define SAVE(x)		sleep_save[SLEEP_SAVE_##x] = x
#define RESTORE(x)	x = sleep_save[SLEEP_SAVE_##x]

/*
 * List of global PXA peripheral registers to preserve.
 * More ones like CP and general purpose register values are preserved
 * with the stack pointer in sleep.S.
 */
enum {
	SLEEP_SAVE_PSTR,
	SLEEP_SAVE_COUNT
};


static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
{
	SAVE(PSTR);
}

static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
{
	RESTORE(PSTR);
}

static void pxa25x_cpu_pm_enter(suspend_state_t state)
{
	/* Clear reset status */
	RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;

	switch (state) {
	case PM_SUSPEND_MEM:
		cpu_suspend(PWRMODE_SLEEP, pxa25x_finish_suspend);
		break;
	}
}

static int pxa25x_cpu_pm_prepare(void)
{
	/* set resume return address */
	PSPR = virt_to_phys(cpu_resume);
	return 0;
}

static void pxa25x_cpu_pm_finish(void)
{
	/* ensure not to come back here if it wasn't intended */
	PSPR = 0;
}

static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
	.save_count	= SLEEP_SAVE_COUNT,
	.valid		= suspend_valid_only_mem,
	.save		= pxa25x_cpu_pm_save,
	.restore	= pxa25x_cpu_pm_restore,
	.enter		= pxa25x_cpu_pm_enter,
	.prepare	= pxa25x_cpu_pm_prepare,
	.finish		= pxa25x_cpu_pm_finish,
};

static void __init pxa25x_init_pm(void)
{
	pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
}
#else
static inline void pxa25x_init_pm(void) {}
#endif

/* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
 */

static int pxa25x_set_wake(struct irq_data *d, unsigned int on)
{
	int gpio = pxa_irq_to_gpio(d->irq);
	uint32_t mask = 0;

	if (gpio >= 0 && gpio < 85)
		return gpio_set_wake(gpio, on);

	if (d->irq == IRQ_RTCAlrm) {
		mask = PWER_RTC;
		goto set_pwer;
	}

	return -EINVAL;

set_pwer:
	if (on)
		PWER |= mask;
	else
		PWER &=~mask;

	return 0;
}

void __init pxa25x_init_irq(void)
{
	pxa_init_irq(32, pxa25x_set_wake);
}

#ifdef CONFIG_CPU_PXA26x
void __init pxa26x_init_irq(void)
{
	pxa_init_irq(32, pxa25x_set_wake);
}
#endif

static struct map_desc pxa25x_io_desc[] __initdata = {
	{	/* Mem Ctl */
		.virtual	= (unsigned long)SMEMC_VIRT,
		.pfn		= __phys_to_pfn(PXA2XX_SMEMC_BASE),
		.length		= 0x00200000,
		.type		= MT_DEVICE
	},
};

void __init pxa25x_map_io(void)
{
	pxa_map_io();
	iotable_init(ARRAY_AND_SIZE(pxa25x_io_desc));
	pxa25x_get_clk_frequency_khz(1);
}

static struct platform_device *pxa25x_devices[] __initdata = {
	&pxa25x_device_udc,
	&pxa_device_pmu,
	&pxa_device_i2s,
	&sa1100_device_rtc,
	&pxa25x_device_ssp,
	&pxa25x_device_nssp,
	&pxa25x_device_assp,
	&pxa25x_device_pwm0,
	&pxa25x_device_pwm1,
	&pxa_device_asoc_platform,
};

static int __init pxa25x_init(void)
{
	int ret = 0;

	if (cpu_is_pxa25x()) {

		reset_status = RCSR;

		clkdev_add_table(pxa25x_clkregs, ARRAY_SIZE(pxa25x_clkregs));

		if ((ret = pxa_init_dma(IRQ_DMA, 16)))
			return ret;

		pxa25x_init_pm();

		register_syscore_ops(&pxa_irq_syscore_ops);
		register_syscore_ops(&pxa2xx_mfp_syscore_ops);
		register_syscore_ops(&pxa_gpio_syscore_ops);
		register_syscore_ops(&pxa2xx_clock_syscore_ops);

		ret = platform_add_devices(pxa25x_devices,
					   ARRAY_SIZE(pxa25x_devices));
		if (ret)
			return ret;
	}

	/* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */
	if (cpu_is_pxa255())
		clkdev_add(&pxa25x_hwuart_clkreg);

	return ret;
}

postcore_initcall(pxa25x_init);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-pxa/pxa25x.c
	3	*
	4	* Author: Nicolas Pitre
	5	* Created: Jun 15, 2001
	6	* Copyright: MontaVista Software Inc.
	7	*
	8	* Code specific to PXA21x/25x/26x variants.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*
	14	* Since this file should be linked before any other machine specific file,
	15	* the __initcall() here will be executed first. This serves as default
	16	* initialization stuff for PXA machines which can be overridden later if
	17	* need be.
	18	*/
2f8163ba	19	#include <linux/gpio.h>
157d2644	20	#include <linux/gpio-pxa.h>
1da177e4 LT	21	#include <linux/module.h>
	22	#include <linux/kernel.h>
	23	#include <linux/init.h>
34f3231f	24	#include <linux/platform_device.h>
95d9ffbe	25	#include <linux/suspend.h>
2eaa03b5	26	#include <linux/syscore_ops.h>
a3f4c927	27	#include <linux/irq.h>
f55be1bf	28	#include <linux/gpio.h>
1da177e4	29
851982c1	30	#include <asm/mach/map.h>
2c74a0ce	31	#include <asm/suspend.h>
a09e64fb RK	32	#include <mach/hardware.h>
a09e64fb RK	33	#include <mach/irqs.h>
51c62982	34	#include <mach/pxa25x.h>
afd2fc02	35	#include <mach/reset.h>
a09e64fb RK	36	#include <mach/pm.h>
a09e64fb RK	37	#include <mach/dma.h>
ad68bb9f	38	#include <mach/smemc.h>
1da177e4 LT	39
1da177e4 LT	40	#include "generic.h"
46c41e62	41	#include "devices.h"
a6dba20c	42	#include "clock.h"
1da177e4 LT	43
	44	/*
	45	* Various clock factors driven by the CCCR register.
	46	*/
	47
	48	/* Crystal Frequency to Memory Frequency Multiplier (L) */
	49	static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
	50
	51	/* Memory Frequency to Run Mode Frequency Multiplier (M) */
	52	static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
	53
	54	/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
	55	/* Note: we store the value N * 2 here. */
	56	static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
	57
	58	/* Crystal clock */
	59	#define BASE_CLK 3686400
	60
	61	/*
	62	* Get the clock frequency as reflected by CCCR and the turbo flag.
	63	* We assume these values have been applied via a fcs.
	64	* If info is not 0 we also display the current settings.
	65	*/
15a40333	66	unsigned int pxa25x_get_clk_frequency_khz(int info)
1da177e4 LT	67	{
	68	unsigned long cccr, turbo;
	69	unsigned int l, L, m, M, n2, N;
	70
	71	cccr = CCCR;
	72	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
	73
	74	l = L_clk_mult[(cccr >> 0) & 0x1f];
	75	m = M_clk_mult[(cccr >> 5) & 0x03];
	76	n2 = N2_clk_mult[(cccr >> 7) & 0x07];
	77
	78	L = l * BASE_CLK;
	79	M = m * L;
	80	N = n2 * M / 2;
	81
	82	if(info)
	83	{
	84	L += 5000;
	85	printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
	86	L / 1000000, (L % 1000000) / 10000, l );
	87	M += 5000;
	88	printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
	89	M / 1000000, (M % 1000000) / 10000, m );
	90	N += 5000;
	91	printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
	92	N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
	93	(turbo & 1) ? "" : "in" );
	94	}
	95
	96	return (turbo & 1) ? (N/1000) : (M/1000);
	97	}
	98
2a125dd5	99	static unsigned long clk_pxa25x_mem_getrate(struct clk *clk)
1da177e4	100	{
2a125dd5	101	return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK;
1da177e4 LT	102	}
1da177e4 LT	103
2a125dd5 EM	104	static const struct clkops clk_pxa25x_mem_ops = {
	105	.enable = clk_dummy_enable,
	106	.disable = clk_dummy_disable,
	107	.getrate = clk_pxa25x_mem_getrate,
	108	};
a6dba20c RK	109
a6dba20c RK	110	static const struct clkops clk_pxa25x_lcd_ops = {
4029813c EM	111	.enable = clk_pxa2xx_cken_enable,
4029813c EM	112	.disable = clk_pxa2xx_cken_disable,
2a125dd5	113	.getrate = clk_pxa25x_mem_getrate,
a6dba20c RK	114	};
a6dba20c RK	115
ed847782 IM	116	static unsigned long gpio12_config_32k[] = {
	117	GPIO12_32KHz,
	118	};
	119
	120	static unsigned long gpio12_config_gpio[] = {
	121	GPIO12_GPIO,
	122	};
	123
	124	static void clk_gpio12_enable(struct clk *clk)
	125	{
	126	pxa2xx_mfp_config(gpio12_config_32k, 1);
	127	}
	128
	129	static void clk_gpio12_disable(struct clk *clk)
	130	{
	131	pxa2xx_mfp_config(gpio12_config_gpio, 1);
	132	}
	133
	134	static const struct clkops clk_pxa25x_gpio12_ops = {
	135	.enable = clk_gpio12_enable,
	136	.disable = clk_gpio12_disable,
	137	};
	138
13f75582 IM	139	static unsigned long gpio11_config_3m6[] = {
	140	GPIO11_3_6MHz,
	141	};
	142
	143	static unsigned long gpio11_config_gpio[] = {
	144	GPIO11_GPIO,
	145	};
	146
	147	static void clk_gpio11_enable(struct clk *clk)
	148	{
	149	pxa2xx_mfp_config(gpio11_config_3m6, 1);
	150	}
	151
	152	static void clk_gpio11_disable(struct clk *clk)
	153	{
	154	pxa2xx_mfp_config(gpio11_config_gpio, 1);
	155	}
	156
	157	static const struct clkops clk_pxa25x_gpio11_ops = {
	158	.enable = clk_gpio11_enable,
	159	.disable = clk_gpio11_disable,
	160	};
	161
a6dba20c RK	162	/*
	163	* 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
	164	* 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
	165	* 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
	166	*/
e01dbdb4	167
bdb08cb2	168	/*
c1ed406c	169	* PXA 2xx clock declarations.
bdb08cb2	170	*/
4029813c EM	171	static DEFINE_PXA2_CKEN(pxa25x_hwuart, HWUART, 14745600, 1);
	172	static DEFINE_PXA2_CKEN(pxa25x_ffuart, FFUART, 14745600, 1);
	173	static DEFINE_PXA2_CKEN(pxa25x_btuart, BTUART, 14745600, 1);
	174	static DEFINE_PXA2_CKEN(pxa25x_stuart, STUART, 14745600, 1);
	175	static DEFINE_PXA2_CKEN(pxa25x_usb, USB, 47923000, 5);
	176	static DEFINE_PXA2_CKEN(pxa25x_mmc, MMC, 19169000, 0);
	177	static DEFINE_PXA2_CKEN(pxa25x_i2c, I2C, 31949000, 0);
	178	static DEFINE_PXA2_CKEN(pxa25x_ssp, SSP, 3686400, 0);
	179	static DEFINE_PXA2_CKEN(pxa25x_nssp, NSSP, 3686400, 0);
	180	static DEFINE_PXA2_CKEN(pxa25x_assp, ASSP, 3686400, 0);
	181	static DEFINE_PXA2_CKEN(pxa25x_pwm0, PWM0, 3686400, 0);
	182	static DEFINE_PXA2_CKEN(pxa25x_pwm1, PWM1, 3686400, 0);
	183	static DEFINE_PXA2_CKEN(pxa25x_ac97, AC97, 24576000, 0);
	184	static DEFINE_PXA2_CKEN(pxa25x_i2s, I2S, 14745600, 0);
	185	static DEFINE_PXA2_CKEN(pxa25x_ficp, FICP, 47923000, 0);
	186
8c3abc7d	187	static DEFINE_CK(pxa25x_lcd, LCD, &clk_pxa25x_lcd_ops);
8c3abc7d RK	188	static DEFINE_CLK(pxa25x_gpio11, &clk_pxa25x_gpio11_ops, 3686400, 0);
8c3abc7d RK	189	static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0);
2a125dd5	190	static DEFINE_CLK(pxa25x_mem, &clk_pxa25x_mem_ops, 0, 0);
8c3abc7d RK	191
	192	static struct clk_lookup pxa25x_clkregs[] = {
	193	INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL),
	194	INIT_CLKREG(&clk_pxa25x_ffuart, "pxa2xx-uart.0", NULL),
	195	INIT_CLKREG(&clk_pxa25x_btuart, "pxa2xx-uart.1", NULL),
	196	INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-uart.2", NULL),
	197	INIT_CLKREG(&clk_pxa25x_usb, "pxa25x-udc", NULL),
	198	INIT_CLKREG(&clk_pxa25x_mmc, "pxa2xx-mci.0", NULL),
	199	INIT_CLKREG(&clk_pxa25x_i2c, "pxa2xx-i2c.0", NULL),
	200	INIT_CLKREG(&clk_pxa25x_ssp, "pxa25x-ssp.0", NULL),
	201	INIT_CLKREG(&clk_pxa25x_nssp, "pxa25x-nssp.1", NULL),
	202	INIT_CLKREG(&clk_pxa25x_assp, "pxa25x-nssp.2", NULL),
	203	INIT_CLKREG(&clk_pxa25x_pwm0, "pxa25x-pwm.0", NULL),
	204	INIT_CLKREG(&clk_pxa25x_pwm1, "pxa25x-pwm.1", NULL),
	205	INIT_CLKREG(&clk_pxa25x_i2s, "pxa2xx-i2s", NULL),
	206	INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-ir", "UARTCLK"),
	207	INIT_CLKREG(&clk_pxa25x_ficp, "pxa2xx-ir", "FICPCLK"),
	208	INIT_CLKREG(&clk_pxa25x_ac97, NULL, "AC97CLK"),
	209	INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"),
	210	INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
2a125dd5	211	INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL),
a6dba20c RK	212	};
a6dba20c RK	213
4029813c EM	214	static struct clk_lookup pxa25x_hwuart_clkreg =
	215	INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL);
	216
a8fa3f0c	217	#ifdef CONFIG_PM
8775420d	218
711be5cc EM	219	#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
	220	#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
	221
711be5cc EM	222	/*
	223	* List of global PXA peripheral registers to preserve.
	224	* More ones like CP and general purpose register values are preserved
	225	* with the stack pointer in sleep.S.
	226	*/
5a3d9651	227	enum {
711be5cc	228	SLEEP_SAVE_PSTR,
649de51b	229	SLEEP_SAVE_COUNT
711be5cc EM	230	};
	231
	232
	233	static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
	234	{
711be5cc EM	235	SAVE(PSTR);
	236	}
	237
	238	static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
	239	{
711be5cc EM	240	RESTORE(PSTR);
	241	}
	242
	243	static void pxa25x_cpu_pm_enter(suspend_state_t state)
8775420d	244	{
dc38e2ad RK	245	/* Clear reset status */
	246	RCSR = RCSR_HWR \| RCSR_WDR \| RCSR_SMR \| RCSR_GPR;
	247
8775420d TP	248	switch (state) {
8775420d TP	249	case PM_SUSPEND_MEM:
2c74a0ce	250	cpu_suspend(PWRMODE_SLEEP, pxa25x_finish_suspend);
8775420d TP	251	break;
	252	}
	253	}
a8fa3f0c	254
4104980a RK	255	static int pxa25x_cpu_pm_prepare(void)
	256	{
	257	/* set resume return address */
4f5ad99b	258	PSPR = virt_to_phys(cpu_resume);
4104980a RK	259	return 0;
	260	}
	261
	262	static void pxa25x_cpu_pm_finish(void)
	263	{
	264	/* ensure not to come back here if it wasn't intended */
	265	PSPR = 0;
	266	}
	267
711be5cc	268	static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
649de51b	269	.save_count = SLEEP_SAVE_COUNT,
26398a70	270	.valid = suspend_valid_only_mem,
711be5cc EM	271	.save = pxa25x_cpu_pm_save,
	272	.restore = pxa25x_cpu_pm_restore,
	273	.enter = pxa25x_cpu_pm_enter,
4104980a RK	274	.prepare = pxa25x_cpu_pm_prepare,
4104980a RK	275	.finish = pxa25x_cpu_pm_finish,
e176bb05	276	};
711be5cc EM	277
	278	static void __init pxa25x_init_pm(void)
	279	{
	280	pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
	281	}
f79299ca	282	#else
f79299ca	283	static inline void pxa25x_init_pm(void) {}
a8fa3f0c	284	#endif
e176bb05	285
c95530c7	286	/* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
	287	*/
	288
a3f4c927	289	static int pxa25x_set_wake(struct irq_data *d, unsigned int on)
c95530c7	290	{
4929f5a8	291	int gpio = pxa_irq_to_gpio(d->irq);
c0a596d6	292	uint32_t mask = 0;
	293
	294	if (gpio >= 0 && gpio < 85)
	295	return gpio_set_wake(gpio, on);
c95530c7	296
a3f4c927	297	if (d->irq == IRQ_RTCAlrm) {
c95530c7	298	mask = PWER_RTC;
	299	goto set_pwer;
	300	}
	301
	302	return -EINVAL;
	303
	304	set_pwer:
	305	if (on)
	306	PWER \|= mask;
	307	else
	308	PWER &=~mask;
	309
	310	return 0;
	311	}
	312
cd49104d EM	313	void __init pxa25x_init_irq(void)
cd49104d EM	314	{
b9e25ace	315	pxa_init_irq(32, pxa25x_set_wake);
cd49104d EM	316	}
cd49104d EM	317
067455aa EM	318	#ifdef CONFIG_CPU_PXA26x
	319	void __init pxa26x_init_irq(void)
	320	{
	321	pxa_init_irq(32, pxa25x_set_wake);
067455aa EM	322	}
	323	#endif
	324
851982c1 MV	325	static struct map_desc pxa25x_io_desc[] __initdata = {
851982c1 MV	326	{ /* Mem Ctl */
97b09da4	327	.virtual = (unsigned long)SMEMC_VIRT,
ad68bb9f	328	.pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE),
851982c1 MV	329	.length = 0x00200000,
	330	.type = MT_DEVICE
	331	},
	332	};
	333
	334	void __init pxa25x_map_io(void)
	335	{
	336	pxa_map_io();
	337	iotable_init(ARRAY_AND_SIZE(pxa25x_io_desc));
	338	pxa25x_get_clk_frequency_khz(1);
	339	}
	340
34f3231f	341	static struct platform_device *pxa25x_devices[] __initdata = {
7a857620	342	&pxa25x_device_udc,
09a5358d	343	&pxa_device_pmu,
e09d02e1	344	&pxa_device_i2s,
72493146	345	&sa1100_device_rtc,
d8e0db11	346	&pxa25x_device_ssp,
	347	&pxa25x_device_nssp,
	348	&pxa25x_device_assp,
75540c1a	349	&pxa25x_device_pwm0,
75540c1a	350	&pxa25x_device_pwm1,
ea73e752	351	&pxa_device_asoc_platform,
34f3231f RK	352	};
34f3231f RK	353
e176bb05 RK	354	static int __init pxa25x_init(void)
e176bb05 RK	355	{
2eaa03b5	356	int ret = 0;
f53f066c	357
0ffcbfd5	358	if (cpu_is_pxa25x()) {
04fef228 EM	359
	360	reset_status = RCSR;
	361
0a0300dc	362	clkdev_add_table(pxa25x_clkregs, ARRAY_SIZE(pxa25x_clkregs));
a6dba20c	363
fef1f99a	364	if ((ret = pxa_init_dma(IRQ_DMA, 16)))
f53f066c	365	return ret;
f79299ca	366
711be5cc	367	pxa25x_init_pm();
f79299ca	368
2eaa03b5 RW	369	register_syscore_ops(&pxa_irq_syscore_ops);
	370	register_syscore_ops(&pxa2xx_mfp_syscore_ops);
	371	register_syscore_ops(&pxa_gpio_syscore_ops);
	372	register_syscore_ops(&pxa2xx_clock_syscore_ops);
c0165504	373
34f3231f RK	374	ret = platform_add_devices(pxa25x_devices,
34f3231f RK	375	ARRAY_SIZE(pxa25x_devices));
c0165504	376	if (ret)
c0165504	377	return ret;
e176bb05	378	}
c0165504	379
2b12797c	380	/* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */
cc155c6f	381	if (cpu_is_pxa255())
0a0300dc	382	clkdev_add(&pxa25x_hwuart_clkreg);
34f3231f RK	383
34f3231f RK	384	return ret;
e176bb05 RK	385	}
e176bb05 RK	386
1c104e0e	387	postcore_initcall(pxa25x_init);