Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-pxa/pxa25x.c | |
3 | * | |
4 | * Author: Nicolas Pitre | |
5 | * Created: Jun 15, 2001 | |
6 | * Copyright: MontaVista Software Inc. | |
7 | * | |
8 | * Code specific to PXA21x/25x/26x variants. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * Since this file should be linked before any other machine specific file, | |
15 | * the __initcall() here will be executed first. This serves as default | |
16 | * initialization stuff for PXA machines which can be overridden later if | |
17 | * need be. | |
18 | */ | |
19 | #include <linux/module.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/init.h> | |
34f3231f | 22 | #include <linux/platform_device.h> |
95d9ffbe | 23 | #include <linux/suspend.h> |
c0165504 | 24 | #include <linux/sysdev.h> |
1da177e4 | 25 | |
a09e64fb RK |
26 | #include <mach/hardware.h> |
27 | #include <mach/irqs.h> | |
28 | #include <mach/pxa-regs.h> | |
29 | #include <mach/pxa2xx-regs.h> | |
30 | #include <mach/mfp-pxa25x.h> | |
31 | #include <mach/pm.h> | |
32 | #include <mach/dma.h> | |
1da177e4 LT |
33 | |
34 | #include "generic.h" | |
46c41e62 | 35 | #include "devices.h" |
a6dba20c | 36 | #include "clock.h" |
1da177e4 LT |
37 | |
38 | /* | |
39 | * Various clock factors driven by the CCCR register. | |
40 | */ | |
41 | ||
42 | /* Crystal Frequency to Memory Frequency Multiplier (L) */ | |
43 | static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, }; | |
44 | ||
45 | /* Memory Frequency to Run Mode Frequency Multiplier (M) */ | |
46 | static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 }; | |
47 | ||
48 | /* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */ | |
49 | /* Note: we store the value N * 2 here. */ | |
50 | static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 }; | |
51 | ||
52 | /* Crystal clock */ | |
53 | #define BASE_CLK 3686400 | |
54 | ||
55 | /* | |
56 | * Get the clock frequency as reflected by CCCR and the turbo flag. | |
57 | * We assume these values have been applied via a fcs. | |
58 | * If info is not 0 we also display the current settings. | |
59 | */ | |
15a40333 | 60 | unsigned int pxa25x_get_clk_frequency_khz(int info) |
1da177e4 LT |
61 | { |
62 | unsigned long cccr, turbo; | |
63 | unsigned int l, L, m, M, n2, N; | |
64 | ||
65 | cccr = CCCR; | |
66 | asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) ); | |
67 | ||
68 | l = L_clk_mult[(cccr >> 0) & 0x1f]; | |
69 | m = M_clk_mult[(cccr >> 5) & 0x03]; | |
70 | n2 = N2_clk_mult[(cccr >> 7) & 0x07]; | |
71 | ||
72 | L = l * BASE_CLK; | |
73 | M = m * L; | |
74 | N = n2 * M / 2; | |
75 | ||
76 | if(info) | |
77 | { | |
78 | L += 5000; | |
79 | printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n", | |
80 | L / 1000000, (L % 1000000) / 10000, l ); | |
81 | M += 5000; | |
82 | printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n", | |
83 | M / 1000000, (M % 1000000) / 10000, m ); | |
84 | N += 5000; | |
85 | printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n", | |
86 | N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5, | |
87 | (turbo & 1) ? "" : "in" ); | |
88 | } | |
89 | ||
90 | return (turbo & 1) ? (N/1000) : (M/1000); | |
91 | } | |
92 | ||
1da177e4 LT |
93 | /* |
94 | * Return the current memory clock frequency in units of 10kHz | |
95 | */ | |
15a40333 | 96 | unsigned int pxa25x_get_memclk_frequency_10khz(void) |
1da177e4 LT |
97 | { |
98 | return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000; | |
99 | } | |
100 | ||
a6dba20c RK |
101 | static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk) |
102 | { | |
103 | return pxa25x_get_memclk_frequency_10khz() * 10000; | |
104 | } | |
105 | ||
106 | static const struct clkops clk_pxa25x_lcd_ops = { | |
107 | .enable = clk_cken_enable, | |
108 | .disable = clk_cken_disable, | |
109 | .getrate = clk_pxa25x_lcd_getrate, | |
110 | }; | |
111 | ||
ed847782 IM |
112 | static unsigned long gpio12_config_32k[] = { |
113 | GPIO12_32KHz, | |
114 | }; | |
115 | ||
116 | static unsigned long gpio12_config_gpio[] = { | |
117 | GPIO12_GPIO, | |
118 | }; | |
119 | ||
120 | static void clk_gpio12_enable(struct clk *clk) | |
121 | { | |
122 | pxa2xx_mfp_config(gpio12_config_32k, 1); | |
123 | } | |
124 | ||
125 | static void clk_gpio12_disable(struct clk *clk) | |
126 | { | |
127 | pxa2xx_mfp_config(gpio12_config_gpio, 1); | |
128 | } | |
129 | ||
130 | static const struct clkops clk_pxa25x_gpio12_ops = { | |
131 | .enable = clk_gpio12_enable, | |
132 | .disable = clk_gpio12_disable, | |
133 | }; | |
134 | ||
13f75582 IM |
135 | static unsigned long gpio11_config_3m6[] = { |
136 | GPIO11_3_6MHz, | |
137 | }; | |
138 | ||
139 | static unsigned long gpio11_config_gpio[] = { | |
140 | GPIO11_GPIO, | |
141 | }; | |
142 | ||
143 | static void clk_gpio11_enable(struct clk *clk) | |
144 | { | |
145 | pxa2xx_mfp_config(gpio11_config_3m6, 1); | |
146 | } | |
147 | ||
148 | static void clk_gpio11_disable(struct clk *clk) | |
149 | { | |
150 | pxa2xx_mfp_config(gpio11_config_gpio, 1); | |
151 | } | |
152 | ||
153 | static const struct clkops clk_pxa25x_gpio11_ops = { | |
154 | .enable = clk_gpio11_enable, | |
155 | .disable = clk_gpio11_disable, | |
156 | }; | |
157 | ||
a6dba20c RK |
158 | /* |
159 | * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz) | |
160 | * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz | |
161 | * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly) | |
162 | */ | |
e01dbdb4 DB |
163 | static struct clk pxa25x_hwuart_clk = |
164 | INIT_CKEN("UARTCLK", HWUART, 14745600, 1, &pxa_device_hwuart.dev) | |
165 | ; | |
166 | ||
bdb08cb2 RK |
167 | /* |
168 | * PXA 2xx clock declarations. Order is important (see aliases below) | |
169 | * Please be careful not to disrupt the ordering. | |
170 | */ | |
a6dba20c RK |
171 | static struct clk pxa25x_clks[] = { |
172 | INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev), | |
173 | INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev), | |
174 | INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev), | |
435b6e94 | 175 | INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL), |
7a857620 | 176 | INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa25x_device_udc.dev), |
13f75582 | 177 | INIT_CLK("GPIO11_CLK", &clk_pxa25x_gpio11_ops, 3686400, 0, NULL), |
ed847782 | 178 | INIT_CLK("GPIO12_CLK", &clk_pxa25x_gpio12_ops, 32768, 0, NULL), |
a6dba20c RK |
179 | INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev), |
180 | INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev), | |
d8e0db11 | 181 | |
182 | INIT_CKEN("SSPCLK", SSP, 3686400, 0, &pxa25x_device_ssp.dev), | |
183 | INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev), | |
184 | INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev), | |
75540c1a | 185 | INIT_CKEN("PWMCLK", PWM0, 3686400, 0, &pxa25x_device_pwm0.dev), |
186 | INIT_CKEN("PWMCLK", PWM1, 3686400, 0, &pxa25x_device_pwm1.dev), | |
d8e0db11 | 187 | |
27b98a67 MB |
188 | INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL), |
189 | ||
a6dba20c | 190 | /* |
a6dba20c | 191 | INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL), |
a6dba20c | 192 | */ |
435b6e94 | 193 | INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL), |
a6dba20c RK |
194 | }; |
195 | ||
13f75582 IM |
196 | static struct clk pxa2xx_clk_aliases[] = { |
197 | INIT_CKOTHER("GPIO7_CLK", &pxa25x_clks[4], NULL), | |
198 | INIT_CKOTHER("SA1111_CLK", &pxa25x_clks[5], NULL), | |
199 | }; | |
bdb08cb2 | 200 | |
a8fa3f0c | 201 | #ifdef CONFIG_PM |
8775420d | 202 | |
711be5cc EM |
203 | #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x |
204 | #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] | |
205 | ||
711be5cc EM |
206 | /* |
207 | * List of global PXA peripheral registers to preserve. | |
208 | * More ones like CP and general purpose register values are preserved | |
209 | * with the stack pointer in sleep.S. | |
210 | */ | |
649de51b | 211 | enum { SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, |
711be5cc EM |
212 | |
213 | SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U, | |
214 | SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U, | |
215 | SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U, | |
216 | ||
217 | SLEEP_SAVE_PSTR, | |
218 | ||
711be5cc EM |
219 | SLEEP_SAVE_CKEN, |
220 | ||
649de51b | 221 | SLEEP_SAVE_COUNT |
711be5cc EM |
222 | }; |
223 | ||
224 | ||
225 | static void pxa25x_cpu_pm_save(unsigned long *sleep_save) | |
226 | { | |
711be5cc EM |
227 | SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); |
228 | ||
229 | SAVE(GAFR0_L); SAVE(GAFR0_U); | |
230 | SAVE(GAFR1_L); SAVE(GAFR1_U); | |
231 | SAVE(GAFR2_L); SAVE(GAFR2_U); | |
232 | ||
711be5cc EM |
233 | SAVE(CKEN); |
234 | SAVE(PSTR); | |
56b11288 RP |
235 | |
236 | /* Clear GPIO transition detect bits */ | |
237 | GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2; | |
711be5cc EM |
238 | } |
239 | ||
240 | static void pxa25x_cpu_pm_restore(unsigned long *sleep_save) | |
241 | { | |
56b11288 RP |
242 | /* ensure not to come back here if it wasn't intended */ |
243 | PSPR = 0; | |
244 | ||
711be5cc | 245 | /* restore registers */ |
711be5cc EM |
246 | RESTORE(GAFR0_L); RESTORE(GAFR0_U); |
247 | RESTORE(GAFR1_L); RESTORE(GAFR1_U); | |
248 | RESTORE(GAFR2_L); RESTORE(GAFR2_U); | |
711be5cc EM |
249 | RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); |
250 | ||
56b11288 RP |
251 | PSSR = PSSR_RDH | PSSR_PH; |
252 | ||
711be5cc | 253 | RESTORE(CKEN); |
711be5cc EM |
254 | RESTORE(PSTR); |
255 | } | |
256 | ||
257 | static void pxa25x_cpu_pm_enter(suspend_state_t state) | |
8775420d | 258 | { |
dc38e2ad RK |
259 | /* Clear reset status */ |
260 | RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR; | |
261 | ||
8775420d TP |
262 | switch (state) { |
263 | case PM_SUSPEND_MEM: | |
264 | /* set resume return address */ | |
265 | PSPR = virt_to_phys(pxa_cpu_resume); | |
b750a093 | 266 | pxa25x_cpu_suspend(PWRMODE_SLEEP); |
8775420d TP |
267 | break; |
268 | } | |
269 | } | |
a8fa3f0c | 270 | |
711be5cc | 271 | static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = { |
649de51b | 272 | .save_count = SLEEP_SAVE_COUNT, |
26398a70 | 273 | .valid = suspend_valid_only_mem, |
711be5cc EM |
274 | .save = pxa25x_cpu_pm_save, |
275 | .restore = pxa25x_cpu_pm_restore, | |
276 | .enter = pxa25x_cpu_pm_enter, | |
e176bb05 | 277 | }; |
711be5cc EM |
278 | |
279 | static void __init pxa25x_init_pm(void) | |
280 | { | |
281 | pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns; | |
282 | } | |
f79299ca | 283 | #else |
284 | static inline void pxa25x_init_pm(void) {} | |
a8fa3f0c | 285 | #endif |
e176bb05 | 286 | |
c95530c7 | 287 | /* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm |
288 | */ | |
289 | ||
290 | static int pxa25x_set_wake(unsigned int irq, unsigned int on) | |
291 | { | |
292 | int gpio = IRQ_TO_GPIO(irq); | |
c0a596d6 | 293 | uint32_t mask = 0; |
294 | ||
295 | if (gpio >= 0 && gpio < 85) | |
296 | return gpio_set_wake(gpio, on); | |
c95530c7 | 297 | |
298 | if (irq == IRQ_RTCAlrm) { | |
299 | mask = PWER_RTC; | |
300 | goto set_pwer; | |
301 | } | |
302 | ||
303 | return -EINVAL; | |
304 | ||
305 | set_pwer: | |
306 | if (on) | |
307 | PWER |= mask; | |
308 | else | |
309 | PWER &=~mask; | |
310 | ||
311 | return 0; | |
312 | } | |
313 | ||
cd49104d EM |
314 | void __init pxa25x_init_irq(void) |
315 | { | |
b9e25ace | 316 | pxa_init_irq(32, pxa25x_set_wake); |
317 | pxa_init_gpio(85, pxa25x_set_wake); | |
cd49104d EM |
318 | } |
319 | ||
34f3231f | 320 | static struct platform_device *pxa25x_devices[] __initdata = { |
7a857620 | 321 | &pxa25x_device_udc, |
e09d02e1 EM |
322 | &pxa_device_ffuart, |
323 | &pxa_device_btuart, | |
324 | &pxa_device_stuart, | |
e09d02e1 | 325 | &pxa_device_i2s, |
e09d02e1 | 326 | &pxa_device_rtc, |
d8e0db11 | 327 | &pxa25x_device_ssp, |
328 | &pxa25x_device_nssp, | |
329 | &pxa25x_device_assp, | |
75540c1a | 330 | &pxa25x_device_pwm0, |
331 | &pxa25x_device_pwm1, | |
34f3231f RK |
332 | }; |
333 | ||
c0165504 | 334 | static struct sys_device pxa25x_sysdev[] = { |
335 | { | |
336 | .cls = &pxa_irq_sysclass, | |
16dfdbf0 | 337 | }, { |
338 | .cls = &pxa_gpio_sysclass, | |
c0165504 | 339 | }, |
340 | }; | |
341 | ||
e176bb05 RK |
342 | static int __init pxa25x_init(void) |
343 | { | |
c0165504 | 344 | int i, ret = 0; |
f53f066c | 345 | |
e01dbdb4 | 346 | /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */ |
aa9ae8eb | 347 | if (cpu_is_pxa255()) |
e01dbdb4 DB |
348 | clks_register(&pxa25x_hwuart_clk, 1); |
349 | ||
e176bb05 | 350 | if (cpu_is_pxa21x() || cpu_is_pxa25x()) { |
a6dba20c RK |
351 | clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks)); |
352 | ||
f53f066c EM |
353 | if ((ret = pxa_init_dma(16))) |
354 | return ret; | |
f79299ca | 355 | |
711be5cc | 356 | pxa25x_init_pm(); |
f79299ca | 357 | |
c0165504 | 358 | for (i = 0; i < ARRAY_SIZE(pxa25x_sysdev); i++) { |
359 | ret = sysdev_register(&pxa25x_sysdev[i]); | |
360 | if (ret) | |
361 | pr_err("failed to register sysdev[%d]\n", i); | |
362 | } | |
363 | ||
34f3231f RK |
364 | ret = platform_add_devices(pxa25x_devices, |
365 | ARRAY_SIZE(pxa25x_devices)); | |
c0165504 | 366 | if (ret) |
367 | return ret; | |
e176bb05 | 368 | } |
c0165504 | 369 | |
34f3231f | 370 | /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */ |
aa9ae8eb | 371 | if (cpu_is_pxa255()) |
e09d02e1 | 372 | ret = platform_device_register(&pxa_device_hwuart); |
34f3231f | 373 | |
13f75582 | 374 | clks_register(pxa2xx_clk_aliases, ARRAY_SIZE(pxa2xx_clk_aliases)); |
bdb08cb2 | 375 | |
34f3231f | 376 | return ret; |
e176bb05 RK |
377 | } |
378 | ||
1c104e0e | 379 | postcore_initcall(pxa25x_init); |