[deliverable/linux.git] / arch / arm / mach-pxa / pxa25x.c

/*
 *  linux/arch/arm/mach-pxa/pxa25x.c
 *
 *  Author:	Nicolas Pitre
 *  Created:	Jun 15, 2001
 *  Copyright:	MontaVista Software Inc.
 *
 * Code specific to PXA21x/25x/26x variants.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Since this file should be linked before any other machine specific file,
 * the __initcall() here will be executed first.  This serves as default
 * initialization stuff for PXA machines which can be overridden later if
 * need be.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/suspend.h>
#include <linux/sysdev.h>

#include <asm/mach/map.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <mach/gpio.h>
#include <mach/pxa25x.h>
#include <mach/reset.h>
#include <mach/pm.h>
#include <mach/dma.h>
#include <mach/smemc.h>

#include "generic.h"
#include "devices.h"
#include "clock.h"

/*
 * Various clock factors driven by the CCCR register.
 */

/* Crystal Frequency to Memory Frequency Multiplier (L) */
static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };

/* Memory Frequency to Run Mode Frequency Multiplier (M) */
static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };

/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
/* Note: we store the value N * 2 here. */
static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };

/* Crystal clock */
#define BASE_CLK	3686400

/*
 * Get the clock frequency as reflected by CCCR and the turbo flag.
 * We assume these values have been applied via a fcs.
 * If info is not 0 we also display the current settings.
 */
unsigned int pxa25x_get_clk_frequency_khz(int info)
{
	unsigned long cccr, turbo;
	unsigned int l, L, m, M, n2, N;

	cccr = CCCR;
	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );

	l  =  L_clk_mult[(cccr >> 0) & 0x1f];
	m  =  M_clk_mult[(cccr >> 5) & 0x03];
	n2 = N2_clk_mult[(cccr >> 7) & 0x07];

	L = l * BASE_CLK;
	M = m * L;
	N = n2 * M / 2;

	if(info)
	{
		L += 5000;
		printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
			L / 1000000, (L % 1000000) / 10000, l );
		M += 5000;
		printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
			M / 1000000, (M % 1000000) / 10000, m );
		N += 5000;
		printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
			N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
			(turbo & 1) ? "" : "in" );
	}

	return (turbo & 1) ? (N/1000) : (M/1000);
}

static unsigned long clk_pxa25x_mem_getrate(struct clk *clk)
{
	return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK;
}

static const struct clkops clk_pxa25x_mem_ops = {
	.enable		= clk_dummy_enable,
	.disable	= clk_dummy_disable,
	.getrate	= clk_pxa25x_mem_getrate,
};

static const struct clkops clk_pxa25x_lcd_ops = {
	.enable		= clk_pxa2xx_cken_enable,
	.disable	= clk_pxa2xx_cken_disable,
	.getrate	= clk_pxa25x_mem_getrate,
};

static unsigned long gpio12_config_32k[] = {
	GPIO12_32KHz,
};

static unsigned long gpio12_config_gpio[] = {
	GPIO12_GPIO,
};

static void clk_gpio12_enable(struct clk *clk)
{
	pxa2xx_mfp_config(gpio12_config_32k, 1);
}

static void clk_gpio12_disable(struct clk *clk)
{
	pxa2xx_mfp_config(gpio12_config_gpio, 1);
}

static const struct clkops clk_pxa25x_gpio12_ops = {
	.enable         = clk_gpio12_enable,
	.disable        = clk_gpio12_disable,
};

static unsigned long gpio11_config_3m6[] = {
	GPIO11_3_6MHz,
};

static unsigned long gpio11_config_gpio[] = {
	GPIO11_GPIO,
};

static void clk_gpio11_enable(struct clk *clk)
{
	pxa2xx_mfp_config(gpio11_config_3m6, 1);
}

static void clk_gpio11_disable(struct clk *clk)
{
	pxa2xx_mfp_config(gpio11_config_gpio, 1);
}

static const struct clkops clk_pxa25x_gpio11_ops = {
	.enable         = clk_gpio11_enable,
	.disable        = clk_gpio11_disable,
};

/*
 * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
 * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
 * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
 */

/*
 * PXA 2xx clock declarations.
 */
static DEFINE_PXA2_CKEN(pxa25x_hwuart, HWUART, 14745600, 1);
static DEFINE_PXA2_CKEN(pxa25x_ffuart, FFUART, 14745600, 1);
static DEFINE_PXA2_CKEN(pxa25x_btuart, BTUART, 14745600, 1);
static DEFINE_PXA2_CKEN(pxa25x_stuart, STUART, 14745600, 1);
static DEFINE_PXA2_CKEN(pxa25x_usb, USB, 47923000, 5);
static DEFINE_PXA2_CKEN(pxa25x_mmc, MMC, 19169000, 0);
static DEFINE_PXA2_CKEN(pxa25x_i2c, I2C, 31949000, 0);
static DEFINE_PXA2_CKEN(pxa25x_ssp, SSP, 3686400, 0);
static DEFINE_PXA2_CKEN(pxa25x_nssp, NSSP, 3686400, 0);
static DEFINE_PXA2_CKEN(pxa25x_assp, ASSP, 3686400, 0);
static DEFINE_PXA2_CKEN(pxa25x_pwm0, PWM0, 3686400, 0);
static DEFINE_PXA2_CKEN(pxa25x_pwm1, PWM1, 3686400, 0);
static DEFINE_PXA2_CKEN(pxa25x_ac97, AC97, 24576000, 0);
static DEFINE_PXA2_CKEN(pxa25x_i2s, I2S, 14745600, 0);
static DEFINE_PXA2_CKEN(pxa25x_ficp, FICP, 47923000, 0);

static DEFINE_CK(pxa25x_lcd, LCD, &clk_pxa25x_lcd_ops);
static DEFINE_CLK(pxa25x_gpio11, &clk_pxa25x_gpio11_ops, 3686400, 0);
static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0);
static DEFINE_CLK(pxa25x_mem, &clk_pxa25x_mem_ops, 0, 0);

static struct clk_lookup pxa25x_clkregs[] = {
	INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL),
	INIT_CLKREG(&clk_pxa25x_ffuart, "pxa2xx-uart.0", NULL),
	INIT_CLKREG(&clk_pxa25x_btuart, "pxa2xx-uart.1", NULL),
	INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-uart.2", NULL),
	INIT_CLKREG(&clk_pxa25x_usb, "pxa25x-udc", NULL),
	INIT_CLKREG(&clk_pxa25x_mmc, "pxa2xx-mci.0", NULL),
	INIT_CLKREG(&clk_pxa25x_i2c, "pxa2xx-i2c.0", NULL),
	INIT_CLKREG(&clk_pxa25x_ssp, "pxa25x-ssp.0", NULL),
	INIT_CLKREG(&clk_pxa25x_nssp, "pxa25x-nssp.1", NULL),
	INIT_CLKREG(&clk_pxa25x_assp, "pxa25x-nssp.2", NULL),
	INIT_CLKREG(&clk_pxa25x_pwm0, "pxa25x-pwm.0", NULL),
	INIT_CLKREG(&clk_pxa25x_pwm1, "pxa25x-pwm.1", NULL),
	INIT_CLKREG(&clk_pxa25x_i2s, "pxa2xx-i2s", NULL),
	INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-ir", "UARTCLK"),
	INIT_CLKREG(&clk_pxa25x_ficp, "pxa2xx-ir", "FICPCLK"),
	INIT_CLKREG(&clk_pxa25x_ac97, NULL, "AC97CLK"),
	INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"),
	INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
	INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL),
};

static struct clk_lookup pxa25x_hwuart_clkreg =
	INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL);

#ifdef CONFIG_PM

#define SAVE(x)		sleep_save[SLEEP_SAVE_##x] = x
#define RESTORE(x)	x = sleep_save[SLEEP_SAVE_##x]

/*
 * List of global PXA peripheral registers to preserve.
 * More ones like CP and general purpose register values are preserved
 * with the stack pointer in sleep.S.
 */
enum {
	SLEEP_SAVE_PSTR,
	SLEEP_SAVE_COUNT
};


static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
{
	SAVE(PSTR);
}

static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
{
	RESTORE(PSTR);
}

static void pxa25x_cpu_pm_enter(suspend_state_t state)
{
	/* Clear reset status */
	RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;

	switch (state) {
	case PM_SUSPEND_MEM:
		pxa25x_cpu_suspend(PWRMODE_SLEEP);
		break;
	}
}

static int pxa25x_cpu_pm_prepare(void)
{
	/* set resume return address */
	PSPR = virt_to_phys(pxa_cpu_resume);
	return 0;
}

static void pxa25x_cpu_pm_finish(void)
{
	/* ensure not to come back here if it wasn't intended */
	PSPR = 0;
}

static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
	.save_count	= SLEEP_SAVE_COUNT,
	.valid		= suspend_valid_only_mem,
	.save		= pxa25x_cpu_pm_save,
	.restore	= pxa25x_cpu_pm_restore,
	.enter		= pxa25x_cpu_pm_enter,
	.prepare	= pxa25x_cpu_pm_prepare,
	.finish		= pxa25x_cpu_pm_finish,
};

static void __init pxa25x_init_pm(void)
{
	pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
}
#else
static inline void pxa25x_init_pm(void) {}
#endif

/* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
 */

static int pxa25x_set_wake(unsigned int irq, unsigned int on)
{
	int gpio = IRQ_TO_GPIO(irq);
	uint32_t mask = 0;

	if (gpio >= 0 && gpio < 85)
		return gpio_set_wake(gpio, on);

	if (irq == IRQ_RTCAlrm) {
		mask = PWER_RTC;
		goto set_pwer;
	}

	return -EINVAL;

set_pwer:
	if (on)
		PWER |= mask;
	else
		PWER &=~mask;

	return 0;
}

void __init pxa25x_init_irq(void)
{
	pxa_init_irq(32, pxa25x_set_wake);
	pxa_init_gpio(IRQ_GPIO_2_x, 2, 84, pxa25x_set_wake);
}

#ifdef CONFIG_CPU_PXA26x
void __init pxa26x_init_irq(void)
{
	pxa_init_irq(32, pxa25x_set_wake);
	pxa_init_gpio(IRQ_GPIO_2_x, 2, 89, pxa25x_set_wake);
}
#endif

static struct map_desc pxa25x_io_desc[] __initdata = {
	{	/* Mem Ctl */
		.virtual	= SMEMC_VIRT,
		.pfn		= __phys_to_pfn(PXA2XX_SMEMC_BASE),
		.length		= 0x00200000,
		.type		= MT_DEVICE
	},
};

void __init pxa25x_map_io(void)
{
	pxa_map_io();
	iotable_init(ARRAY_AND_SIZE(pxa25x_io_desc));
	pxa25x_get_clk_frequency_khz(1);
}

static struct platform_device *pxa25x_devices[] __initdata = {
	&pxa25x_device_udc,
	&pxa_device_pmu,
	&pxa_device_i2s,
	&sa1100_device_rtc,
	&pxa25x_device_ssp,
	&pxa25x_device_nssp,
	&pxa25x_device_assp,
	&pxa25x_device_pwm0,
	&pxa25x_device_pwm1,
};

static struct sys_device pxa25x_sysdev[] = {
	{
		.cls	= &pxa_irq_sysclass,
	}, {
		.cls	= &pxa2xx_mfp_sysclass,
	}, {
		.cls	= &pxa_gpio_sysclass,
	}, {
		.cls	= &pxa2xx_clock_sysclass,
	}
};

static int __init pxa25x_init(void)
{
	int i, ret = 0;

	if (cpu_is_pxa25x()) {

		reset_status = RCSR;

		clkdev_add_table(pxa25x_clkregs, ARRAY_SIZE(pxa25x_clkregs));

		if ((ret = pxa_init_dma(IRQ_DMA, 16)))
			return ret;

		pxa25x_init_pm();

		for (i = 0; i < ARRAY_SIZE(pxa25x_sysdev); i++) {
			ret = sysdev_register(&pxa25x_sysdev[i]);
			if (ret)
				pr_err("failed to register sysdev[%d]\n", i);
		}

		ret = platform_add_devices(pxa25x_devices,
					   ARRAY_SIZE(pxa25x_devices));
		if (ret)
			return ret;
	}

	/* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */
	if (cpu_is_pxa255())
		clkdev_add(&pxa25x_hwuart_clkreg);

	return ret;
}

postcore_initcall(pxa25x_init);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-pxa/pxa25x.c
	3	*
	4	* Author: Nicolas Pitre
	5	* Created: Jun 15, 2001
	6	* Copyright: MontaVista Software Inc.
	7	*
	8	* Code specific to PXA21x/25x/26x variants.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*
	14	* Since this file should be linked before any other machine specific file,
	15	* the __initcall() here will be executed first. This serves as default
	16	* initialization stuff for PXA machines which can be overridden later if
	17	* need be.
	18	*/
	19	#include <linux/module.h>
	20	#include <linux/kernel.h>
	21	#include <linux/init.h>
34f3231f	22	#include <linux/platform_device.h>
95d9ffbe	23	#include <linux/suspend.h>
c0165504	24	#include <linux/sysdev.h>
1da177e4	25
851982c1	26	#include <asm/mach/map.h>
a09e64fb RK	27	#include <mach/hardware.h>
a09e64fb RK	28	#include <mach/irqs.h>
a58fbcd8	29	#include <mach/gpio.h>
51c62982	30	#include <mach/pxa25x.h>
afd2fc02	31	#include <mach/reset.h>
a09e64fb RK	32	#include <mach/pm.h>
a09e64fb RK	33	#include <mach/dma.h>
ad68bb9f	34	#include <mach/smemc.h>
1da177e4 LT	35
1da177e4 LT	36	#include "generic.h"
46c41e62	37	#include "devices.h"
a6dba20c	38	#include "clock.h"
1da177e4 LT	39
	40	/*
	41	* Various clock factors driven by the CCCR register.
	42	*/
	43
	44	/* Crystal Frequency to Memory Frequency Multiplier (L) */
	45	static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
	46
	47	/* Memory Frequency to Run Mode Frequency Multiplier (M) */
	48	static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
	49
	50	/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
	51	/* Note: we store the value N * 2 here. */
	52	static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
	53
	54	/* Crystal clock */
	55	#define BASE_CLK 3686400
	56
	57	/*
	58	* Get the clock frequency as reflected by CCCR and the turbo flag.
	59	* We assume these values have been applied via a fcs.
	60	* If info is not 0 we also display the current settings.
	61	*/
15a40333	62	unsigned int pxa25x_get_clk_frequency_khz(int info)
1da177e4 LT	63	{
	64	unsigned long cccr, turbo;
	65	unsigned int l, L, m, M, n2, N;
	66
	67	cccr = CCCR;
	68	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
	69
	70	l = L_clk_mult[(cccr >> 0) & 0x1f];
	71	m = M_clk_mult[(cccr >> 5) & 0x03];
	72	n2 = N2_clk_mult[(cccr >> 7) & 0x07];
	73
	74	L = l * BASE_CLK;
	75	M = m * L;
	76	N = n2 * M / 2;
	77
	78	if(info)
	79	{
	80	L += 5000;
	81	printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
	82	L / 1000000, (L % 1000000) / 10000, l );
	83	M += 5000;
	84	printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
	85	M / 1000000, (M % 1000000) / 10000, m );
	86	N += 5000;
	87	printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
	88	N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
	89	(turbo & 1) ? "" : "in" );
	90	}
	91
	92	return (turbo & 1) ? (N/1000) : (M/1000);
	93	}
	94
2a125dd5	95	static unsigned long clk_pxa25x_mem_getrate(struct clk *clk)
1da177e4	96	{
2a125dd5	97	return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK;
1da177e4 LT	98	}
1da177e4 LT	99
2a125dd5 EM	100	static const struct clkops clk_pxa25x_mem_ops = {
	101	.enable = clk_dummy_enable,
	102	.disable = clk_dummy_disable,
	103	.getrate = clk_pxa25x_mem_getrate,
	104	};
a6dba20c RK	105
a6dba20c RK	106	static const struct clkops clk_pxa25x_lcd_ops = {
4029813c EM	107	.enable = clk_pxa2xx_cken_enable,
4029813c EM	108	.disable = clk_pxa2xx_cken_disable,
2a125dd5	109	.getrate = clk_pxa25x_mem_getrate,
a6dba20c RK	110	};
a6dba20c RK	111
ed847782 IM	112	static unsigned long gpio12_config_32k[] = {
	113	GPIO12_32KHz,
	114	};
	115
	116	static unsigned long gpio12_config_gpio[] = {
	117	GPIO12_GPIO,
	118	};
	119
	120	static void clk_gpio12_enable(struct clk *clk)
	121	{
	122	pxa2xx_mfp_config(gpio12_config_32k, 1);
	123	}
	124
	125	static void clk_gpio12_disable(struct clk *clk)
	126	{
	127	pxa2xx_mfp_config(gpio12_config_gpio, 1);
	128	}
	129
	130	static const struct clkops clk_pxa25x_gpio12_ops = {
	131	.enable = clk_gpio12_enable,
	132	.disable = clk_gpio12_disable,
	133	};
	134
13f75582 IM	135	static unsigned long gpio11_config_3m6[] = {
	136	GPIO11_3_6MHz,
	137	};
	138
	139	static unsigned long gpio11_config_gpio[] = {
	140	GPIO11_GPIO,
	141	};
	142
	143	static void clk_gpio11_enable(struct clk *clk)
	144	{
	145	pxa2xx_mfp_config(gpio11_config_3m6, 1);
	146	}
	147
	148	static void clk_gpio11_disable(struct clk *clk)
	149	{
	150	pxa2xx_mfp_config(gpio11_config_gpio, 1);
	151	}
	152
	153	static const struct clkops clk_pxa25x_gpio11_ops = {
	154	.enable = clk_gpio11_enable,
	155	.disable = clk_gpio11_disable,
	156	};
	157
a6dba20c RK	158	/*
	159	* 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
	160	* 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
	161	* 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
	162	*/
e01dbdb4	163
bdb08cb2	164	/*
c1ed406c	165	* PXA 2xx clock declarations.
bdb08cb2	166	*/
4029813c EM	167	static DEFINE_PXA2_CKEN(pxa25x_hwuart, HWUART, 14745600, 1);
	168	static DEFINE_PXA2_CKEN(pxa25x_ffuart, FFUART, 14745600, 1);
	169	static DEFINE_PXA2_CKEN(pxa25x_btuart, BTUART, 14745600, 1);
	170	static DEFINE_PXA2_CKEN(pxa25x_stuart, STUART, 14745600, 1);
	171	static DEFINE_PXA2_CKEN(pxa25x_usb, USB, 47923000, 5);
	172	static DEFINE_PXA2_CKEN(pxa25x_mmc, MMC, 19169000, 0);
	173	static DEFINE_PXA2_CKEN(pxa25x_i2c, I2C, 31949000, 0);
	174	static DEFINE_PXA2_CKEN(pxa25x_ssp, SSP, 3686400, 0);
	175	static DEFINE_PXA2_CKEN(pxa25x_nssp, NSSP, 3686400, 0);
	176	static DEFINE_PXA2_CKEN(pxa25x_assp, ASSP, 3686400, 0);
	177	static DEFINE_PXA2_CKEN(pxa25x_pwm0, PWM0, 3686400, 0);
	178	static DEFINE_PXA2_CKEN(pxa25x_pwm1, PWM1, 3686400, 0);
	179	static DEFINE_PXA2_CKEN(pxa25x_ac97, AC97, 24576000, 0);
	180	static DEFINE_PXA2_CKEN(pxa25x_i2s, I2S, 14745600, 0);
	181	static DEFINE_PXA2_CKEN(pxa25x_ficp, FICP, 47923000, 0);
	182
8c3abc7d	183	static DEFINE_CK(pxa25x_lcd, LCD, &clk_pxa25x_lcd_ops);
8c3abc7d RK	184	static DEFINE_CLK(pxa25x_gpio11, &clk_pxa25x_gpio11_ops, 3686400, 0);
8c3abc7d RK	185	static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0);
2a125dd5	186	static DEFINE_CLK(pxa25x_mem, &clk_pxa25x_mem_ops, 0, 0);
8c3abc7d RK	187
	188	static struct clk_lookup pxa25x_clkregs[] = {
	189	INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL),
	190	INIT_CLKREG(&clk_pxa25x_ffuart, "pxa2xx-uart.0", NULL),
	191	INIT_CLKREG(&clk_pxa25x_btuart, "pxa2xx-uart.1", NULL),
	192	INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-uart.2", NULL),
	193	INIT_CLKREG(&clk_pxa25x_usb, "pxa25x-udc", NULL),
	194	INIT_CLKREG(&clk_pxa25x_mmc, "pxa2xx-mci.0", NULL),
	195	INIT_CLKREG(&clk_pxa25x_i2c, "pxa2xx-i2c.0", NULL),
	196	INIT_CLKREG(&clk_pxa25x_ssp, "pxa25x-ssp.0", NULL),
	197	INIT_CLKREG(&clk_pxa25x_nssp, "pxa25x-nssp.1", NULL),
	198	INIT_CLKREG(&clk_pxa25x_assp, "pxa25x-nssp.2", NULL),
	199	INIT_CLKREG(&clk_pxa25x_pwm0, "pxa25x-pwm.0", NULL),
	200	INIT_CLKREG(&clk_pxa25x_pwm1, "pxa25x-pwm.1", NULL),
	201	INIT_CLKREG(&clk_pxa25x_i2s, "pxa2xx-i2s", NULL),
	202	INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-ir", "UARTCLK"),
	203	INIT_CLKREG(&clk_pxa25x_ficp, "pxa2xx-ir", "FICPCLK"),
	204	INIT_CLKREG(&clk_pxa25x_ac97, NULL, "AC97CLK"),
	205	INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"),
	206	INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
2a125dd5	207	INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL),
a6dba20c RK	208	};
a6dba20c RK	209
4029813c EM	210	static struct clk_lookup pxa25x_hwuart_clkreg =
	211	INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL);
	212
a8fa3f0c	213	#ifdef CONFIG_PM
8775420d	214
711be5cc EM	215	#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
	216	#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
	217
711be5cc EM	218	/*
	219	* List of global PXA peripheral registers to preserve.
	220	* More ones like CP and general purpose register values are preserved
	221	* with the stack pointer in sleep.S.
	222	*/
5a3d9651	223	enum {
711be5cc	224	SLEEP_SAVE_PSTR,
649de51b	225	SLEEP_SAVE_COUNT
711be5cc EM	226	};
	227
	228
	229	static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
	230	{
711be5cc EM	231	SAVE(PSTR);
	232	}
	233
	234	static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
	235	{
711be5cc EM	236	RESTORE(PSTR);
	237	}
	238
	239	static void pxa25x_cpu_pm_enter(suspend_state_t state)
8775420d	240	{
dc38e2ad RK	241	/* Clear reset status */
	242	RCSR = RCSR_HWR \| RCSR_WDR \| RCSR_SMR \| RCSR_GPR;
	243
8775420d TP	244	switch (state) {
8775420d TP	245	case PM_SUSPEND_MEM:
b750a093	246	pxa25x_cpu_suspend(PWRMODE_SLEEP);
8775420d TP	247	break;
	248	}
	249	}
a8fa3f0c	250
4104980a RK	251	static int pxa25x_cpu_pm_prepare(void)
	252	{
	253	/* set resume return address */
	254	PSPR = virt_to_phys(pxa_cpu_resume);
	255	return 0;
	256	}
	257
	258	static void pxa25x_cpu_pm_finish(void)
	259	{
	260	/* ensure not to come back here if it wasn't intended */
	261	PSPR = 0;
	262	}
	263
711be5cc	264	static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
649de51b	265	.save_count = SLEEP_SAVE_COUNT,
26398a70	266	.valid = suspend_valid_only_mem,
711be5cc EM	267	.save = pxa25x_cpu_pm_save,
	268	.restore = pxa25x_cpu_pm_restore,
	269	.enter = pxa25x_cpu_pm_enter,
4104980a RK	270	.prepare = pxa25x_cpu_pm_prepare,
4104980a RK	271	.finish = pxa25x_cpu_pm_finish,
e176bb05	272	};
711be5cc EM	273
	274	static void __init pxa25x_init_pm(void)
	275	{
	276	pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
	277	}
f79299ca	278	#else
f79299ca	279	static inline void pxa25x_init_pm(void) {}
a8fa3f0c	280	#endif
e176bb05	281
c95530c7	282	/* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
	283	*/
	284
	285	static int pxa25x_set_wake(unsigned int irq, unsigned int on)
	286	{
	287	int gpio = IRQ_TO_GPIO(irq);
c0a596d6	288	uint32_t mask = 0;
	289
	290	if (gpio >= 0 && gpio < 85)
	291	return gpio_set_wake(gpio, on);
c95530c7	292
	293	if (irq == IRQ_RTCAlrm) {
	294	mask = PWER_RTC;
	295	goto set_pwer;
	296	}
	297
	298	return -EINVAL;
	299
	300	set_pwer:
	301	if (on)
	302	PWER \|= mask;
	303	else
	304	PWER &=~mask;
	305
	306	return 0;
	307	}
	308
cd49104d EM	309	void __init pxa25x_init_irq(void)
cd49104d EM	310	{
b9e25ace	311	pxa_init_irq(32, pxa25x_set_wake);
a58fbcd8	312	pxa_init_gpio(IRQ_GPIO_2_x, 2, 84, pxa25x_set_wake);
cd49104d EM	313	}
cd49104d EM	314
067455aa EM	315	#ifdef CONFIG_CPU_PXA26x
	316	void __init pxa26x_init_irq(void)
	317	{
	318	pxa_init_irq(32, pxa25x_set_wake);
a58fbcd8	319	pxa_init_gpio(IRQ_GPIO_2_x, 2, 89, pxa25x_set_wake);
067455aa EM	320	}
	321	#endif
	322
851982c1 MV	323	static struct map_desc pxa25x_io_desc[] __initdata = {
851982c1 MV	324	{ /* Mem Ctl */
ad68bb9f MV	325	.virtual = SMEMC_VIRT,
ad68bb9f MV	326	.pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE),
851982c1 MV	327	.length = 0x00200000,
	328	.type = MT_DEVICE
	329	},
	330	};
	331
	332	void __init pxa25x_map_io(void)
	333	{
	334	pxa_map_io();
	335	iotable_init(ARRAY_AND_SIZE(pxa25x_io_desc));
	336	pxa25x_get_clk_frequency_khz(1);
	337	}
	338
34f3231f	339	static struct platform_device *pxa25x_devices[] __initdata = {
7a857620	340	&pxa25x_device_udc,
09a5358d	341	&pxa_device_pmu,
e09d02e1	342	&pxa_device_i2s,
72493146	343	&sa1100_device_rtc,
d8e0db11	344	&pxa25x_device_ssp,
	345	&pxa25x_device_nssp,
	346	&pxa25x_device_assp,
75540c1a	347	&pxa25x_device_pwm0,
75540c1a	348	&pxa25x_device_pwm1,
34f3231f RK	349	};
34f3231f RK	350
c0165504	351	static struct sys_device pxa25x_sysdev[] = {
	352	{
	353	.cls = &pxa_irq_sysclass,
5a3d9651 EM	354	}, {
5a3d9651 EM	355	.cls = &pxa2xx_mfp_sysclass,
16dfdbf0	356	}, {
16dfdbf0	357	.cls = &pxa_gpio_sysclass,
f113fe4e EM	358	}, {
	359	.cls = &pxa2xx_clock_sysclass,
	360	}
c0165504	361	};
c0165504	362
e176bb05 RK	363	static int __init pxa25x_init(void)
e176bb05 RK	364	{
c0165504	365	int i, ret = 0;
f53f066c	366
0ffcbfd5	367	if (cpu_is_pxa25x()) {
04fef228 EM	368
	369	reset_status = RCSR;
	370
0a0300dc	371	clkdev_add_table(pxa25x_clkregs, ARRAY_SIZE(pxa25x_clkregs));
a6dba20c	372
fef1f99a	373	if ((ret = pxa_init_dma(IRQ_DMA, 16)))
f53f066c	374	return ret;
f79299ca	375
711be5cc	376	pxa25x_init_pm();
f79299ca	377
c0165504	378	for (i = 0; i < ARRAY_SIZE(pxa25x_sysdev); i++) {
	379	ret = sysdev_register(&pxa25x_sysdev[i]);
	380	if (ret)
	381	pr_err("failed to register sysdev[%d]\n", i);
	382	}
	383
34f3231f RK	384	ret = platform_add_devices(pxa25x_devices,
34f3231f RK	385	ARRAY_SIZE(pxa25x_devices));
c0165504	386	if (ret)
c0165504	387	return ret;
e176bb05	388	}
c0165504	389
2b12797c	390	/* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */
cc155c6f	391	if (cpu_is_pxa255())
0a0300dc	392	clkdev_add(&pxa25x_hwuart_clkreg);
34f3231f RK	393
34f3231f RK	394	return ret;
e176bb05 RK	395	}
e176bb05 RK	396
1c104e0e	397	postcore_initcall(pxa25x_init);