[deliverable/linux.git] / arch / arm / mach-pxa / pxa25x.c

/*
 *  linux/arch/arm/mach-pxa/pxa25x.c
 *
 *  Author:	Nicolas Pitre
 *  Created:	Jun 15, 2001
 *  Copyright:	MontaVista Software Inc.
 *
 * Code specific to PXA21x/25x/26x variants.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Since this file should be linked before any other machine specific file,
 * the __initcall() here will be executed first.  This serves as default
 * initialization stuff for PXA machines which can be overridden later if
 * need be.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/suspend.h>

#include <asm/hardware.h>
#include <asm/arch/irqs.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pm.h>
#include <asm/arch/dma.h>

#include "generic.h"
#include "devices.h"
#include "clock.h"

/*
 * Various clock factors driven by the CCCR register.
 */

/* Crystal Frequency to Memory Frequency Multiplier (L) */
static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };

/* Memory Frequency to Run Mode Frequency Multiplier (M) */
static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };

/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
/* Note: we store the value N * 2 here. */
static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };

/* Crystal clock */
#define BASE_CLK	3686400

/*
 * Get the clock frequency as reflected by CCCR and the turbo flag.
 * We assume these values have been applied via a fcs.
 * If info is not 0 we also display the current settings.
 */
unsigned int pxa25x_get_clk_frequency_khz(int info)
{
	unsigned long cccr, turbo;
	unsigned int l, L, m, M, n2, N;

	cccr = CCCR;
	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );

	l  =  L_clk_mult[(cccr >> 0) & 0x1f];
	m  =  M_clk_mult[(cccr >> 5) & 0x03];
	n2 = N2_clk_mult[(cccr >> 7) & 0x07];

	L = l * BASE_CLK;
	M = m * L;
	N = n2 * M / 2;

	if(info)
	{
		L += 5000;
		printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
			L / 1000000, (L % 1000000) / 10000, l );
		M += 5000;
		printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
			M / 1000000, (M % 1000000) / 10000, m );
		N += 5000;
		printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
			N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
			(turbo & 1) ? "" : "in" );
	}

	return (turbo & 1) ? (N/1000) : (M/1000);
}

/*
 * Return the current memory clock frequency in units of 10kHz
 */
unsigned int pxa25x_get_memclk_frequency_10khz(void)
{
	return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000;
}

static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk)
{
	return pxa25x_get_memclk_frequency_10khz() * 10000;
}

static const struct clkops clk_pxa25x_lcd_ops = {
	.enable		= clk_cken_enable,
	.disable	= clk_cken_disable,
	.getrate	= clk_pxa25x_lcd_getrate,
};

/*
 * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
 * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
 * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
 */
static struct clk pxa25x_clks[] = {
	INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev),
	INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev),
	INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev),
	INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev),
	INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL),
	INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa_device_udc.dev),
	INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev),
	INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev),
	/*
	INIT_CKEN("PWMCLK",  PWM0, 3686400,  0, NULL),
	INIT_CKEN("PWMCLK",  PWM0, 3686400,  0, NULL),
	INIT_CKEN("SSPCLK",  SSP,  3686400,  0, NULL),
	INIT_CKEN("I2SCLK",  I2S,  14745600, 0, NULL),
	INIT_CKEN("NSSPCLK", NSSP, 3686400,  0, NULL),
	*/
	INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL),
};

#ifdef CONFIG_PM

#define SAVE(x)		sleep_save[SLEEP_SAVE_##x] = x
#define RESTORE(x)	x = sleep_save[SLEEP_SAVE_##x]

#define RESTORE_GPLEVEL(n) do { \
	GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \
	GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \
} while (0)

/*
 * List of global PXA peripheral registers to preserve.
 * More ones like CP and general purpose register values are preserved
 * with the stack pointer in sleep.S.
 */
enum {	SLEEP_SAVE_START = 0,

	SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2,
	SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2,
	SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2,
	SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2,
	SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2,

	SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
	SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
	SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,

	SLEEP_SAVE_PSTR,

	SLEEP_SAVE_ICMR,
	SLEEP_SAVE_CKEN,

	SLEEP_SAVE_SIZE
};


static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
{
	SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2);
	SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2);
	SAVE(GRER0); SAVE(GRER1); SAVE(GRER2);
	SAVE(GFER0); SAVE(GFER1); SAVE(GFER2);
	SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2);

	SAVE(GAFR0_L); SAVE(GAFR0_U);
	SAVE(GAFR1_L); SAVE(GAFR1_U);
	SAVE(GAFR2_L); SAVE(GAFR2_U);

	SAVE(ICMR); ICMR = 0;
	SAVE(CKEN);
	SAVE(PSTR);

	/* Clear GPIO transition detect bits */
	GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2;
}

static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
{
	/* ensure not to come back here if it wasn't intended */
	PSPR = 0;

	/* restore registers */
	RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); RESTORE_GPLEVEL(2);
	RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2);
	RESTORE(GAFR0_L); RESTORE(GAFR0_U);
	RESTORE(GAFR1_L); RESTORE(GAFR1_U);
	RESTORE(GAFR2_L); RESTORE(GAFR2_U);
	RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2);
	RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2);
	RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);

	PSSR = PSSR_RDH | PSSR_PH;

	RESTORE(CKEN);

	ICLR = 0;
	ICCR = 1;
	RESTORE(ICMR);
	RESTORE(PSTR);
}

static void pxa25x_cpu_pm_enter(suspend_state_t state)
{
	CKEN = 0;

	switch (state) {
	case PM_SUSPEND_MEM:
		/* set resume return address */
		PSPR = virt_to_phys(pxa_cpu_resume);
		pxa25x_cpu_suspend(PWRMODE_SLEEP);
		break;
	}
}

static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
	.save_size	= SLEEP_SAVE_SIZE,
	.valid		= suspend_valid_only_mem,
	.save		= pxa25x_cpu_pm_save,
	.restore	= pxa25x_cpu_pm_restore,
	.enter		= pxa25x_cpu_pm_enter,
};

static void __init pxa25x_init_pm(void)
{
	pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
}
#endif

/* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
 */

static int pxa25x_set_wake(unsigned int irq, unsigned int on)
{
	int gpio = IRQ_TO_GPIO(irq);
	uint32_t gpio_bit, mask = 0;

	if (gpio >= 0 && gpio <= 15) {
		gpio_bit = GPIO_bit(gpio);
		mask = gpio_bit;
		if (on) {
			if (GRER(gpio) | gpio_bit)
				PRER |= gpio_bit;
			else
				PRER &= ~gpio_bit;

			if (GFER(gpio) | gpio_bit)
				PFER |= gpio_bit;
			else
				PFER &= ~gpio_bit;
		}
		goto set_pwer;
	}

	if (irq == IRQ_RTCAlrm) {
		mask = PWER_RTC;
		goto set_pwer;
	}

	return -EINVAL;

set_pwer:
	if (on)
		PWER |= mask;
	else
		PWER &=~mask;

	return 0;
}

void __init pxa25x_init_irq(void)
{
	pxa_init_irq_low();
	pxa_init_irq_gpio(85);
	pxa_init_irq_set_wake(pxa25x_set_wake);
}

static struct platform_device *pxa25x_devices[] __initdata = {
	&pxa_device_mci,
	&pxa_device_udc,
	&pxa_device_fb,
	&pxa_device_ffuart,
	&pxa_device_btuart,
	&pxa_device_stuart,
	&pxa_device_i2c,
	&pxa_device_i2s,
	&pxa_device_ficp,
	&pxa_device_rtc,
};

static int __init pxa25x_init(void)
{
	int ret = 0;

	if (cpu_is_pxa21x() || cpu_is_pxa25x()) {
		clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks));

		if ((ret = pxa_init_dma(16)))
			return ret;
#ifdef CONFIG_PM
		pxa25x_init_pm();
#endif
		ret = platform_add_devices(pxa25x_devices,
					   ARRAY_SIZE(pxa25x_devices));
	}
	/* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
	if (cpu_is_pxa25x())
		ret = platform_device_register(&pxa_device_hwuart);

	return ret;
}

subsys_initcall(pxa25x_init);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-pxa/pxa25x.c
	3	*
	4	* Author: Nicolas Pitre
	5	* Created: Jun 15, 2001
	6	* Copyright: MontaVista Software Inc.
	7	*
	8	* Code specific to PXA21x/25x/26x variants.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*
	14	* Since this file should be linked before any other machine specific file,
	15	* the __initcall() here will be executed first. This serves as default
	16	* initialization stuff for PXA machines which can be overridden later if
	17	* need be.
	18	*/
	19	#include <linux/module.h>
	20	#include <linux/kernel.h>
	21	#include <linux/init.h>
34f3231f	22	#include <linux/platform_device.h>
95d9ffbe	23	#include <linux/suspend.h>
1da177e4 LT	24
1da177e4 LT	25	#include <asm/hardware.h>
cd49104d	26	#include <asm/arch/irqs.h>
1da177e4	27	#include <asm/arch/pxa-regs.h>
e176bb05	28	#include <asm/arch/pm.h>
f53f066c	29	#include <asm/arch/dma.h>
1da177e4 LT	30
1da177e4 LT	31	#include "generic.h"
46c41e62	32	#include "devices.h"
a6dba20c	33	#include "clock.h"
1da177e4 LT	34
	35	/*
	36	* Various clock factors driven by the CCCR register.
	37	*/
	38
	39	/* Crystal Frequency to Memory Frequency Multiplier (L) */
	40	static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
	41
	42	/* Memory Frequency to Run Mode Frequency Multiplier (M) */
	43	static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
	44
	45	/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
	46	/* Note: we store the value N * 2 here. */
	47	static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
	48
	49	/* Crystal clock */
	50	#define BASE_CLK 3686400
	51
	52	/*
	53	* Get the clock frequency as reflected by CCCR and the turbo flag.
	54	* We assume these values have been applied via a fcs.
	55	* If info is not 0 we also display the current settings.
	56	*/
15a40333	57	unsigned int pxa25x_get_clk_frequency_khz(int info)
1da177e4 LT	58	{
	59	unsigned long cccr, turbo;
	60	unsigned int l, L, m, M, n2, N;
	61
	62	cccr = CCCR;
	63	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
	64
	65	l = L_clk_mult[(cccr >> 0) & 0x1f];
	66	m = M_clk_mult[(cccr >> 5) & 0x03];
	67	n2 = N2_clk_mult[(cccr >> 7) & 0x07];
	68
	69	L = l * BASE_CLK;
	70	M = m * L;
	71	N = n2 * M / 2;
	72
	73	if(info)
	74	{
	75	L += 5000;
	76	printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
	77	L / 1000000, (L % 1000000) / 10000, l );
	78	M += 5000;
	79	printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
	80	M / 1000000, (M % 1000000) / 10000, m );
	81	N += 5000;
	82	printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
	83	N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
	84	(turbo & 1) ? "" : "in" );
	85	}
	86
	87	return (turbo & 1) ? (N/1000) : (M/1000);
	88	}
	89
1da177e4 LT	90	/*
	91	* Return the current memory clock frequency in units of 10kHz
	92	*/
15a40333	93	unsigned int pxa25x_get_memclk_frequency_10khz(void)
1da177e4 LT	94	{
	95	return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000;
	96	}
	97
a6dba20c RK	98	static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk)
	99	{
	100	return pxa25x_get_memclk_frequency_10khz() * 10000;
	101	}
	102
	103	static const struct clkops clk_pxa25x_lcd_ops = {
	104	.enable = clk_cken_enable,
	105	.disable = clk_cken_disable,
	106	.getrate = clk_pxa25x_lcd_getrate,
	107	};
	108
	109	/*
	110	* 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
	111	* 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
	112	* 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
	113	*/
	114	static struct clk pxa25x_clks[] = {
	115	INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev),
	116	INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev),
	117	INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev),
a6dba20c	118	INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev),
435b6e94	119	INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL),
a6dba20c RK	120	INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa_device_udc.dev),
	121	INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev),
	122	INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev),
	123	/*
	124	INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL),
	125	INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL),
	126	INIT_CKEN("SSPCLK", SSP, 3686400, 0, NULL),
	127	INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL),
	128	INIT_CKEN("NSSPCLK", NSSP, 3686400, 0, NULL),
a6dba20c	129	*/
435b6e94	130	INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL),
a6dba20c RK	131	};
a6dba20c RK	132
a8fa3f0c	133	#ifdef CONFIG_PM
8775420d	134
711be5cc EM	135	#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
	136	#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
	137
	138	#define RESTORE_GPLEVEL(n) do { \
	139	GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \
	140	GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \
	141	} while (0)
	142
	143	/*
	144	* List of global PXA peripheral registers to preserve.
	145	* More ones like CP and general purpose register values are preserved
	146	* with the stack pointer in sleep.S.
	147	*/
	148	enum { SLEEP_SAVE_START = 0,
	149
	150	SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2,
	151	SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2,
	152	SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2,
	153	SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2,
	154	SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2,
	155
	156	SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
	157	SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
	158	SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
	159
	160	SLEEP_SAVE_PSTR,
	161
	162	SLEEP_SAVE_ICMR,
	163	SLEEP_SAVE_CKEN,
	164
	165	SLEEP_SAVE_SIZE
	166	};
	167
	168
	169	static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
	170	{
	171	SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2);
	172	SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2);
	173	SAVE(GRER0); SAVE(GRER1); SAVE(GRER2);
	174	SAVE(GFER0); SAVE(GFER1); SAVE(GFER2);
	175	SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2);
	176
	177	SAVE(GAFR0_L); SAVE(GAFR0_U);
	178	SAVE(GAFR1_L); SAVE(GAFR1_U);
	179	SAVE(GAFR2_L); SAVE(GAFR2_U);
	180
56b11288	181	SAVE(ICMR); ICMR = 0;
711be5cc EM	182	SAVE(CKEN);
711be5cc EM	183	SAVE(PSTR);
56b11288 RP	184
	185	/* Clear GPIO transition detect bits */
	186	GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2;
711be5cc EM	187	}
	188
	189	static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
	190	{
56b11288 RP	191	/* ensure not to come back here if it wasn't intended */
	192	PSPR = 0;
	193
711be5cc EM	194	/* restore registers */
	195	RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); RESTORE_GPLEVEL(2);
	196	RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2);
	197	RESTORE(GAFR0_L); RESTORE(GAFR0_U);
	198	RESTORE(GAFR1_L); RESTORE(GAFR1_U);
	199	RESTORE(GAFR2_L); RESTORE(GAFR2_U);
	200	RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2);
	201	RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2);
	202	RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);
	203
56b11288 RP	204	PSSR = PSSR_RDH \| PSSR_PH;
56b11288 RP	205
711be5cc	206	RESTORE(CKEN);
56b11288 RP	207
	208	ICLR = 0;
	209	ICCR = 1;
711be5cc EM	210	RESTORE(ICMR);
	211	RESTORE(PSTR);
	212	}
	213
	214	static void pxa25x_cpu_pm_enter(suspend_state_t state)
8775420d	215	{
8775420d TP	216	CKEN = 0;
	217
	218	switch (state) {
	219	case PM_SUSPEND_MEM:
	220	/* set resume return address */
	221	PSPR = virt_to_phys(pxa_cpu_resume);
b750a093	222	pxa25x_cpu_suspend(PWRMODE_SLEEP);
8775420d TP	223	break;
	224	}
	225	}
a8fa3f0c	226
711be5cc EM	227	static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
711be5cc EM	228	.save_size = SLEEP_SAVE_SIZE,
26398a70	229	.valid = suspend_valid_only_mem,
711be5cc EM	230	.save = pxa25x_cpu_pm_save,
	231	.restore = pxa25x_cpu_pm_restore,
	232	.enter = pxa25x_cpu_pm_enter,
e176bb05	233	};
711be5cc EM	234
	235	static void __init pxa25x_init_pm(void)
	236	{
	237	pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
	238	}
a8fa3f0c	239	#endif
e176bb05	240
c95530c7	241	/* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
	242	*/
	243
	244	static int pxa25x_set_wake(unsigned int irq, unsigned int on)
	245	{
	246	int gpio = IRQ_TO_GPIO(irq);
	247	uint32_t gpio_bit, mask = 0;
	248
	249	if (gpio >= 0 && gpio <= 15) {
	250	gpio_bit = GPIO_bit(gpio);
	251	mask = gpio_bit;
	252	if (on) {
	253	if (GRER(gpio) \| gpio_bit)
	254	PRER \|= gpio_bit;
	255	else
	256	PRER &= ~gpio_bit;
	257
	258	if (GFER(gpio) \| gpio_bit)
	259	PFER \|= gpio_bit;
	260	else
	261	PFER &= ~gpio_bit;
	262	}
	263	goto set_pwer;
	264	}
	265
	266	if (irq == IRQ_RTCAlrm) {
	267	mask = PWER_RTC;
	268	goto set_pwer;
	269	}
	270
	271	return -EINVAL;
	272
	273	set_pwer:
	274	if (on)
	275	PWER \|= mask;
	276	else
	277	PWER &=~mask;
	278
	279	return 0;
	280	}
	281
cd49104d EM	282	void __init pxa25x_init_irq(void)
	283	{
	284	pxa_init_irq_low();
	285	pxa_init_irq_gpio(85);
c95530c7	286	pxa_init_irq_set_wake(pxa25x_set_wake);
cd49104d EM	287	}
cd49104d EM	288
34f3231f	289	static struct platform_device *pxa25x_devices[] __initdata = {
e09d02e1 EM	290	&pxa_device_mci,
	291	&pxa_device_udc,
	292	&pxa_device_fb,
	293	&pxa_device_ffuart,
	294	&pxa_device_btuart,
	295	&pxa_device_stuart,
	296	&pxa_device_i2c,
	297	&pxa_device_i2s,
	298	&pxa_device_ficp,
	299	&pxa_device_rtc,
34f3231f RK	300	};
34f3231f RK	301
e176bb05 RK	302	static int __init pxa25x_init(void)
e176bb05 RK	303	{
f53f066c EM	304	int ret = 0;
f53f066c EM	305
e176bb05	306	if (cpu_is_pxa21x() \|\| cpu_is_pxa25x()) {
a6dba20c RK	307	clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks));
a6dba20c RK	308
f53f066c EM	309	if ((ret = pxa_init_dma(16)))
f53f066c EM	310	return ret;
e176bb05	311	#ifdef CONFIG_PM
711be5cc	312	pxa25x_init_pm();
e176bb05	313	#endif
34f3231f RK	314	ret = platform_add_devices(pxa25x_devices,
34f3231f RK	315	ARRAY_SIZE(pxa25x_devices));
e176bb05	316	}
34f3231f RK	317	/* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
34f3231f RK	318	if (cpu_is_pxa25x())
e09d02e1	319	ret = platform_device_register(&pxa_device_hwuart);
34f3231f RK	320
34f3231f RK	321	return ret;
e176bb05 RK	322	}
	323
	324	subsys_initcall(pxa25x_init);