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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-pxa/pxa25x.c | |
3 | * | |
4 | * Author: Nicolas Pitre | |
5 | * Created: Jun 15, 2001 | |
6 | * Copyright: MontaVista Software Inc. | |
7 | * | |
8 | * Code specific to PXA21x/25x/26x variants. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * Since this file should be linked before any other machine specific file, | |
15 | * the __initcall() here will be executed first. This serves as default | |
16 | * initialization stuff for PXA machines which can be overridden later if | |
17 | * need be. | |
18 | */ | |
19 | #include <linux/module.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/init.h> | |
34f3231f | 22 | #include <linux/platform_device.h> |
95d9ffbe | 23 | #include <linux/suspend.h> |
c0165504 | 24 | #include <linux/sysdev.h> |
1da177e4 | 25 | |
a09e64fb RK |
26 | #include <mach/hardware.h> |
27 | #include <mach/irqs.h> | |
28 | #include <mach/pxa-regs.h> | |
29 | #include <mach/pxa2xx-regs.h> | |
30 | #include <mach/mfp-pxa25x.h> | |
afd2fc02 | 31 | #include <mach/reset.h> |
a09e64fb RK |
32 | #include <mach/pm.h> |
33 | #include <mach/dma.h> | |
1da177e4 LT |
34 | |
35 | #include "generic.h" | |
46c41e62 | 36 | #include "devices.h" |
a6dba20c | 37 | #include "clock.h" |
1da177e4 LT |
38 | |
39 | /* | |
40 | * Various clock factors driven by the CCCR register. | |
41 | */ | |
42 | ||
43 | /* Crystal Frequency to Memory Frequency Multiplier (L) */ | |
44 | static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, }; | |
45 | ||
46 | /* Memory Frequency to Run Mode Frequency Multiplier (M) */ | |
47 | static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 }; | |
48 | ||
49 | /* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */ | |
50 | /* Note: we store the value N * 2 here. */ | |
51 | static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 }; | |
52 | ||
53 | /* Crystal clock */ | |
54 | #define BASE_CLK 3686400 | |
55 | ||
56 | /* | |
57 | * Get the clock frequency as reflected by CCCR and the turbo flag. | |
58 | * We assume these values have been applied via a fcs. | |
59 | * If info is not 0 we also display the current settings. | |
60 | */ | |
15a40333 | 61 | unsigned int pxa25x_get_clk_frequency_khz(int info) |
1da177e4 LT |
62 | { |
63 | unsigned long cccr, turbo; | |
64 | unsigned int l, L, m, M, n2, N; | |
65 | ||
66 | cccr = CCCR; | |
67 | asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) ); | |
68 | ||
69 | l = L_clk_mult[(cccr >> 0) & 0x1f]; | |
70 | m = M_clk_mult[(cccr >> 5) & 0x03]; | |
71 | n2 = N2_clk_mult[(cccr >> 7) & 0x07]; | |
72 | ||
73 | L = l * BASE_CLK; | |
74 | M = m * L; | |
75 | N = n2 * M / 2; | |
76 | ||
77 | if(info) | |
78 | { | |
79 | L += 5000; | |
80 | printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n", | |
81 | L / 1000000, (L % 1000000) / 10000, l ); | |
82 | M += 5000; | |
83 | printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n", | |
84 | M / 1000000, (M % 1000000) / 10000, m ); | |
85 | N += 5000; | |
86 | printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n", | |
87 | N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5, | |
88 | (turbo & 1) ? "" : "in" ); | |
89 | } | |
90 | ||
91 | return (turbo & 1) ? (N/1000) : (M/1000); | |
92 | } | |
93 | ||
1da177e4 LT |
94 | /* |
95 | * Return the current memory clock frequency in units of 10kHz | |
96 | */ | |
15a40333 | 97 | unsigned int pxa25x_get_memclk_frequency_10khz(void) |
1da177e4 LT |
98 | { |
99 | return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000; | |
100 | } | |
101 | ||
a6dba20c RK |
102 | static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk) |
103 | { | |
104 | return pxa25x_get_memclk_frequency_10khz() * 10000; | |
105 | } | |
106 | ||
107 | static const struct clkops clk_pxa25x_lcd_ops = { | |
108 | .enable = clk_cken_enable, | |
109 | .disable = clk_cken_disable, | |
110 | .getrate = clk_pxa25x_lcd_getrate, | |
111 | }; | |
112 | ||
ed847782 IM |
113 | static unsigned long gpio12_config_32k[] = { |
114 | GPIO12_32KHz, | |
115 | }; | |
116 | ||
117 | static unsigned long gpio12_config_gpio[] = { | |
118 | GPIO12_GPIO, | |
119 | }; | |
120 | ||
121 | static void clk_gpio12_enable(struct clk *clk) | |
122 | { | |
123 | pxa2xx_mfp_config(gpio12_config_32k, 1); | |
124 | } | |
125 | ||
126 | static void clk_gpio12_disable(struct clk *clk) | |
127 | { | |
128 | pxa2xx_mfp_config(gpio12_config_gpio, 1); | |
129 | } | |
130 | ||
131 | static const struct clkops clk_pxa25x_gpio12_ops = { | |
132 | .enable = clk_gpio12_enable, | |
133 | .disable = clk_gpio12_disable, | |
134 | }; | |
135 | ||
13f75582 IM |
136 | static unsigned long gpio11_config_3m6[] = { |
137 | GPIO11_3_6MHz, | |
138 | }; | |
139 | ||
140 | static unsigned long gpio11_config_gpio[] = { | |
141 | GPIO11_GPIO, | |
142 | }; | |
143 | ||
144 | static void clk_gpio11_enable(struct clk *clk) | |
145 | { | |
146 | pxa2xx_mfp_config(gpio11_config_3m6, 1); | |
147 | } | |
148 | ||
149 | static void clk_gpio11_disable(struct clk *clk) | |
150 | { | |
151 | pxa2xx_mfp_config(gpio11_config_gpio, 1); | |
152 | } | |
153 | ||
154 | static const struct clkops clk_pxa25x_gpio11_ops = { | |
155 | .enable = clk_gpio11_enable, | |
156 | .disable = clk_gpio11_disable, | |
157 | }; | |
158 | ||
a6dba20c RK |
159 | /* |
160 | * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz) | |
161 | * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz | |
162 | * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly) | |
163 | */ | |
e01dbdb4 DB |
164 | static struct clk pxa25x_hwuart_clk = |
165 | INIT_CKEN("UARTCLK", HWUART, 14745600, 1, &pxa_device_hwuart.dev) | |
166 | ; | |
167 | ||
bdb08cb2 | 168 | /* |
c1ed406c | 169 | * PXA 2xx clock declarations. |
bdb08cb2 | 170 | */ |
a6dba20c RK |
171 | static struct clk pxa25x_clks[] = { |
172 | INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev), | |
173 | INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev), | |
174 | INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev), | |
435b6e94 | 175 | INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL), |
7a857620 | 176 | INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa25x_device_udc.dev), |
13f75582 | 177 | INIT_CLK("GPIO11_CLK", &clk_pxa25x_gpio11_ops, 3686400, 0, NULL), |
ed847782 | 178 | INIT_CLK("GPIO12_CLK", &clk_pxa25x_gpio12_ops, 32768, 0, NULL), |
a6dba20c RK |
179 | INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev), |
180 | INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev), | |
d8e0db11 | 181 | |
182 | INIT_CKEN("SSPCLK", SSP, 3686400, 0, &pxa25x_device_ssp.dev), | |
183 | INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev), | |
184 | INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev), | |
75540c1a | 185 | INIT_CKEN("PWMCLK", PWM0, 3686400, 0, &pxa25x_device_pwm0.dev), |
186 | INIT_CKEN("PWMCLK", PWM1, 3686400, 0, &pxa25x_device_pwm1.dev), | |
d8e0db11 | 187 | |
27b98a67 MB |
188 | INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL), |
189 | ||
a6dba20c | 190 | /* |
a6dba20c | 191 | INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL), |
a6dba20c | 192 | */ |
435b6e94 | 193 | INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL), |
a6dba20c RK |
194 | }; |
195 | ||
a8fa3f0c | 196 | #ifdef CONFIG_PM |
8775420d | 197 | |
711be5cc EM |
198 | #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x |
199 | #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] | |
200 | ||
711be5cc EM |
201 | /* |
202 | * List of global PXA peripheral registers to preserve. | |
203 | * More ones like CP and general purpose register values are preserved | |
204 | * with the stack pointer in sleep.S. | |
205 | */ | |
649de51b | 206 | enum { SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, |
711be5cc EM |
207 | |
208 | SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U, | |
209 | SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U, | |
210 | SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U, | |
211 | ||
212 | SLEEP_SAVE_PSTR, | |
213 | ||
711be5cc EM |
214 | SLEEP_SAVE_CKEN, |
215 | ||
649de51b | 216 | SLEEP_SAVE_COUNT |
711be5cc EM |
217 | }; |
218 | ||
219 | ||
220 | static void pxa25x_cpu_pm_save(unsigned long *sleep_save) | |
221 | { | |
711be5cc EM |
222 | SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); |
223 | ||
224 | SAVE(GAFR0_L); SAVE(GAFR0_U); | |
225 | SAVE(GAFR1_L); SAVE(GAFR1_U); | |
226 | SAVE(GAFR2_L); SAVE(GAFR2_U); | |
227 | ||
711be5cc EM |
228 | SAVE(CKEN); |
229 | SAVE(PSTR); | |
56b11288 RP |
230 | |
231 | /* Clear GPIO transition detect bits */ | |
232 | GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2; | |
711be5cc EM |
233 | } |
234 | ||
235 | static void pxa25x_cpu_pm_restore(unsigned long *sleep_save) | |
236 | { | |
56b11288 RP |
237 | /* ensure not to come back here if it wasn't intended */ |
238 | PSPR = 0; | |
239 | ||
711be5cc | 240 | /* restore registers */ |
711be5cc EM |
241 | RESTORE(GAFR0_L); RESTORE(GAFR0_U); |
242 | RESTORE(GAFR1_L); RESTORE(GAFR1_U); | |
243 | RESTORE(GAFR2_L); RESTORE(GAFR2_U); | |
711be5cc EM |
244 | RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); |
245 | ||
56b11288 RP |
246 | PSSR = PSSR_RDH | PSSR_PH; |
247 | ||
711be5cc | 248 | RESTORE(CKEN); |
711be5cc EM |
249 | RESTORE(PSTR); |
250 | } | |
251 | ||
252 | static void pxa25x_cpu_pm_enter(suspend_state_t state) | |
8775420d | 253 | { |
dc38e2ad RK |
254 | /* Clear reset status */ |
255 | RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR; | |
256 | ||
8775420d TP |
257 | switch (state) { |
258 | case PM_SUSPEND_MEM: | |
259 | /* set resume return address */ | |
260 | PSPR = virt_to_phys(pxa_cpu_resume); | |
b750a093 | 261 | pxa25x_cpu_suspend(PWRMODE_SLEEP); |
8775420d TP |
262 | break; |
263 | } | |
264 | } | |
a8fa3f0c | 265 | |
711be5cc | 266 | static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = { |
649de51b | 267 | .save_count = SLEEP_SAVE_COUNT, |
26398a70 | 268 | .valid = suspend_valid_only_mem, |
711be5cc EM |
269 | .save = pxa25x_cpu_pm_save, |
270 | .restore = pxa25x_cpu_pm_restore, | |
271 | .enter = pxa25x_cpu_pm_enter, | |
e176bb05 | 272 | }; |
711be5cc EM |
273 | |
274 | static void __init pxa25x_init_pm(void) | |
275 | { | |
276 | pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns; | |
277 | } | |
f79299ca | 278 | #else |
279 | static inline void pxa25x_init_pm(void) {} | |
a8fa3f0c | 280 | #endif |
e176bb05 | 281 | |
c95530c7 | 282 | /* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm |
283 | */ | |
284 | ||
285 | static int pxa25x_set_wake(unsigned int irq, unsigned int on) | |
286 | { | |
287 | int gpio = IRQ_TO_GPIO(irq); | |
c0a596d6 | 288 | uint32_t mask = 0; |
289 | ||
290 | if (gpio >= 0 && gpio < 85) | |
291 | return gpio_set_wake(gpio, on); | |
c95530c7 | 292 | |
293 | if (irq == IRQ_RTCAlrm) { | |
294 | mask = PWER_RTC; | |
295 | goto set_pwer; | |
296 | } | |
297 | ||
298 | return -EINVAL; | |
299 | ||
300 | set_pwer: | |
301 | if (on) | |
302 | PWER |= mask; | |
303 | else | |
304 | PWER &=~mask; | |
305 | ||
306 | return 0; | |
307 | } | |
308 | ||
cd49104d EM |
309 | void __init pxa25x_init_irq(void) |
310 | { | |
b9e25ace | 311 | pxa_init_irq(32, pxa25x_set_wake); |
312 | pxa_init_gpio(85, pxa25x_set_wake); | |
cd49104d EM |
313 | } |
314 | ||
34f3231f | 315 | static struct platform_device *pxa25x_devices[] __initdata = { |
7a857620 | 316 | &pxa25x_device_udc, |
e09d02e1 EM |
317 | &pxa_device_ffuart, |
318 | &pxa_device_btuart, | |
319 | &pxa_device_stuart, | |
e09d02e1 | 320 | &pxa_device_i2s, |
e09d02e1 | 321 | &pxa_device_rtc, |
d8e0db11 | 322 | &pxa25x_device_ssp, |
323 | &pxa25x_device_nssp, | |
324 | &pxa25x_device_assp, | |
75540c1a | 325 | &pxa25x_device_pwm0, |
326 | &pxa25x_device_pwm1, | |
34f3231f RK |
327 | }; |
328 | ||
c0165504 | 329 | static struct sys_device pxa25x_sysdev[] = { |
330 | { | |
331 | .cls = &pxa_irq_sysclass, | |
16dfdbf0 | 332 | }, { |
333 | .cls = &pxa_gpio_sysclass, | |
c0165504 | 334 | }, |
335 | }; | |
336 | ||
e176bb05 RK |
337 | static int __init pxa25x_init(void) |
338 | { | |
c0165504 | 339 | int i, ret = 0; |
f53f066c | 340 | |
e01dbdb4 | 341 | /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */ |
aa9ae8eb | 342 | if (cpu_is_pxa255()) |
e01dbdb4 DB |
343 | clks_register(&pxa25x_hwuart_clk, 1); |
344 | ||
e176bb05 | 345 | if (cpu_is_pxa21x() || cpu_is_pxa25x()) { |
04fef228 EM |
346 | |
347 | reset_status = RCSR; | |
348 | ||
a6dba20c RK |
349 | clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks)); |
350 | ||
f53f066c EM |
351 | if ((ret = pxa_init_dma(16))) |
352 | return ret; | |
f79299ca | 353 | |
711be5cc | 354 | pxa25x_init_pm(); |
f79299ca | 355 | |
c0165504 | 356 | for (i = 0; i < ARRAY_SIZE(pxa25x_sysdev); i++) { |
357 | ret = sysdev_register(&pxa25x_sysdev[i]); | |
358 | if (ret) | |
359 | pr_err("failed to register sysdev[%d]\n", i); | |
360 | } | |
361 | ||
34f3231f RK |
362 | ret = platform_add_devices(pxa25x_devices, |
363 | ARRAY_SIZE(pxa25x_devices)); | |
c0165504 | 364 | if (ret) |
365 | return ret; | |
e176bb05 | 366 | } |
c0165504 | 367 | |
34f3231f | 368 | /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */ |
aa9ae8eb | 369 | if (cpu_is_pxa255()) |
e09d02e1 | 370 | ret = platform_device_register(&pxa_device_hwuart); |
34f3231f RK |
371 | |
372 | return ret; | |
e176bb05 RK |
373 | } |
374 | ||
1c104e0e | 375 | postcore_initcall(pxa25x_init); |