[deliverable/linux.git] / arch / arm / mach-pxa / pxa25x.c

/*
 *  linux/arch/arm/mach-pxa/pxa25x.c
 *
 *  Author:	Nicolas Pitre
 *  Created:	Jun 15, 2001
 *  Copyright:	MontaVista Software Inc.
 *
 * Code specific to PXA21x/25x/26x variants.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Since this file should be linked before any other machine specific file,
 * the __initcall() here will be executed first.  This serves as default
 * initialization stuff for PXA machines which can be overridden later if
 * need be.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/pm.h>

#include <asm/hardware.h>
#include <asm/arch/irqs.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pm.h>
#include <asm/arch/dma.h>

#include "generic.h"
#include "devices.h"

/*
 * Various clock factors driven by the CCCR register.
 */

/* Crystal Frequency to Memory Frequency Multiplier (L) */
static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };

/* Memory Frequency to Run Mode Frequency Multiplier (M) */
static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };

/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
/* Note: we store the value N * 2 here. */
static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };

/* Crystal clock */
#define BASE_CLK	3686400

/*
 * Get the clock frequency as reflected by CCCR and the turbo flag.
 * We assume these values have been applied via a fcs.
 * If info is not 0 we also display the current settings.
 */
unsigned int get_clk_frequency_khz(int info)
{
	unsigned long cccr, turbo;
	unsigned int l, L, m, M, n2, N;

	cccr = CCCR;
	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );

	l  =  L_clk_mult[(cccr >> 0) & 0x1f];
	m  =  M_clk_mult[(cccr >> 5) & 0x03];
	n2 = N2_clk_mult[(cccr >> 7) & 0x07];

	L = l * BASE_CLK;
	M = m * L;
	N = n2 * M / 2;

	if(info)
	{
		L += 5000;
		printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
			L / 1000000, (L % 1000000) / 10000, l );
		M += 5000;
		printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
			M / 1000000, (M % 1000000) / 10000, m );
		N += 5000;
		printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
			N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
			(turbo & 1) ? "" : "in" );
	}

	return (turbo & 1) ? (N/1000) : (M/1000);
}

EXPORT_SYMBOL(get_clk_frequency_khz);

/*
 * Return the current memory clock frequency in units of 10kHz
 */
unsigned int get_memclk_frequency_10khz(void)
{
	return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000;
}

EXPORT_SYMBOL(get_memclk_frequency_10khz);

/*
 * Return the current LCD clock frequency in units of 10kHz
 */
unsigned int get_lcdclk_frequency_10khz(void)
{
	return get_memclk_frequency_10khz();
}

EXPORT_SYMBOL(get_lcdclk_frequency_10khz);

#ifdef CONFIG_PM

#define SAVE(x)		sleep_save[SLEEP_SAVE_##x] = x
#define RESTORE(x)	x = sleep_save[SLEEP_SAVE_##x]

#define RESTORE_GPLEVEL(n) do { \
	GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \
	GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \
} while (0)

/*
 * List of global PXA peripheral registers to preserve.
 * More ones like CP and general purpose register values are preserved
 * with the stack pointer in sleep.S.
 */
enum {	SLEEP_SAVE_START = 0,

	SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2,
	SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2,
	SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2,
	SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2,
	SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2,

	SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
	SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
	SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,

	SLEEP_SAVE_PSTR,

	SLEEP_SAVE_ICMR,
	SLEEP_SAVE_CKEN,

	SLEEP_SAVE_SIZE
};


static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
{
	SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2);
	SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2);
	SAVE(GRER0); SAVE(GRER1); SAVE(GRER2);
	SAVE(GFER0); SAVE(GFER1); SAVE(GFER2);
	SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2);

	SAVE(GAFR0_L); SAVE(GAFR0_U);
	SAVE(GAFR1_L); SAVE(GAFR1_U);
	SAVE(GAFR2_L); SAVE(GAFR2_U);

	SAVE(ICMR);
	SAVE(CKEN);
	SAVE(PSTR);
}

static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
{
	/* restore registers */
	RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); RESTORE_GPLEVEL(2);
	RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2);
	RESTORE(GAFR0_L); RESTORE(GAFR0_U);
	RESTORE(GAFR1_L); RESTORE(GAFR1_U);
	RESTORE(GAFR2_L); RESTORE(GAFR2_U);
	RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2);
	RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2);
	RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);

	RESTORE(CKEN);
	RESTORE(ICMR);
	RESTORE(PSTR);
}

static void pxa25x_cpu_pm_enter(suspend_state_t state)
{
	extern void pxa_cpu_suspend(unsigned int);
	extern void pxa_cpu_resume(void);

	CKEN = 0;

	switch (state) {
	case PM_SUSPEND_MEM:
		/* set resume return address */
		PSPR = virt_to_phys(pxa_cpu_resume);
		pxa_cpu_suspend(PWRMODE_SLEEP);
		break;
	}
}

static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
	.save_size	= SLEEP_SAVE_SIZE,
	.valid		= pm_valid_only_mem,
	.save		= pxa25x_cpu_pm_save,
	.restore	= pxa25x_cpu_pm_restore,
	.enter		= pxa25x_cpu_pm_enter,
};

static void __init pxa25x_init_pm(void)
{
	pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
}
#endif

void __init pxa25x_init_irq(void)
{
	pxa_init_irq_low();
	pxa_init_irq_gpio(85);
}

static struct platform_device *pxa25x_devices[] __initdata = {
	&pxa_device_mci,
	&pxa_device_udc,
	&pxa_device_fb,
	&pxa_device_ffuart,
	&pxa_device_btuart,
	&pxa_device_stuart,
	&pxa_device_i2c,
	&pxa_device_i2s,
	&pxa_device_ficp,
	&pxa_device_rtc,
};

static int __init pxa25x_init(void)
{
	int ret = 0;

	if (cpu_is_pxa21x() || cpu_is_pxa25x()) {
		if ((ret = pxa_init_dma(16)))
			return ret;
#ifdef CONFIG_PM
		pxa25x_init_pm();
#endif
		ret = platform_add_devices(pxa25x_devices,
					   ARRAY_SIZE(pxa25x_devices));
	}
	/* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
	if (cpu_is_pxa25x())
		ret = platform_device_register(&pxa_device_hwuart);

	return ret;
}

subsys_initcall(pxa25x_init);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-pxa/pxa25x.c
	3	*
	4	* Author: Nicolas Pitre
	5	* Created: Jun 15, 2001
	6	* Copyright: MontaVista Software Inc.
	7	*
	8	* Code specific to PXA21x/25x/26x variants.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*
	14	* Since this file should be linked before any other machine specific file,
	15	* the __initcall() here will be executed first. This serves as default
	16	* initialization stuff for PXA machines which can be overridden later if
	17	* need be.
	18	*/
	19	#include <linux/module.h>
	20	#include <linux/kernel.h>
	21	#include <linux/init.h>
34f3231f	22	#include <linux/platform_device.h>
1da177e4 LT	23	#include <linux/pm.h>
	24
	25	#include <asm/hardware.h>
cd49104d	26	#include <asm/arch/irqs.h>
1da177e4	27	#include <asm/arch/pxa-regs.h>
e176bb05	28	#include <asm/arch/pm.h>
f53f066c	29	#include <asm/arch/dma.h>
1da177e4 LT	30
1da177e4 LT	31	#include "generic.h"
46c41e62	32	#include "devices.h"
1da177e4 LT	33
	34	/*
	35	* Various clock factors driven by the CCCR register.
	36	*/
	37
	38	/* Crystal Frequency to Memory Frequency Multiplier (L) */
	39	static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
	40
	41	/* Memory Frequency to Run Mode Frequency Multiplier (M) */
	42	static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
	43
	44	/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
	45	/* Note: we store the value N * 2 here. */
	46	static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
	47
	48	/* Crystal clock */
	49	#define BASE_CLK 3686400
	50
	51	/*
	52	* Get the clock frequency as reflected by CCCR and the turbo flag.
	53	* We assume these values have been applied via a fcs.
	54	* If info is not 0 we also display the current settings.
	55	*/
	56	unsigned int get_clk_frequency_khz(int info)
	57	{
	58	unsigned long cccr, turbo;
	59	unsigned int l, L, m, M, n2, N;
	60
	61	cccr = CCCR;
	62	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
	63
	64	l = L_clk_mult[(cccr >> 0) & 0x1f];
	65	m = M_clk_mult[(cccr >> 5) & 0x03];
	66	n2 = N2_clk_mult[(cccr >> 7) & 0x07];
	67
	68	L = l * BASE_CLK;
	69	M = m * L;
	70	N = n2 * M / 2;
	71
	72	if(info)
	73	{
	74	L += 5000;
	75	printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
	76	L / 1000000, (L % 1000000) / 10000, l );
	77	M += 5000;
	78	printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
	79	M / 1000000, (M % 1000000) / 10000, m );
	80	N += 5000;
	81	printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
	82	N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
	83	(turbo & 1) ? "" : "in" );
	84	}
	85
	86	return (turbo & 1) ? (N/1000) : (M/1000);
	87	}
	88
	89	EXPORT_SYMBOL(get_clk_frequency_khz);
	90
	91	/*
	92	* Return the current memory clock frequency in units of 10kHz
	93	*/
	94	unsigned int get_memclk_frequency_10khz(void)
	95	{
	96	return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000;
97	}
98
99	EXPORT_SYMBOL(get_memclk_frequency_10khz);
100
101	/*
102	* Return the current LCD clock frequency in units of 10kHz
103	*/
104	unsigned int get_lcdclk_frequency_10khz(void)
105	{
106	return get_memclk_frequency_10khz();
107	}
108
109	EXPORT_SYMBOL(get_lcdclk_frequency_10khz);
8775420d	110
a8fa3f0c	111	#ifdef CONFIG_PM
8775420d	112
711be5cc EM	113	#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
	114	#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
	115
	116	#define RESTORE_GPLEVEL(n) do { \
	117	GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \
	118	GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \
	119	} while (0)
	120
	121	/*
	122	* List of global PXA peripheral registers to preserve.
	123	* More ones like CP and general purpose register values are preserved
	124	* with the stack pointer in sleep.S.
	125	*/
	126	enum { SLEEP_SAVE_START = 0,
	127
	128	SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2,
	129	SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2,
	130	SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2,
	131	SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2,
	132	SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2,
	133
	134	SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
	135	SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
	136	SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
	137
	138	SLEEP_SAVE_PSTR,
	139
	140	SLEEP_SAVE_ICMR,
	141	SLEEP_SAVE_CKEN,
	142
	143	SLEEP_SAVE_SIZE
	144	};
	145
	146
	147	static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
	148	{
	149	SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2);
	150	SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2);
	151	SAVE(GRER0); SAVE(GRER1); SAVE(GRER2);
	152	SAVE(GFER0); SAVE(GFER1); SAVE(GFER2);
	153	SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2);
	154
	155	SAVE(GAFR0_L); SAVE(GAFR0_U);
	156	SAVE(GAFR1_L); SAVE(GAFR1_U);
	157	SAVE(GAFR2_L); SAVE(GAFR2_U);
	158
	159	SAVE(ICMR);
	160	SAVE(CKEN);
	161	SAVE(PSTR);
	162	}
	163
	164	static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
	165	{
	166	/* restore registers */
	167	RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); RESTORE_GPLEVEL(2);
	168	RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2);
	169	RESTORE(GAFR0_L); RESTORE(GAFR0_U);
	170	RESTORE(GAFR1_L); RESTORE(GAFR1_U);
	171	RESTORE(GAFR2_L); RESTORE(GAFR2_U);
	172	RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2);
	173	RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2);
	174	RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);
	175
	176	RESTORE(CKEN);
177	RESTORE(ICMR);
178	RESTORE(PSTR);
179	}
180
181	static void pxa25x_cpu_pm_enter(suspend_state_t state)
8775420d TP	182	{
	183	extern void pxa_cpu_suspend(unsigned int);
	184	extern void pxa_cpu_resume(void);
	185
	186	CKEN = 0;
	187
	188	switch (state) {
	189	case PM_SUSPEND_MEM:
	190	/* set resume return address */
	191	PSPR = virt_to_phys(pxa_cpu_resume);
80a18573	192	pxa_cpu_suspend(PWRMODE_SLEEP);
8775420d TP	193	break;
	194	}
	195	}
a8fa3f0c	196
711be5cc EM	197	static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
711be5cc EM	198	.save_size = SLEEP_SAVE_SIZE,
e176bb05	199	.valid = pm_valid_only_mem,
711be5cc EM	200	.save = pxa25x_cpu_pm_save,
	201	.restore = pxa25x_cpu_pm_restore,
	202	.enter = pxa25x_cpu_pm_enter,
e176bb05	203	};
711be5cc EM	204
	205	static void __init pxa25x_init_pm(void)
	206	{
	207	pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
	208	}
a8fa3f0c	209	#endif
e176bb05	210
cd49104d EM	211	void __init pxa25x_init_irq(void)
	212	{
	213	pxa_init_irq_low();
	214	pxa_init_irq_gpio(85);
	215	}
	216
34f3231f	217	static struct platform_device *pxa25x_devices[] __initdata = {
e09d02e1 EM	218	&pxa_device_mci,
	219	&pxa_device_udc,
	220	&pxa_device_fb,
	221	&pxa_device_ffuart,
	222	&pxa_device_btuart,
	223	&pxa_device_stuart,
	224	&pxa_device_i2c,
	225	&pxa_device_i2s,
	226	&pxa_device_ficp,
	227	&pxa_device_rtc,
34f3231f RK	228	};
34f3231f RK	229
e176bb05 RK	230	static int __init pxa25x_init(void)
e176bb05 RK	231	{
f53f066c EM	232	int ret = 0;
f53f066c EM	233
e176bb05	234	if (cpu_is_pxa21x() \|\| cpu_is_pxa25x()) {
f53f066c EM	235	if ((ret = pxa_init_dma(16)))
f53f066c EM	236	return ret;
e176bb05	237	#ifdef CONFIG_PM
711be5cc	238	pxa25x_init_pm();
e176bb05	239	#endif
34f3231f RK	240	ret = platform_add_devices(pxa25x_devices,
34f3231f RK	241	ARRAY_SIZE(pxa25x_devices));
e176bb05	242	}
34f3231f RK	243	/* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
34f3231f RK	244	if (cpu_is_pxa25x())
e09d02e1	245	ret = platform_device_register(&pxa_device_hwuart);
34f3231f RK	246
34f3231f RK	247	return ret;
e176bb05 RK	248	}
	249
	250	subsys_initcall(pxa25x_init);