[deliverable/linux.git] / arch / arm / mach-pxa / pxa25x.c

/*
 *  linux/arch/arm/mach-pxa/pxa25x.c
 *
 *  Author:	Nicolas Pitre
 *  Created:	Jun 15, 2001
 *  Copyright:	MontaVista Software Inc.
 *
 * Code specific to PXA21x/25x/26x variants.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Since this file should be linked before any other machine specific file,
 * the __initcall() here will be executed first.  This serves as default
 * initialization stuff for PXA machines which can be overridden later if
 * need be.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/suspend.h>
#include <linux/syscore_ops.h>
#include <linux/irq.h>

#include <asm/mach/map.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <mach/gpio.h>
#include <mach/pxa25x.h>
#include <mach/reset.h>
#include <mach/pm.h>
#include <mach/dma.h>
#include <mach/smemc.h>

#include "generic.h"
#include "devices.h"
#include "clock.h"

/*
 * Various clock factors driven by the CCCR register.
 */

/* Crystal Frequency to Memory Frequency Multiplier (L) */
static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };

/* Memory Frequency to Run Mode Frequency Multiplier (M) */
static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };

/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
/* Note: we store the value N * 2 here. */
static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };

/* Crystal clock */
#define BASE_CLK	3686400

/*
 * Get the clock frequency as reflected by CCCR and the turbo flag.
 * We assume these values have been applied via a fcs.
 * If info is not 0 we also display the current settings.
 */
unsigned int pxa25x_get_clk_frequency_khz(int info)
{
	unsigned long cccr, turbo;
	unsigned int l, L, m, M, n2, N;

	cccr = CCCR;
	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );

	l  =  L_clk_mult[(cccr >> 0) & 0x1f];
	m  =  M_clk_mult[(cccr >> 5) & 0x03];
	n2 = N2_clk_mult[(cccr >> 7) & 0x07];

	L = l * BASE_CLK;
	M = m * L;
	N = n2 * M / 2;

	if(info)
	{
		L += 5000;
		printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
			L / 1000000, (L % 1000000) / 10000, l );
		M += 5000;
		printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
			M / 1000000, (M % 1000000) / 10000, m );
		N += 5000;
		printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
			N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
			(turbo & 1) ? "" : "in" );
	}

	return (turbo & 1) ? (N/1000) : (M/1000);
}

static unsigned long clk_pxa25x_mem_getrate(struct clk *clk)
{
	return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK;
}

static const struct clkops clk_pxa25x_mem_ops = {
	.enable		= clk_dummy_enable,
	.disable	= clk_dummy_disable,
	.getrate	= clk_pxa25x_mem_getrate,
};

static const struct clkops clk_pxa25x_lcd_ops = {
	.enable		= clk_pxa2xx_cken_enable,
	.disable	= clk_pxa2xx_cken_disable,
	.getrate	= clk_pxa25x_mem_getrate,
};

static unsigned long gpio12_config_32k[] = {
	GPIO12_32KHz,
};

static unsigned long gpio12_config_gpio[] = {
	GPIO12_GPIO,
};

static void clk_gpio12_enable(struct clk *clk)
{
	pxa2xx_mfp_config(gpio12_config_32k, 1);
}

static void clk_gpio12_disable(struct clk *clk)
{
	pxa2xx_mfp_config(gpio12_config_gpio, 1);
}

static const struct clkops clk_pxa25x_gpio12_ops = {
	.enable         = clk_gpio12_enable,
	.disable        = clk_gpio12_disable,
};

static unsigned long gpio11_config_3m6[] = {
	GPIO11_3_6MHz,
};

static unsigned long gpio11_config_gpio[] = {
	GPIO11_GPIO,
};

static void clk_gpio11_enable(struct clk *clk)
{
	pxa2xx_mfp_config(gpio11_config_3m6, 1);
}

static void clk_gpio11_disable(struct clk *clk)
{
	pxa2xx_mfp_config(gpio11_config_gpio, 1);
}

static const struct clkops clk_pxa25x_gpio11_ops = {
	.enable         = clk_gpio11_enable,
	.disable        = clk_gpio11_disable,
};

/*
 * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
 * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
 * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
 */

/*
 * PXA 2xx clock declarations.
 */
static DEFINE_PXA2_CKEN(pxa25x_hwuart, HWUART, 14745600, 1);
static DEFINE_PXA2_CKEN(pxa25x_ffuart, FFUART, 14745600, 1);
static DEFINE_PXA2_CKEN(pxa25x_btuart, BTUART, 14745600, 1);
static DEFINE_PXA2_CKEN(pxa25x_stuart, STUART, 14745600, 1);
static DEFINE_PXA2_CKEN(pxa25x_usb, USB, 47923000, 5);
static DEFINE_PXA2_CKEN(pxa25x_mmc, MMC, 19169000, 0);
static DEFINE_PXA2_CKEN(pxa25x_i2c, I2C, 31949000, 0);
static DEFINE_PXA2_CKEN(pxa25x_ssp, SSP, 3686400, 0);
static DEFINE_PXA2_CKEN(pxa25x_nssp, NSSP, 3686400, 0);
static DEFINE_PXA2_CKEN(pxa25x_assp, ASSP, 3686400, 0);
static DEFINE_PXA2_CKEN(pxa25x_pwm0, PWM0, 3686400, 0);
static DEFINE_PXA2_CKEN(pxa25x_pwm1, PWM1, 3686400, 0);
static DEFINE_PXA2_CKEN(pxa25x_ac97, AC97, 24576000, 0);
static DEFINE_PXA2_CKEN(pxa25x_i2s, I2S, 14745600, 0);
static DEFINE_PXA2_CKEN(pxa25x_ficp, FICP, 47923000, 0);

static DEFINE_CK(pxa25x_lcd, LCD, &clk_pxa25x_lcd_ops);
static DEFINE_CLK(pxa25x_gpio11, &clk_pxa25x_gpio11_ops, 3686400, 0);
static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0);
static DEFINE_CLK(pxa25x_mem, &clk_pxa25x_mem_ops, 0, 0);

static struct clk_lookup pxa25x_clkregs[] = {
	INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL),
	INIT_CLKREG(&clk_pxa25x_ffuart, "pxa2xx-uart.0", NULL),
	INIT_CLKREG(&clk_pxa25x_btuart, "pxa2xx-uart.1", NULL),
	INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-uart.2", NULL),
	INIT_CLKREG(&clk_pxa25x_usb, "pxa25x-udc", NULL),
	INIT_CLKREG(&clk_pxa25x_mmc, "pxa2xx-mci.0", NULL),
	INIT_CLKREG(&clk_pxa25x_i2c, "pxa2xx-i2c.0", NULL),
	INIT_CLKREG(&clk_pxa25x_ssp, "pxa25x-ssp.0", NULL),
	INIT_CLKREG(&clk_pxa25x_nssp, "pxa25x-nssp.1", NULL),
	INIT_CLKREG(&clk_pxa25x_assp, "pxa25x-nssp.2", NULL),
	INIT_CLKREG(&clk_pxa25x_pwm0, "pxa25x-pwm.0", NULL),
	INIT_CLKREG(&clk_pxa25x_pwm1, "pxa25x-pwm.1", NULL),
	INIT_CLKREG(&clk_pxa25x_i2s, "pxa2xx-i2s", NULL),
	INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-ir", "UARTCLK"),
	INIT_CLKREG(&clk_pxa25x_ficp, "pxa2xx-ir", "FICPCLK"),
	INIT_CLKREG(&clk_pxa25x_ac97, NULL, "AC97CLK"),
	INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"),
	INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
	INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL),
};

static struct clk_lookup pxa25x_hwuart_clkreg =
	INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL);

#ifdef CONFIG_PM

#define SAVE(x)		sleep_save[SLEEP_SAVE_##x] = x
#define RESTORE(x)	x = sleep_save[SLEEP_SAVE_##x]

/*
 * List of global PXA peripheral registers to preserve.
 * More ones like CP and general purpose register values are preserved
 * with the stack pointer in sleep.S.
 */
enum {
	SLEEP_SAVE_PSTR,
	SLEEP_SAVE_COUNT
};


static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
{
	SAVE(PSTR);
}

static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
{
	RESTORE(PSTR);
}

static void pxa25x_cpu_pm_enter(suspend_state_t state)
{
	/* Clear reset status */
	RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;

	switch (state) {
	case PM_SUSPEND_MEM:
		pxa25x_cpu_suspend(PWRMODE_SLEEP, PLAT_PHYS_OFFSET - PAGE_OFFSET);
		break;
	}
}

static int pxa25x_cpu_pm_prepare(void)
{
	/* set resume return address */
	PSPR = virt_to_phys(cpu_resume);
	return 0;
}

static void pxa25x_cpu_pm_finish(void)
{
	/* ensure not to come back here if it wasn't intended */
	PSPR = 0;
}

static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
	.save_count	= SLEEP_SAVE_COUNT,
	.valid		= suspend_valid_only_mem,
	.save		= pxa25x_cpu_pm_save,
	.restore	= pxa25x_cpu_pm_restore,
	.enter		= pxa25x_cpu_pm_enter,
	.prepare	= pxa25x_cpu_pm_prepare,
	.finish		= pxa25x_cpu_pm_finish,
};

static void __init pxa25x_init_pm(void)
{
	pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
}
#else
static inline void pxa25x_init_pm(void) {}
#endif

/* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
 */

static int pxa25x_set_wake(struct irq_data *d, unsigned int on)
{
	int gpio = irq_to_gpio(d->irq);
	uint32_t mask = 0;

	if (gpio >= 0 && gpio < 85)
		return gpio_set_wake(gpio, on);

	if (d->irq == IRQ_RTCAlrm) {
		mask = PWER_RTC;
		goto set_pwer;
	}

	return -EINVAL;

set_pwer:
	if (on)
		PWER |= mask;
	else
		PWER &=~mask;

	return 0;
}

void __init pxa25x_init_irq(void)
{
	pxa_init_irq(32, pxa25x_set_wake);
	pxa_init_gpio(IRQ_GPIO_2_x, 2, 84, pxa25x_set_wake);
}

#ifdef CONFIG_CPU_PXA26x
void __init pxa26x_init_irq(void)
{
	pxa_init_irq(32, pxa25x_set_wake);
	pxa_init_gpio(IRQ_GPIO_2_x, 2, 89, pxa25x_set_wake);
}
#endif

static struct map_desc pxa25x_io_desc[] __initdata = {
	{	/* Mem Ctl */
		.virtual	= SMEMC_VIRT,
		.pfn		= __phys_to_pfn(PXA2XX_SMEMC_BASE),
		.length		= 0x00200000,
		.type		= MT_DEVICE
	},
};

void __init pxa25x_map_io(void)
{
	pxa_map_io();
	iotable_init(ARRAY_AND_SIZE(pxa25x_io_desc));
	pxa25x_get_clk_frequency_khz(1);
}

static struct platform_device *pxa25x_devices[] __initdata = {
	&pxa25x_device_udc,
	&pxa_device_pmu,
	&pxa_device_i2s,
	&sa1100_device_rtc,
	&pxa25x_device_ssp,
	&pxa25x_device_nssp,
	&pxa25x_device_assp,
	&pxa25x_device_pwm0,
	&pxa25x_device_pwm1,
	&pxa_device_asoc_platform,
};

static int __init pxa25x_init(void)
{
	int ret = 0;

	if (cpu_is_pxa25x()) {

		reset_status = RCSR;

		clkdev_add_table(pxa25x_clkregs, ARRAY_SIZE(pxa25x_clkregs));

		if ((ret = pxa_init_dma(IRQ_DMA, 16)))
			return ret;

		pxa25x_init_pm();

		register_syscore_ops(&pxa_irq_syscore_ops);
		register_syscore_ops(&pxa2xx_mfp_syscore_ops);
		register_syscore_ops(&pxa_gpio_syscore_ops);
		register_syscore_ops(&pxa2xx_clock_syscore_ops);

		ret = platform_add_devices(pxa25x_devices,
					   ARRAY_SIZE(pxa25x_devices));
		if (ret)
			return ret;
	}

	/* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */
	if (cpu_is_pxa255())
		clkdev_add(&pxa25x_hwuart_clkreg);

	return ret;
}

postcore_initcall(pxa25x_init);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-pxa/pxa25x.c
	3	*
	4	* Author: Nicolas Pitre
	5	* Created: Jun 15, 2001
	6	* Copyright: MontaVista Software Inc.
	7	*
	8	* Code specific to PXA21x/25x/26x variants.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*
	14	* Since this file should be linked before any other machine specific file,
	15	* the __initcall() here will be executed first. This serves as default
	16	* initialization stuff for PXA machines which can be overridden later if
	17	* need be.
	18	*/
	19	#include <linux/module.h>
	20	#include <linux/kernel.h>
	21	#include <linux/init.h>
34f3231f	22	#include <linux/platform_device.h>
95d9ffbe	23	#include <linux/suspend.h>
2eaa03b5	24	#include <linux/syscore_ops.h>
a3f4c927	25	#include <linux/irq.h>
1da177e4	26
851982c1	27	#include <asm/mach/map.h>
a09e64fb RK	28	#include <mach/hardware.h>
a09e64fb RK	29	#include <mach/irqs.h>
a58fbcd8	30	#include <mach/gpio.h>
51c62982	31	#include <mach/pxa25x.h>
afd2fc02	32	#include <mach/reset.h>
a09e64fb RK	33	#include <mach/pm.h>
a09e64fb RK	34	#include <mach/dma.h>
ad68bb9f	35	#include <mach/smemc.h>
1da177e4 LT	36
1da177e4 LT	37	#include "generic.h"
46c41e62	38	#include "devices.h"
a6dba20c	39	#include "clock.h"
1da177e4 LT	40
	41	/*
	42	* Various clock factors driven by the CCCR register.
	43	*/
	44
	45	/* Crystal Frequency to Memory Frequency Multiplier (L) */
	46	static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
	47
	48	/* Memory Frequency to Run Mode Frequency Multiplier (M) */
	49	static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
	50
	51	/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
	52	/* Note: we store the value N * 2 here. */
	53	static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
	54
	55	/* Crystal clock */
	56	#define BASE_CLK 3686400
	57
	58	/*
	59	* Get the clock frequency as reflected by CCCR and the turbo flag.
	60	* We assume these values have been applied via a fcs.
	61	* If info is not 0 we also display the current settings.
	62	*/
15a40333	63	unsigned int pxa25x_get_clk_frequency_khz(int info)
1da177e4 LT	64	{
	65	unsigned long cccr, turbo;
	66	unsigned int l, L, m, M, n2, N;
	67
	68	cccr = CCCR;
	69	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
	70
	71	l = L_clk_mult[(cccr >> 0) & 0x1f];
	72	m = M_clk_mult[(cccr >> 5) & 0x03];
	73	n2 = N2_clk_mult[(cccr >> 7) & 0x07];
	74
	75	L = l * BASE_CLK;
	76	M = m * L;
	77	N = n2 * M / 2;
	78
	79	if(info)
	80	{
	81	L += 5000;
	82	printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
	83	L / 1000000, (L % 1000000) / 10000, l );
	84	M += 5000;
	85	printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
	86	M / 1000000, (M % 1000000) / 10000, m );
	87	N += 5000;
	88	printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
	89	N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
	90	(turbo & 1) ? "" : "in" );
	91	}
	92
	93	return (turbo & 1) ? (N/1000) : (M/1000);
	94	}
	95
2a125dd5	96	static unsigned long clk_pxa25x_mem_getrate(struct clk *clk)
1da177e4	97	{
2a125dd5	98	return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK;
1da177e4 LT	99	}
1da177e4 LT	100
2a125dd5 EM	101	static const struct clkops clk_pxa25x_mem_ops = {
	102	.enable = clk_dummy_enable,
	103	.disable = clk_dummy_disable,
	104	.getrate = clk_pxa25x_mem_getrate,
	105	};
a6dba20c RK	106
a6dba20c RK	107	static const struct clkops clk_pxa25x_lcd_ops = {
4029813c EM	108	.enable = clk_pxa2xx_cken_enable,
4029813c EM	109	.disable = clk_pxa2xx_cken_disable,
2a125dd5	110	.getrate = clk_pxa25x_mem_getrate,
a6dba20c RK	111	};
a6dba20c RK	112
ed847782 IM	113	static unsigned long gpio12_config_32k[] = {
	114	GPIO12_32KHz,
	115	};
	116
	117	static unsigned long gpio12_config_gpio[] = {
	118	GPIO12_GPIO,
	119	};
	120
	121	static void clk_gpio12_enable(struct clk *clk)
	122	{
	123	pxa2xx_mfp_config(gpio12_config_32k, 1);
	124	}
	125
	126	static void clk_gpio12_disable(struct clk *clk)
	127	{
	128	pxa2xx_mfp_config(gpio12_config_gpio, 1);
	129	}
	130
	131	static const struct clkops clk_pxa25x_gpio12_ops = {
	132	.enable = clk_gpio12_enable,
	133	.disable = clk_gpio12_disable,
	134	};
	135
13f75582 IM	136	static unsigned long gpio11_config_3m6[] = {
	137	GPIO11_3_6MHz,
	138	};
	139
	140	static unsigned long gpio11_config_gpio[] = {
	141	GPIO11_GPIO,
	142	};
	143
	144	static void clk_gpio11_enable(struct clk *clk)
	145	{
	146	pxa2xx_mfp_config(gpio11_config_3m6, 1);
	147	}
	148
	149	static void clk_gpio11_disable(struct clk *clk)
	150	{
	151	pxa2xx_mfp_config(gpio11_config_gpio, 1);
	152	}
	153
	154	static const struct clkops clk_pxa25x_gpio11_ops = {
	155	.enable = clk_gpio11_enable,
	156	.disable = clk_gpio11_disable,
	157	};
	158
a6dba20c RK	159	/*
	160	* 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
	161	* 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
	162	* 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
	163	*/
e01dbdb4	164
bdb08cb2	165	/*
c1ed406c	166	* PXA 2xx clock declarations.
bdb08cb2	167	*/
4029813c EM	168	static DEFINE_PXA2_CKEN(pxa25x_hwuart, HWUART, 14745600, 1);
	169	static DEFINE_PXA2_CKEN(pxa25x_ffuart, FFUART, 14745600, 1);
	170	static DEFINE_PXA2_CKEN(pxa25x_btuart, BTUART, 14745600, 1);
	171	static DEFINE_PXA2_CKEN(pxa25x_stuart, STUART, 14745600, 1);
	172	static DEFINE_PXA2_CKEN(pxa25x_usb, USB, 47923000, 5);
	173	static DEFINE_PXA2_CKEN(pxa25x_mmc, MMC, 19169000, 0);
	174	static DEFINE_PXA2_CKEN(pxa25x_i2c, I2C, 31949000, 0);
	175	static DEFINE_PXA2_CKEN(pxa25x_ssp, SSP, 3686400, 0);
	176	static DEFINE_PXA2_CKEN(pxa25x_nssp, NSSP, 3686400, 0);
	177	static DEFINE_PXA2_CKEN(pxa25x_assp, ASSP, 3686400, 0);
	178	static DEFINE_PXA2_CKEN(pxa25x_pwm0, PWM0, 3686400, 0);
	179	static DEFINE_PXA2_CKEN(pxa25x_pwm1, PWM1, 3686400, 0);
	180	static DEFINE_PXA2_CKEN(pxa25x_ac97, AC97, 24576000, 0);
	181	static DEFINE_PXA2_CKEN(pxa25x_i2s, I2S, 14745600, 0);
	182	static DEFINE_PXA2_CKEN(pxa25x_ficp, FICP, 47923000, 0);
	183
8c3abc7d	184	static DEFINE_CK(pxa25x_lcd, LCD, &clk_pxa25x_lcd_ops);
8c3abc7d RK	185	static DEFINE_CLK(pxa25x_gpio11, &clk_pxa25x_gpio11_ops, 3686400, 0);
8c3abc7d RK	186	static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0);
2a125dd5	187	static DEFINE_CLK(pxa25x_mem, &clk_pxa25x_mem_ops, 0, 0);
8c3abc7d RK	188
	189	static struct clk_lookup pxa25x_clkregs[] = {
	190	INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL),
	191	INIT_CLKREG(&clk_pxa25x_ffuart, "pxa2xx-uart.0", NULL),
	192	INIT_CLKREG(&clk_pxa25x_btuart, "pxa2xx-uart.1", NULL),
	193	INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-uart.2", NULL),
	194	INIT_CLKREG(&clk_pxa25x_usb, "pxa25x-udc", NULL),
	195	INIT_CLKREG(&clk_pxa25x_mmc, "pxa2xx-mci.0", NULL),
	196	INIT_CLKREG(&clk_pxa25x_i2c, "pxa2xx-i2c.0", NULL),
	197	INIT_CLKREG(&clk_pxa25x_ssp, "pxa25x-ssp.0", NULL),
	198	INIT_CLKREG(&clk_pxa25x_nssp, "pxa25x-nssp.1", NULL),
	199	INIT_CLKREG(&clk_pxa25x_assp, "pxa25x-nssp.2", NULL),
	200	INIT_CLKREG(&clk_pxa25x_pwm0, "pxa25x-pwm.0", NULL),
	201	INIT_CLKREG(&clk_pxa25x_pwm1, "pxa25x-pwm.1", NULL),
	202	INIT_CLKREG(&clk_pxa25x_i2s, "pxa2xx-i2s", NULL),
	203	INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-ir", "UARTCLK"),
	204	INIT_CLKREG(&clk_pxa25x_ficp, "pxa2xx-ir", "FICPCLK"),
	205	INIT_CLKREG(&clk_pxa25x_ac97, NULL, "AC97CLK"),
	206	INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"),
	207	INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
2a125dd5	208	INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL),
a6dba20c RK	209	};
a6dba20c RK	210
4029813c EM	211	static struct clk_lookup pxa25x_hwuart_clkreg =
	212	INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL);
	213
a8fa3f0c	214	#ifdef CONFIG_PM
8775420d	215
711be5cc EM	216	#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
	217	#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
	218
711be5cc EM	219	/*
	220	* List of global PXA peripheral registers to preserve.
	221	* More ones like CP and general purpose register values are preserved
	222	* with the stack pointer in sleep.S.
	223	*/
5a3d9651	224	enum {
711be5cc	225	SLEEP_SAVE_PSTR,
649de51b	226	SLEEP_SAVE_COUNT
711be5cc EM	227	};
	228
	229
	230	static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
	231	{
711be5cc EM	232	SAVE(PSTR);
	233	}
	234
	235	static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
	236	{
711be5cc EM	237	RESTORE(PSTR);
	238	}
	239
	240	static void pxa25x_cpu_pm_enter(suspend_state_t state)
8775420d	241	{
dc38e2ad RK	242	/* Clear reset status */
	243	RCSR = RCSR_HWR \| RCSR_WDR \| RCSR_SMR \| RCSR_GPR;
	244
8775420d TP	245	switch (state) {
8775420d TP	246	case PM_SUSPEND_MEM:
4f5ad99b	247	pxa25x_cpu_suspend(PWRMODE_SLEEP, PLAT_PHYS_OFFSET - PAGE_OFFSET);
8775420d TP	248	break;
	249	}
	250	}
a8fa3f0c	251
4104980a RK	252	static int pxa25x_cpu_pm_prepare(void)
	253	{
	254	/* set resume return address */
4f5ad99b	255	PSPR = virt_to_phys(cpu_resume);
4104980a RK	256	return 0;
	257	}
	258
	259	static void pxa25x_cpu_pm_finish(void)
	260	{
	261	/* ensure not to come back here if it wasn't intended */
	262	PSPR = 0;
	263	}
	264
711be5cc	265	static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
649de51b	266	.save_count = SLEEP_SAVE_COUNT,
26398a70	267	.valid = suspend_valid_only_mem,
711be5cc EM	268	.save = pxa25x_cpu_pm_save,
	269	.restore = pxa25x_cpu_pm_restore,
	270	.enter = pxa25x_cpu_pm_enter,
4104980a RK	271	.prepare = pxa25x_cpu_pm_prepare,
4104980a RK	272	.finish = pxa25x_cpu_pm_finish,
e176bb05	273	};
711be5cc EM	274
	275	static void __init pxa25x_init_pm(void)
	276	{
	277	pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
	278	}
f79299ca	279	#else
f79299ca	280	static inline void pxa25x_init_pm(void) {}
a8fa3f0c	281	#endif
e176bb05	282
c95530c7	283	/* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
	284	*/
	285
a3f4c927	286	static int pxa25x_set_wake(struct irq_data *d, unsigned int on)
c95530c7	287	{
7db6a7fa	288	int gpio = irq_to_gpio(d->irq);
c0a596d6	289	uint32_t mask = 0;
	290
	291	if (gpio >= 0 && gpio < 85)
	292	return gpio_set_wake(gpio, on);
c95530c7	293
a3f4c927	294	if (d->irq == IRQ_RTCAlrm) {
c95530c7	295	mask = PWER_RTC;
	296	goto set_pwer;
	297	}
	298
	299	return -EINVAL;
	300
	301	set_pwer:
	302	if (on)
	303	PWER \|= mask;
	304	else
	305	PWER &=~mask;
	306
	307	return 0;
	308	}
	309
cd49104d EM	310	void __init pxa25x_init_irq(void)
cd49104d EM	311	{
b9e25ace	312	pxa_init_irq(32, pxa25x_set_wake);
a58fbcd8	313	pxa_init_gpio(IRQ_GPIO_2_x, 2, 84, pxa25x_set_wake);
cd49104d EM	314	}
cd49104d EM	315
067455aa EM	316	#ifdef CONFIG_CPU_PXA26x
	317	void __init pxa26x_init_irq(void)
	318	{
	319	pxa_init_irq(32, pxa25x_set_wake);
a58fbcd8	320	pxa_init_gpio(IRQ_GPIO_2_x, 2, 89, pxa25x_set_wake);
067455aa EM	321	}
	322	#endif
	323
851982c1 MV	324	static struct map_desc pxa25x_io_desc[] __initdata = {
851982c1 MV	325	{ /* Mem Ctl */
ad68bb9f MV	326	.virtual = SMEMC_VIRT,
ad68bb9f MV	327	.pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE),
851982c1 MV	328	.length = 0x00200000,
	329	.type = MT_DEVICE
	330	},
	331	};
	332
	333	void __init pxa25x_map_io(void)
	334	{
	335	pxa_map_io();
	336	iotable_init(ARRAY_AND_SIZE(pxa25x_io_desc));
	337	pxa25x_get_clk_frequency_khz(1);
	338	}
	339
34f3231f	340	static struct platform_device *pxa25x_devices[] __initdata = {
7a857620	341	&pxa25x_device_udc,
09a5358d	342	&pxa_device_pmu,
e09d02e1	343	&pxa_device_i2s,
72493146	344	&sa1100_device_rtc,
d8e0db11	345	&pxa25x_device_ssp,
	346	&pxa25x_device_nssp,
	347	&pxa25x_device_assp,
75540c1a	348	&pxa25x_device_pwm0,
75540c1a	349	&pxa25x_device_pwm1,
ea73e752	350	&pxa_device_asoc_platform,
34f3231f RK	351	};
34f3231f RK	352
e176bb05 RK	353	static int __init pxa25x_init(void)
e176bb05 RK	354	{
2eaa03b5	355	int ret = 0;
f53f066c	356
0ffcbfd5	357	if (cpu_is_pxa25x()) {
04fef228 EM	358
	359	reset_status = RCSR;
	360
0a0300dc	361	clkdev_add_table(pxa25x_clkregs, ARRAY_SIZE(pxa25x_clkregs));
a6dba20c	362
fef1f99a	363	if ((ret = pxa_init_dma(IRQ_DMA, 16)))
f53f066c	364	return ret;
f79299ca	365
711be5cc	366	pxa25x_init_pm();
f79299ca	367
2eaa03b5 RW	368	register_syscore_ops(&pxa_irq_syscore_ops);
	369	register_syscore_ops(&pxa2xx_mfp_syscore_ops);
	370	register_syscore_ops(&pxa_gpio_syscore_ops);
	371	register_syscore_ops(&pxa2xx_clock_syscore_ops);
c0165504	372
34f3231f RK	373	ret = platform_add_devices(pxa25x_devices,
34f3231f RK	374	ARRAY_SIZE(pxa25x_devices));
c0165504	375	if (ret)
c0165504	376	return ret;
e176bb05	377	}
c0165504	378
2b12797c	379	/* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */
cc155c6f	380	if (cpu_is_pxa255())
0a0300dc	381	clkdev_add(&pxa25x_hwuart_clkreg);
34f3231f RK	382
34f3231f RK	383	return ret;
e176bb05 RK	384	}
e176bb05 RK	385
1c104e0e	386	postcore_initcall(pxa25x_init);