Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-pxa/pxa25x.c | |
3 | * | |
4 | * Author: Nicolas Pitre | |
5 | * Created: Jun 15, 2001 | |
6 | * Copyright: MontaVista Software Inc. | |
7 | * | |
8 | * Code specific to PXA21x/25x/26x variants. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * Since this file should be linked before any other machine specific file, | |
15 | * the __initcall() here will be executed first. This serves as default | |
16 | * initialization stuff for PXA machines which can be overridden later if | |
17 | * need be. | |
18 | */ | |
19 | #include <linux/module.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/init.h> | |
34f3231f | 22 | #include <linux/platform_device.h> |
95d9ffbe | 23 | #include <linux/suspend.h> |
2eaa03b5 | 24 | #include <linux/syscore_ops.h> |
a3f4c927 | 25 | #include <linux/irq.h> |
1da177e4 | 26 | |
851982c1 | 27 | #include <asm/mach/map.h> |
2c74a0ce | 28 | #include <asm/suspend.h> |
a09e64fb RK |
29 | #include <mach/hardware.h> |
30 | #include <mach/irqs.h> | |
a58fbcd8 | 31 | #include <mach/gpio.h> |
51c62982 | 32 | #include <mach/pxa25x.h> |
afd2fc02 | 33 | #include <mach/reset.h> |
a09e64fb RK |
34 | #include <mach/pm.h> |
35 | #include <mach/dma.h> | |
ad68bb9f | 36 | #include <mach/smemc.h> |
1da177e4 LT |
37 | |
38 | #include "generic.h" | |
46c41e62 | 39 | #include "devices.h" |
a6dba20c | 40 | #include "clock.h" |
1da177e4 LT |
41 | |
42 | /* | |
43 | * Various clock factors driven by the CCCR register. | |
44 | */ | |
45 | ||
46 | /* Crystal Frequency to Memory Frequency Multiplier (L) */ | |
47 | static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, }; | |
48 | ||
49 | /* Memory Frequency to Run Mode Frequency Multiplier (M) */ | |
50 | static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 }; | |
51 | ||
52 | /* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */ | |
53 | /* Note: we store the value N * 2 here. */ | |
54 | static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 }; | |
55 | ||
56 | /* Crystal clock */ | |
57 | #define BASE_CLK 3686400 | |
58 | ||
59 | /* | |
60 | * Get the clock frequency as reflected by CCCR and the turbo flag. | |
61 | * We assume these values have been applied via a fcs. | |
62 | * If info is not 0 we also display the current settings. | |
63 | */ | |
15a40333 | 64 | unsigned int pxa25x_get_clk_frequency_khz(int info) |
1da177e4 LT |
65 | { |
66 | unsigned long cccr, turbo; | |
67 | unsigned int l, L, m, M, n2, N; | |
68 | ||
69 | cccr = CCCR; | |
70 | asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) ); | |
71 | ||
72 | l = L_clk_mult[(cccr >> 0) & 0x1f]; | |
73 | m = M_clk_mult[(cccr >> 5) & 0x03]; | |
74 | n2 = N2_clk_mult[(cccr >> 7) & 0x07]; | |
75 | ||
76 | L = l * BASE_CLK; | |
77 | M = m * L; | |
78 | N = n2 * M / 2; | |
79 | ||
80 | if(info) | |
81 | { | |
82 | L += 5000; | |
83 | printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n", | |
84 | L / 1000000, (L % 1000000) / 10000, l ); | |
85 | M += 5000; | |
86 | printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n", | |
87 | M / 1000000, (M % 1000000) / 10000, m ); | |
88 | N += 5000; | |
89 | printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n", | |
90 | N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5, | |
91 | (turbo & 1) ? "" : "in" ); | |
92 | } | |
93 | ||
94 | return (turbo & 1) ? (N/1000) : (M/1000); | |
95 | } | |
96 | ||
2a125dd5 | 97 | static unsigned long clk_pxa25x_mem_getrate(struct clk *clk) |
1da177e4 | 98 | { |
2a125dd5 | 99 | return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK; |
1da177e4 LT |
100 | } |
101 | ||
2a125dd5 EM |
102 | static const struct clkops clk_pxa25x_mem_ops = { |
103 | .enable = clk_dummy_enable, | |
104 | .disable = clk_dummy_disable, | |
105 | .getrate = clk_pxa25x_mem_getrate, | |
106 | }; | |
a6dba20c RK |
107 | |
108 | static const struct clkops clk_pxa25x_lcd_ops = { | |
4029813c EM |
109 | .enable = clk_pxa2xx_cken_enable, |
110 | .disable = clk_pxa2xx_cken_disable, | |
2a125dd5 | 111 | .getrate = clk_pxa25x_mem_getrate, |
a6dba20c RK |
112 | }; |
113 | ||
ed847782 IM |
114 | static unsigned long gpio12_config_32k[] = { |
115 | GPIO12_32KHz, | |
116 | }; | |
117 | ||
118 | static unsigned long gpio12_config_gpio[] = { | |
119 | GPIO12_GPIO, | |
120 | }; | |
121 | ||
122 | static void clk_gpio12_enable(struct clk *clk) | |
123 | { | |
124 | pxa2xx_mfp_config(gpio12_config_32k, 1); | |
125 | } | |
126 | ||
127 | static void clk_gpio12_disable(struct clk *clk) | |
128 | { | |
129 | pxa2xx_mfp_config(gpio12_config_gpio, 1); | |
130 | } | |
131 | ||
132 | static const struct clkops clk_pxa25x_gpio12_ops = { | |
133 | .enable = clk_gpio12_enable, | |
134 | .disable = clk_gpio12_disable, | |
135 | }; | |
136 | ||
13f75582 IM |
137 | static unsigned long gpio11_config_3m6[] = { |
138 | GPIO11_3_6MHz, | |
139 | }; | |
140 | ||
141 | static unsigned long gpio11_config_gpio[] = { | |
142 | GPIO11_GPIO, | |
143 | }; | |
144 | ||
145 | static void clk_gpio11_enable(struct clk *clk) | |
146 | { | |
147 | pxa2xx_mfp_config(gpio11_config_3m6, 1); | |
148 | } | |
149 | ||
150 | static void clk_gpio11_disable(struct clk *clk) | |
151 | { | |
152 | pxa2xx_mfp_config(gpio11_config_gpio, 1); | |
153 | } | |
154 | ||
155 | static const struct clkops clk_pxa25x_gpio11_ops = { | |
156 | .enable = clk_gpio11_enable, | |
157 | .disable = clk_gpio11_disable, | |
158 | }; | |
159 | ||
a6dba20c RK |
160 | /* |
161 | * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz) | |
162 | * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz | |
163 | * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly) | |
164 | */ | |
e01dbdb4 | 165 | |
bdb08cb2 | 166 | /* |
c1ed406c | 167 | * PXA 2xx clock declarations. |
bdb08cb2 | 168 | */ |
4029813c EM |
169 | static DEFINE_PXA2_CKEN(pxa25x_hwuart, HWUART, 14745600, 1); |
170 | static DEFINE_PXA2_CKEN(pxa25x_ffuart, FFUART, 14745600, 1); | |
171 | static DEFINE_PXA2_CKEN(pxa25x_btuart, BTUART, 14745600, 1); | |
172 | static DEFINE_PXA2_CKEN(pxa25x_stuart, STUART, 14745600, 1); | |
173 | static DEFINE_PXA2_CKEN(pxa25x_usb, USB, 47923000, 5); | |
174 | static DEFINE_PXA2_CKEN(pxa25x_mmc, MMC, 19169000, 0); | |
175 | static DEFINE_PXA2_CKEN(pxa25x_i2c, I2C, 31949000, 0); | |
176 | static DEFINE_PXA2_CKEN(pxa25x_ssp, SSP, 3686400, 0); | |
177 | static DEFINE_PXA2_CKEN(pxa25x_nssp, NSSP, 3686400, 0); | |
178 | static DEFINE_PXA2_CKEN(pxa25x_assp, ASSP, 3686400, 0); | |
179 | static DEFINE_PXA2_CKEN(pxa25x_pwm0, PWM0, 3686400, 0); | |
180 | static DEFINE_PXA2_CKEN(pxa25x_pwm1, PWM1, 3686400, 0); | |
181 | static DEFINE_PXA2_CKEN(pxa25x_ac97, AC97, 24576000, 0); | |
182 | static DEFINE_PXA2_CKEN(pxa25x_i2s, I2S, 14745600, 0); | |
183 | static DEFINE_PXA2_CKEN(pxa25x_ficp, FICP, 47923000, 0); | |
184 | ||
8c3abc7d | 185 | static DEFINE_CK(pxa25x_lcd, LCD, &clk_pxa25x_lcd_ops); |
8c3abc7d RK |
186 | static DEFINE_CLK(pxa25x_gpio11, &clk_pxa25x_gpio11_ops, 3686400, 0); |
187 | static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0); | |
2a125dd5 | 188 | static DEFINE_CLK(pxa25x_mem, &clk_pxa25x_mem_ops, 0, 0); |
8c3abc7d RK |
189 | |
190 | static struct clk_lookup pxa25x_clkregs[] = { | |
191 | INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL), | |
192 | INIT_CLKREG(&clk_pxa25x_ffuart, "pxa2xx-uart.0", NULL), | |
193 | INIT_CLKREG(&clk_pxa25x_btuart, "pxa2xx-uart.1", NULL), | |
194 | INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-uart.2", NULL), | |
195 | INIT_CLKREG(&clk_pxa25x_usb, "pxa25x-udc", NULL), | |
196 | INIT_CLKREG(&clk_pxa25x_mmc, "pxa2xx-mci.0", NULL), | |
197 | INIT_CLKREG(&clk_pxa25x_i2c, "pxa2xx-i2c.0", NULL), | |
198 | INIT_CLKREG(&clk_pxa25x_ssp, "pxa25x-ssp.0", NULL), | |
199 | INIT_CLKREG(&clk_pxa25x_nssp, "pxa25x-nssp.1", NULL), | |
200 | INIT_CLKREG(&clk_pxa25x_assp, "pxa25x-nssp.2", NULL), | |
201 | INIT_CLKREG(&clk_pxa25x_pwm0, "pxa25x-pwm.0", NULL), | |
202 | INIT_CLKREG(&clk_pxa25x_pwm1, "pxa25x-pwm.1", NULL), | |
203 | INIT_CLKREG(&clk_pxa25x_i2s, "pxa2xx-i2s", NULL), | |
204 | INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-ir", "UARTCLK"), | |
205 | INIT_CLKREG(&clk_pxa25x_ficp, "pxa2xx-ir", "FICPCLK"), | |
206 | INIT_CLKREG(&clk_pxa25x_ac97, NULL, "AC97CLK"), | |
207 | INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"), | |
208 | INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"), | |
2a125dd5 | 209 | INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL), |
a6dba20c RK |
210 | }; |
211 | ||
4029813c EM |
212 | static struct clk_lookup pxa25x_hwuart_clkreg = |
213 | INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL); | |
214 | ||
a8fa3f0c | 215 | #ifdef CONFIG_PM |
8775420d | 216 | |
711be5cc EM |
217 | #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x |
218 | #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] | |
219 | ||
711be5cc EM |
220 | /* |
221 | * List of global PXA peripheral registers to preserve. | |
222 | * More ones like CP and general purpose register values are preserved | |
223 | * with the stack pointer in sleep.S. | |
224 | */ | |
5a3d9651 | 225 | enum { |
711be5cc | 226 | SLEEP_SAVE_PSTR, |
649de51b | 227 | SLEEP_SAVE_COUNT |
711be5cc EM |
228 | }; |
229 | ||
230 | ||
231 | static void pxa25x_cpu_pm_save(unsigned long *sleep_save) | |
232 | { | |
711be5cc EM |
233 | SAVE(PSTR); |
234 | } | |
235 | ||
236 | static void pxa25x_cpu_pm_restore(unsigned long *sleep_save) | |
237 | { | |
711be5cc EM |
238 | RESTORE(PSTR); |
239 | } | |
240 | ||
241 | static void pxa25x_cpu_pm_enter(suspend_state_t state) | |
8775420d | 242 | { |
dc38e2ad RK |
243 | /* Clear reset status */ |
244 | RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR; | |
245 | ||
8775420d TP |
246 | switch (state) { |
247 | case PM_SUSPEND_MEM: | |
2c74a0ce | 248 | cpu_suspend(PWRMODE_SLEEP, pxa25x_finish_suspend); |
8775420d TP |
249 | break; |
250 | } | |
251 | } | |
a8fa3f0c | 252 | |
4104980a RK |
253 | static int pxa25x_cpu_pm_prepare(void) |
254 | { | |
255 | /* set resume return address */ | |
4f5ad99b | 256 | PSPR = virt_to_phys(cpu_resume); |
4104980a RK |
257 | return 0; |
258 | } | |
259 | ||
260 | static void pxa25x_cpu_pm_finish(void) | |
261 | { | |
262 | /* ensure not to come back here if it wasn't intended */ | |
263 | PSPR = 0; | |
264 | } | |
265 | ||
711be5cc | 266 | static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = { |
649de51b | 267 | .save_count = SLEEP_SAVE_COUNT, |
26398a70 | 268 | .valid = suspend_valid_only_mem, |
711be5cc EM |
269 | .save = pxa25x_cpu_pm_save, |
270 | .restore = pxa25x_cpu_pm_restore, | |
271 | .enter = pxa25x_cpu_pm_enter, | |
4104980a RK |
272 | .prepare = pxa25x_cpu_pm_prepare, |
273 | .finish = pxa25x_cpu_pm_finish, | |
e176bb05 | 274 | }; |
711be5cc EM |
275 | |
276 | static void __init pxa25x_init_pm(void) | |
277 | { | |
278 | pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns; | |
279 | } | |
f79299ca | 280 | #else |
281 | static inline void pxa25x_init_pm(void) {} | |
a8fa3f0c | 282 | #endif |
e176bb05 | 283 | |
c95530c7 | 284 | /* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm |
285 | */ | |
286 | ||
a3f4c927 | 287 | static int pxa25x_set_wake(struct irq_data *d, unsigned int on) |
c95530c7 | 288 | { |
7db6a7fa | 289 | int gpio = irq_to_gpio(d->irq); |
c0a596d6 | 290 | uint32_t mask = 0; |
291 | ||
292 | if (gpio >= 0 && gpio < 85) | |
293 | return gpio_set_wake(gpio, on); | |
c95530c7 | 294 | |
a3f4c927 | 295 | if (d->irq == IRQ_RTCAlrm) { |
c95530c7 | 296 | mask = PWER_RTC; |
297 | goto set_pwer; | |
298 | } | |
299 | ||
300 | return -EINVAL; | |
301 | ||
302 | set_pwer: | |
303 | if (on) | |
304 | PWER |= mask; | |
305 | else | |
306 | PWER &=~mask; | |
307 | ||
308 | return 0; | |
309 | } | |
310 | ||
cd49104d EM |
311 | void __init pxa25x_init_irq(void) |
312 | { | |
b9e25ace | 313 | pxa_init_irq(32, pxa25x_set_wake); |
a58fbcd8 | 314 | pxa_init_gpio(IRQ_GPIO_2_x, 2, 84, pxa25x_set_wake); |
cd49104d EM |
315 | } |
316 | ||
067455aa EM |
317 | #ifdef CONFIG_CPU_PXA26x |
318 | void __init pxa26x_init_irq(void) | |
319 | { | |
320 | pxa_init_irq(32, pxa25x_set_wake); | |
a58fbcd8 | 321 | pxa_init_gpio(IRQ_GPIO_2_x, 2, 89, pxa25x_set_wake); |
067455aa EM |
322 | } |
323 | #endif | |
324 | ||
851982c1 MV |
325 | static struct map_desc pxa25x_io_desc[] __initdata = { |
326 | { /* Mem Ctl */ | |
ad68bb9f MV |
327 | .virtual = SMEMC_VIRT, |
328 | .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE), | |
851982c1 MV |
329 | .length = 0x00200000, |
330 | .type = MT_DEVICE | |
331 | }, | |
332 | }; | |
333 | ||
334 | void __init pxa25x_map_io(void) | |
335 | { | |
336 | pxa_map_io(); | |
337 | iotable_init(ARRAY_AND_SIZE(pxa25x_io_desc)); | |
338 | pxa25x_get_clk_frequency_khz(1); | |
339 | } | |
340 | ||
34f3231f | 341 | static struct platform_device *pxa25x_devices[] __initdata = { |
7a857620 | 342 | &pxa25x_device_udc, |
09a5358d | 343 | &pxa_device_pmu, |
e09d02e1 | 344 | &pxa_device_i2s, |
72493146 | 345 | &sa1100_device_rtc, |
d8e0db11 | 346 | &pxa25x_device_ssp, |
347 | &pxa25x_device_nssp, | |
348 | &pxa25x_device_assp, | |
75540c1a | 349 | &pxa25x_device_pwm0, |
350 | &pxa25x_device_pwm1, | |
ea73e752 | 351 | &pxa_device_asoc_platform, |
34f3231f RK |
352 | }; |
353 | ||
e176bb05 RK |
354 | static int __init pxa25x_init(void) |
355 | { | |
2eaa03b5 | 356 | int ret = 0; |
f53f066c | 357 | |
0ffcbfd5 | 358 | if (cpu_is_pxa25x()) { |
04fef228 EM |
359 | |
360 | reset_status = RCSR; | |
361 | ||
0a0300dc | 362 | clkdev_add_table(pxa25x_clkregs, ARRAY_SIZE(pxa25x_clkregs)); |
a6dba20c | 363 | |
fef1f99a | 364 | if ((ret = pxa_init_dma(IRQ_DMA, 16))) |
f53f066c | 365 | return ret; |
f79299ca | 366 | |
711be5cc | 367 | pxa25x_init_pm(); |
f79299ca | 368 | |
2eaa03b5 RW |
369 | register_syscore_ops(&pxa_irq_syscore_ops); |
370 | register_syscore_ops(&pxa2xx_mfp_syscore_ops); | |
371 | register_syscore_ops(&pxa_gpio_syscore_ops); | |
372 | register_syscore_ops(&pxa2xx_clock_syscore_ops); | |
c0165504 | 373 | |
34f3231f RK |
374 | ret = platform_add_devices(pxa25x_devices, |
375 | ARRAY_SIZE(pxa25x_devices)); | |
c0165504 | 376 | if (ret) |
377 | return ret; | |
e176bb05 | 378 | } |
c0165504 | 379 | |
2b12797c | 380 | /* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */ |
cc155c6f | 381 | if (cpu_is_pxa255()) |
0a0300dc | 382 | clkdev_add(&pxa25x_hwuart_clkreg); |
34f3231f RK |
383 | |
384 | return ret; | |
e176bb05 RK |
385 | } |
386 | ||
1c104e0e | 387 | postcore_initcall(pxa25x_init); |