[deliverable/linux.git] / arch / arm / mach-pxa / pxa27x.c

/*
 *  linux/arch/arm/mach-pxa/pxa27x.c
 *
 *  Author:	Nicolas Pitre
 *  Created:	Nov 05, 2002
 *  Copyright:	MontaVista Software Inc.
 *
 * Code specific to PXA27x aka Bulverde.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/gpio.h>
#include <linux/gpio-pxa.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/suspend.h>
#include <linux/platform_device.h>
#include <linux/syscore_ops.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/i2c/pxa-i2c.h>

#include <asm/mach/map.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/suspend.h>
#include <mach/irqs.h>
#include <mach/pxa27x.h>
#include <mach/reset.h>
#include <linux/platform_data/usb-ohci-pxa27x.h>
#include <mach/pm.h>
#include <mach/dma.h>
#include <mach/smemc.h>

#include "generic.h"
#include "devices.h"
#include "clock.h"

void pxa27x_clear_otgph(void)
{
	if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
		PSSR |= PSSR_OTGPH;
}
EXPORT_SYMBOL(pxa27x_clear_otgph);

static unsigned long ac97_reset_config[] = {
	GPIO113_AC97_nRESET_GPIO_HIGH,
	GPIO113_AC97_nRESET,
	GPIO95_AC97_nRESET_GPIO_HIGH,
	GPIO95_AC97_nRESET,
};

void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio)
{
	/*
	 * This helper function is used to work around a bug in the pxa27x's
	 * ac97 controller during a warm reset.  The configuration of the
	 * reset_gpio is changed as follows:
	 * to_gpio == true: configured to generic output gpio and driven high
	 * to_gpio == false: configured to ac97 controller alt fn AC97_nRESET
	 */

	if (reset_gpio == 113)
		pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[0] :
				  &ac97_reset_config[1], 1);

	if (reset_gpio == 95)
		pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[2] :
				  &ac97_reset_config[3], 1);
}
EXPORT_SYMBOL_GPL(pxa27x_configure_ac97reset);

/* Crystal clock: 13MHz */
#define BASE_CLK	13000000

/*
 * Get the clock frequency as reflected by CCSR and the turbo flag.
 * We assume these values have been applied via a fcs.
 * If info is not 0 we also display the current settings.
 */
unsigned int pxa27x_get_clk_frequency_khz(int info)
{
	unsigned long ccsr, clkcfg;
	unsigned int l, L, m, M, n2, N, S;
       	int cccr_a, t, ht, b;

	ccsr = CCSR;
	cccr_a = CCCR & (1 << 25);

	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	t  = clkcfg & (1 << 0);
	ht = clkcfg & (1 << 2);
	b  = clkcfg & (1 << 3);

	l  = ccsr & 0x1f;
	n2 = (ccsr>>7) & 0xf;
	m  = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;

	L  = l * BASE_CLK;
	N  = (L * n2) / 2;
	M  = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	S  = (b) ? L : (L/2);

	if (info) {
		printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
			L / 1000000, (L % 1000000) / 10000, l );
		printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
			N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
			(t) ? "" : "in" );
		printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
			M / 1000000, (M % 1000000) / 10000, m );
		printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
			S / 1000000, (S % 1000000) / 10000 );
	}

	return (t) ? (N/1000) : (L/1000);
}

/*
 * Return the current mem clock frequency as reflected by CCCR[A], B, and L
 */
static unsigned long clk_pxa27x_mem_getrate(struct clk *clk)
{
	unsigned long ccsr, clkcfg;
	unsigned int l, L, m, M;
       	int cccr_a, b;

	ccsr = CCSR;
	cccr_a = CCCR & (1 << 25);

	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	b = clkcfg & (1 << 3);

	l = ccsr & 0x1f;
	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;

	L = l * BASE_CLK;
	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));

	return M;
}

static const struct clkops clk_pxa27x_mem_ops = {
	.enable		= clk_dummy_enable,
	.disable	= clk_dummy_disable,
	.getrate	= clk_pxa27x_mem_getrate,
};

/*
 * Return the current LCD clock frequency in units of 10kHz as
 */
static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
{
	unsigned long ccsr;
	unsigned int l, L, k, K;

	ccsr = CCSR;

	l = ccsr & 0x1f;
	k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;

	L = l * BASE_CLK;
	K = L / k;

	return (K / 10000);
}

static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
{
	return pxa27x_get_lcdclk_frequency_10khz() * 10000;
}

static const struct clkops clk_pxa27x_lcd_ops = {
	.enable		= clk_pxa2xx_cken_enable,
	.disable	= clk_pxa2xx_cken_disable,
	.getrate	= clk_pxa27x_lcd_getrate,
};

static DEFINE_PXA2_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
static DEFINE_PXA2_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
static DEFINE_PXA2_CKEN(pxa27x_stuart, STUART, 14857000, 1);
static DEFINE_PXA2_CKEN(pxa27x_i2s, I2S, 14682000, 0);
static DEFINE_PXA2_CKEN(pxa27x_i2c, I2C, 32842000, 0);
static DEFINE_PXA2_CKEN(pxa27x_usb, USB, 48000000, 5);
static DEFINE_PXA2_CKEN(pxa27x_mmc, MMC, 19500000, 0);
static DEFINE_PXA2_CKEN(pxa27x_ficp, FICP, 48000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
static DEFINE_PXA2_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_ac97, AC97, 24576000, 0);
static DEFINE_PXA2_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
static DEFINE_PXA2_CKEN(pxa27x_msl, MSL, 48000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_usim, USIM, 48000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
static DEFINE_PXA2_CKEN(pxa27x_im, IM, 0, 0);
static DEFINE_PXA2_CKEN(pxa27x_memc, MEMC, 0, 0);

static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
static DEFINE_CLK(pxa27x_mem, &clk_pxa27x_mem_ops, 0, 0);

static struct clk_lookup pxa27x_clkregs[] = {
	INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
	INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL),
	INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL),
	INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL),
	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL),
	INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL),
	INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL),
	INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL),
	INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL),
	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"),
	INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"),
	INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL),
	INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL),
	INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL),
	INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL),
	INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL),
	INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL),
	INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL),
	INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL),
	INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"),
	INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"),
	INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"),
	INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"),
	INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
	INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
	INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
	INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
	INIT_CLKREG(&clk_dummy, "pxa27x-gpio", NULL),
	INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
};

#ifdef CONFIG_PM

#define SAVE(x)		sleep_save[SLEEP_SAVE_##x] = x
#define RESTORE(x)	x = sleep_save[SLEEP_SAVE_##x]

/*
 * allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM
 */
static unsigned int pwrmode = PWRMODE_SLEEP;

int __init pxa27x_set_pwrmode(unsigned int mode)
{
	switch (mode) {
	case PWRMODE_SLEEP:
	case PWRMODE_DEEPSLEEP:
		pwrmode = mode;
		return 0;
	}

	return -EINVAL;
}

/*
 * List of global PXA peripheral registers to preserve.
 * More ones like CP and general purpose register values are preserved
 * with the stack pointer in sleep.S.
 */
enum {
	SLEEP_SAVE_PSTR,
	SLEEP_SAVE_MDREFR,
	SLEEP_SAVE_PCFR,
	SLEEP_SAVE_COUNT
};

void pxa27x_cpu_pm_save(unsigned long *sleep_save)
{
	sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR);
	SAVE(PCFR);

	SAVE(PSTR);
}

void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
{
	__raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR);
	RESTORE(PCFR);

	PSSR = PSSR_RDH | PSSR_PH;

	RESTORE(PSTR);
}

void pxa27x_cpu_pm_enter(suspend_state_t state)
{
	extern void pxa_cpu_standby(void);
#ifndef CONFIG_IWMMXT
	u64 acc0;

	asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0));
#endif

	/* ensure voltage-change sequencer not initiated, which hangs */
	PCFR &= ~PCFR_FVC;

	/* Clear edge-detect status register. */
	PEDR = 0xDF12FE1B;

	/* Clear reset status */
	RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;

	switch (state) {
	case PM_SUSPEND_STANDBY:
		pxa_cpu_standby();
		break;
	case PM_SUSPEND_MEM:
		cpu_suspend(pwrmode, pxa27x_finish_suspend);
#ifndef CONFIG_IWMMXT
		asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0));
#endif
		break;
	}
}

static int pxa27x_cpu_pm_valid(suspend_state_t state)
{
	return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
}

static int pxa27x_cpu_pm_prepare(void)
{
	/* set resume return address */
	PSPR = virt_to_phys(cpu_resume);
	return 0;
}

static void pxa27x_cpu_pm_finish(void)
{
	/* ensure not to come back here if it wasn't intended */
	PSPR = 0;
}

static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
	.save_count	= SLEEP_SAVE_COUNT,
	.save		= pxa27x_cpu_pm_save,
	.restore	= pxa27x_cpu_pm_restore,
	.valid		= pxa27x_cpu_pm_valid,
	.enter		= pxa27x_cpu_pm_enter,
	.prepare	= pxa27x_cpu_pm_prepare,
	.finish		= pxa27x_cpu_pm_finish,
};

static void __init pxa27x_init_pm(void)
{
	pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
}
#else
static inline void pxa27x_init_pm(void) {}
#endif

/* PXA27x:  Various gpios can issue wakeup events.  This logic only
 * handles the simple cases, not the WEMUX2 and WEMUX3 options
 */
static int pxa27x_set_wake(struct irq_data *d, unsigned int on)
{
	int gpio = pxa_irq_to_gpio(d->irq);
	uint32_t mask;

	if (gpio >= 0 && gpio < 128)
		return gpio_set_wake(gpio, on);

	if (d->irq == IRQ_KEYPAD)
		return keypad_set_wake(on);

	switch (d->irq) {
	case IRQ_RTCAlrm:
		mask = PWER_RTC;
		break;
	case IRQ_USB:
		mask = 1u << 26;
		break;
	default:
		return -EINVAL;
	}

	if (on)
		PWER |= mask;
	else
		PWER &=~mask;

	return 0;
}

void __init pxa27x_init_irq(void)
{
	pxa_init_irq(34, pxa27x_set_wake);
}

static struct map_desc pxa27x_io_desc[] __initdata = {
	{	/* Mem Ctl */
		.virtual	= (unsigned long)SMEMC_VIRT,
		.pfn		= __phys_to_pfn(PXA2XX_SMEMC_BASE),
		.length		= 0x00200000,
		.type		= MT_DEVICE
	}, {	/* IMem ctl */
		.virtual	=  0xfe000000,
		.pfn		= __phys_to_pfn(0x58000000),
		.length		= 0x00100000,
		.type		= MT_DEVICE
	},
};

void __init pxa27x_map_io(void)
{
	pxa_map_io();
	iotable_init(ARRAY_AND_SIZE(pxa27x_io_desc));
	pxa27x_get_clk_frequency_khz(1);
}

/*
 * device registration specific to PXA27x.
 */
void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
{
	local_irq_disable();
	PCFR |= PCFR_PI2CEN;
	local_irq_enable();
	pxa_register_device(&pxa27x_device_i2c_power, info);
}

static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = {
	.irq_base	= PXA_GPIO_TO_IRQ(0),
	.gpio_set_wake	= gpio_set_wake,
};

static struct platform_device *devices[] __initdata = {
	&pxa27x_device_udc,
	&pxa_device_pmu,
	&pxa_device_i2s,
	&pxa_device_asoc_ssp1,
	&pxa_device_asoc_ssp2,
	&pxa_device_asoc_ssp3,
	&pxa_device_asoc_platform,
	&sa1100_device_rtc,
	&pxa_device_rtc,
	&pxa27x_device_ssp1,
	&pxa27x_device_ssp2,
	&pxa27x_device_ssp3,
	&pxa27x_device_pwm0,
	&pxa27x_device_pwm1,
};

static int __init pxa27x_init(void)
{
	int ret = 0;

	if (cpu_is_pxa27x()) {

		reset_status = RCSR;

		clkdev_add_table(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));

		if ((ret = pxa_init_dma(IRQ_DMA, 32)))
			return ret;

		pxa27x_init_pm();

		register_syscore_ops(&pxa_irq_syscore_ops);
		register_syscore_ops(&pxa2xx_mfp_syscore_ops);
		register_syscore_ops(&pxa2xx_clock_syscore_ops);

		pxa_register_device(&pxa27x_device_gpio, &pxa27x_gpio_info);
		ret = platform_add_devices(devices, ARRAY_SIZE(devices));
	}

	return ret;
}

postcore_initcall(pxa27x_init);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-pxa/pxa27x.c
	3	*
	4	* Author: Nicolas Pitre
	5	* Created: Nov 05, 2002
	6	* Copyright: MontaVista Software Inc.
	7	*
	8	* Code specific to PXA27x aka Bulverde.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
2f8163ba	14	#include <linux/gpio.h>
157d2644	15	#include <linux/gpio-pxa.h>
1da177e4 LT	16	#include <linux/module.h>
	17	#include <linux/kernel.h>
	18	#include <linux/init.h>
95d9ffbe	19	#include <linux/suspend.h>
d052d1be	20	#include <linux/platform_device.h>
2eaa03b5	21	#include <linux/syscore_ops.h>
ad68bb9f	22	#include <linux/io.h>
a3f4c927	23	#include <linux/irq.h>
b459396e	24	#include <linux/i2c/pxa-i2c.h>
1da177e4	25
851982c1	26	#include <asm/mach/map.h>
a09e64fb	27	#include <mach/hardware.h>
1da177e4	28	#include <asm/irq.h>
2c74a0ce	29	#include <asm/suspend.h>
a09e64fb	30	#include <mach/irqs.h>
51c62982	31	#include <mach/pxa27x.h>
afd2fc02	32	#include <mach/reset.h>
293b2da1	33	#include <linux/platform_data/usb-ohci-pxa27x.h>
a09e64fb RK	34	#include <mach/pm.h>
a09e64fb RK	35	#include <mach/dma.h>
ad68bb9f MV	36	#include <mach/smemc.h>
ad68bb9f MV	37
1da177e4	38	#include "generic.h"
46c41e62	39	#include "devices.h"
a6dba20c	40	#include "clock.h"
1da177e4	41
0cb0b0d3 EM	42	void pxa27x_clear_otgph(void)
	43	{
	44	if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
	45	PSSR \|= PSSR_OTGPH;
	46	}
	47	EXPORT_SYMBOL(pxa27x_clear_otgph);
	48
fb1bf8cd	49	static unsigned long ac97_reset_config[] = {
3b4bc7bc	50	GPIO113_AC97_nRESET_GPIO_HIGH,
5e16e3cb	51	GPIO113_AC97_nRESET,
3b4bc7bc	52	GPIO95_AC97_nRESET_GPIO_HIGH,
5e16e3cb	53	GPIO95_AC97_nRESET,
fb1bf8cd EM	54	};
fb1bf8cd EM	55
053fe0f1	56	void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio)
fb1bf8cd	57	{
053fe0f1 MD	58	/*
	59	* This helper function is used to work around a bug in the pxa27x's
	60	* ac97 controller during a warm reset. The configuration of the
	61	* reset_gpio is changed as follows:
	62	* to_gpio == true: configured to generic output gpio and driven high
	63	* to_gpio == false: configured to ac97 controller alt fn AC97_nRESET
	64	*/
	65
fb1bf8cd	66	if (reset_gpio == 113)
053fe0f1 MD	67	pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[0] :
053fe0f1 MD	68	&ac97_reset_config[1], 1);
fb1bf8cd EM	69
fb1bf8cd EM	70	if (reset_gpio == 95)
053fe0f1 MD	71	pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[2] :
053fe0f1 MD	72	&ac97_reset_config[3], 1);
fb1bf8cd	73	}
053fe0f1	74	EXPORT_SYMBOL_GPL(pxa27x_configure_ac97reset);
fb1bf8cd	75
1da177e4 LT	76	/* Crystal clock: 13MHz */
	77	#define BASE_CLK 13000000
	78
	79	/*
	80	* Get the clock frequency as reflected by CCSR and the turbo flag.
	81	* We assume these values have been applied via a fcs.
	82	* If info is not 0 we also display the current settings.
	83	*/
15a40333	84	unsigned int pxa27x_get_clk_frequency_khz(int info)
1da177e4 LT	85	{
	86	unsigned long ccsr, clkcfg;
	87	unsigned int l, L, m, M, n2, N, S;
	88	int cccr_a, t, ht, b;
	89
	90	ccsr = CCSR;
	91	cccr_a = CCCR & (1 << 25);
	92
	93	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	94	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
afe5df20	95	t = clkcfg & (1 << 0);
1da177e4 LT	96	ht = clkcfg & (1 << 2);
	97	b = clkcfg & (1 << 3);
	98
	99	l = ccsr & 0x1f;
	100	n2 = (ccsr>>7) & 0xf;
	101	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
	102
	103	L = l * BASE_CLK;
	104	N = (L * n2) / 2;
	105	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	106	S = (b) ? L : (L/2);
	107
	108	if (info) {
	109	printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
	110	L / 1000000, (L % 1000000) / 10000, l );
	111	printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
	112	N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
	113	(t) ? "" : "in" );
	114	printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
	115	M / 1000000, (M % 1000000) / 10000, m );
	116	printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
	117	S / 1000000, (S % 1000000) / 10000 );
	118	}
	119
	120	return (t) ? (N/1000) : (L/1000);
	121	}
	122
	123	/*
2a125dd5	124	* Return the current mem clock frequency as reflected by CCCR[A], B, and L
1da177e4	125	*/
2a125dd5	126	static unsigned long clk_pxa27x_mem_getrate(struct clk *clk)
1da177e4 LT	127	{
	128	unsigned long ccsr, clkcfg;
	129	unsigned int l, L, m, M;
	130	int cccr_a, b;
	131
	132	ccsr = CCSR;
	133	cccr_a = CCCR & (1 << 25);
	134
	135	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	136	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	137	b = clkcfg & (1 << 3);
	138
	139	l = ccsr & 0x1f;
	140	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
	141
	142	L = l * BASE_CLK;
	143	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	144
2a125dd5	145	return M;
1da177e4 LT	146	}
1da177e4 LT	147
2a125dd5 EM	148	static const struct clkops clk_pxa27x_mem_ops = {
	149	.enable = clk_dummy_enable,
	150	.disable = clk_dummy_disable,
	151	.getrate = clk_pxa27x_mem_getrate,
	152	};
	153
1da177e4 LT	154	/*
	155	* Return the current LCD clock frequency in units of 10kHz as
	156	*/
a88a447d	157	static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
1da177e4 LT	158	{
	159	unsigned long ccsr;
	160	unsigned int l, L, k, K;
	161
	162	ccsr = CCSR;
	163
	164	l = ccsr & 0x1f;
	165	k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
	166
	167	L = l * BASE_CLK;
	168	K = L / k;
	169
	170	return (K / 10000);
	171	}
	172
a6dba20c RK	173	static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
	174	{
	175	return pxa27x_get_lcdclk_frequency_10khz() * 10000;
	176	}
	177
	178	static const struct clkops clk_pxa27x_lcd_ops = {
4029813c EM	179	.enable = clk_pxa2xx_cken_enable,
4029813c EM	180	.disable = clk_pxa2xx_cken_disable,
a6dba20c RK	181	.getrate = clk_pxa27x_lcd_getrate,
	182	};
	183
4029813c EM	184	static DEFINE_PXA2_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
	185	static DEFINE_PXA2_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
	186	static DEFINE_PXA2_CKEN(pxa27x_stuart, STUART, 14857000, 1);
	187	static DEFINE_PXA2_CKEN(pxa27x_i2s, I2S, 14682000, 0);
	188	static DEFINE_PXA2_CKEN(pxa27x_i2c, I2C, 32842000, 0);
	189	static DEFINE_PXA2_CKEN(pxa27x_usb, USB, 48000000, 5);
	190	static DEFINE_PXA2_CKEN(pxa27x_mmc, MMC, 19500000, 0);
	191	static DEFINE_PXA2_CKEN(pxa27x_ficp, FICP, 48000000, 0);
	192	static DEFINE_PXA2_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
	193	static DEFINE_PXA2_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
	194	static DEFINE_PXA2_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
	195	static DEFINE_PXA2_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
	196	static DEFINE_PXA2_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
	197	static DEFINE_PXA2_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
	198	static DEFINE_PXA2_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
	199	static DEFINE_PXA2_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
	200	static DEFINE_PXA2_CKEN(pxa27x_ac97, AC97, 24576000, 0);
	201	static DEFINE_PXA2_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
	202	static DEFINE_PXA2_CKEN(pxa27x_msl, MSL, 48000000, 0);
	203	static DEFINE_PXA2_CKEN(pxa27x_usim, USIM, 48000000, 0);
	204	static DEFINE_PXA2_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
	205	static DEFINE_PXA2_CKEN(pxa27x_im, IM, 0, 0);
	206	static DEFINE_PXA2_CKEN(pxa27x_memc, MEMC, 0, 0);
	207
8c3abc7d RK	208	static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
8c3abc7d RK	209	static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
2a125dd5	210	static DEFINE_CLK(pxa27x_mem, &clk_pxa27x_mem_ops, 0, 0);
8c3abc7d RK	211
	212	static struct clk_lookup pxa27x_clkregs[] = {
	213	INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
	214	INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL),
	215	INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL),
	216	INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL),
	217	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL),
	218	INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL),
	219	INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL),
	220	INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL),
	221	INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL),
	222	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"),
	223	INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"),
	224	INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL),
	225	INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL),
	226	INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL),
	227	INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL),
	228	INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL),
	229	INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL),
	230	INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL),
	231	INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL),
	232	INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"),
	233	INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"),
	234	INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"),
	235	INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"),
	236	INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
	237	INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
	238	INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
2a125dd5	239	INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
2cab0292	240	INIT_CLKREG(&clk_dummy, "pxa27x-gpio", NULL),
495b21dc	241	INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
a6dba20c RK	242	};
a6dba20c RK	243
a8fa3f0c NP	244	#ifdef CONFIG_PM
a8fa3f0c NP	245
711be5cc EM	246	#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
	247	#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
	248
d082d36e MR	249	/*
	250	* allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM
	251	*/
	252	static unsigned int pwrmode = PWRMODE_SLEEP;
	253
	254	int __init pxa27x_set_pwrmode(unsigned int mode)
	255	{
	256	switch (mode) {
	257	case PWRMODE_SLEEP:
	258	case PWRMODE_DEEPSLEEP:
	259	pwrmode = mode;
	260	return 0;
	261	}
	262
	263	return -EINVAL;
	264	}
	265
711be5cc EM	266	/*
	267	* List of global PXA peripheral registers to preserve.
	268	* More ones like CP and general purpose register values are preserved
	269	* with the stack pointer in sleep.S.
	270	*/
5a3d9651	271	enum {
711be5cc	272	SLEEP_SAVE_PSTR,
711be5cc	273	SLEEP_SAVE_MDREFR,
5a3d9651	274	SLEEP_SAVE_PCFR,
649de51b	275	SLEEP_SAVE_COUNT
711be5cc EM	276	};
	277
	278	void pxa27x_cpu_pm_save(unsigned long *sleep_save)
	279	{
ad68bb9f	280	sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR);
5a3d9651	281	SAVE(PCFR);
711be5cc	282
711be5cc	283	SAVE(PSTR);
711be5cc EM	284	}
	285
	286	void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
	287	{
ad68bb9f	288	__raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR);
5a3d9651	289	RESTORE(PCFR);
711be5cc EM	290
	291	PSSR = PSSR_RDH \| PSSR_PH;
	292
711be5cc EM	293	RESTORE(PSTR);
	294	}
	295
	296	void pxa27x_cpu_pm_enter(suspend_state_t state)
8775420d TP	297	{
8775420d TP	298	extern void pxa_cpu_standby(void);
a9503d21 RK	299	#ifndef CONFIG_IWMMXT
	300	u64 acc0;
	301
	302	asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0));
	303	#endif
8775420d	304
8775420d TP	305	/* ensure voltage-change sequencer not initiated, which hangs */
	306	PCFR &= ~PCFR_FVC;
	307
	308	/* Clear edge-detect status register. */
	309	PEDR = 0xDF12FE1B;
	310
dc38e2ad RK	311	/* Clear reset status */
	312	RCSR = RCSR_HWR \| RCSR_WDR \| RCSR_SMR \| RCSR_GPR;
	313
8775420d	314	switch (state) {
26705ca4 TP	315	case PM_SUSPEND_STANDBY:
	316	pxa_cpu_standby();
	317	break;
8775420d	318	case PM_SUSPEND_MEM:
2c74a0ce	319	cpu_suspend(pwrmode, pxa27x_finish_suspend);
a9503d21 RK	320	#ifndef CONFIG_IWMMXT
	321	asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0));
	322	#endif
8775420d TP	323	break;
	324	}
	325	}
1da177e4	326
711be5cc	327	static int pxa27x_cpu_pm_valid(suspend_state_t state)
88dfe98c RK	328	{
	329	return state == PM_SUSPEND_MEM \|\| state == PM_SUSPEND_STANDBY;
	330	}
	331
4104980a RK	332	static int pxa27x_cpu_pm_prepare(void)
	333	{
	334	/* set resume return address */
4f5ad99b	335	PSPR = virt_to_phys(cpu_resume);
4104980a RK	336	return 0;
	337	}
	338
	339	static void pxa27x_cpu_pm_finish(void)
	340	{
	341	/* ensure not to come back here if it wasn't intended */
	342	PSPR = 0;
	343	}
	344
711be5cc	345	static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
649de51b	346	.save_count = SLEEP_SAVE_COUNT,
711be5cc EM	347	.save = pxa27x_cpu_pm_save,
	348	.restore = pxa27x_cpu_pm_restore,
	349	.valid = pxa27x_cpu_pm_valid,
	350	.enter = pxa27x_cpu_pm_enter,
4104980a RK	351	.prepare = pxa27x_cpu_pm_prepare,
4104980a RK	352	.finish = pxa27x_cpu_pm_finish,
e176bb05	353	};
711be5cc EM	354
	355	static void __init pxa27x_init_pm(void)
	356	{
	357	pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
	358	}
f79299ca	359	#else
f79299ca	360	static inline void pxa27x_init_pm(void) {}
a8fa3f0c NP	361	#endif
a8fa3f0c NP	362
c95530c7	363	/* PXA27x: Various gpios can issue wakeup events. This logic only
	364	* handles the simple cases, not the WEMUX2 and WEMUX3 options
	365	*/
a3f4c927	366	static int pxa27x_set_wake(struct irq_data *d, unsigned int on)
c95530c7	367	{
4929f5a8	368	int gpio = pxa_irq_to_gpio(d->irq);
c95530c7	369	uint32_t mask;
c95530c7	370
c0a596d6	371	if (gpio >= 0 && gpio < 128)
c0a596d6	372	return gpio_set_wake(gpio, on);
c95530c7	373
a3f4c927	374	if (d->irq == IRQ_KEYPAD)
c0a596d6	375	return keypad_set_wake(on);
c95530c7	376
a3f4c927	377	switch (d->irq) {
c95530c7	378	case IRQ_RTCAlrm:
	379	mask = PWER_RTC;
	380	break;
	381	case IRQ_USB:
	382	mask = 1u << 26;
	383	break;
	384	default:
	385	return -EINVAL;
	386	}
	387
c95530c7	388	if (on)
	389	PWER \|= mask;
	390	else
	391	PWER &=~mask;
	392
	393	return 0;
	394	}
	395
	396	void __init pxa27x_init_irq(void)
	397	{
b9e25ace	398	pxa_init_irq(34, pxa27x_set_wake);
c95530c7	399	}
c95530c7	400
851982c1 MV	401	static struct map_desc pxa27x_io_desc[] __initdata = {
851982c1 MV	402	{ /* Mem Ctl */
97b09da4	403	.virtual = (unsigned long)SMEMC_VIRT,
ad68bb9f	404	.pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE),
851982c1 MV	405	.length = 0x00200000,
	406	.type = MT_DEVICE
	407	}, { /* IMem ctl */
	408	.virtual = 0xfe000000,
	409	.pfn = __phys_to_pfn(0x58000000),
	410	.length = 0x00100000,
	411	.type = MT_DEVICE
	412	},
	413	};
	414
	415	void __init pxa27x_map_io(void)
	416	{
	417	pxa_map_io();
	418	iotable_init(ARRAY_AND_SIZE(pxa27x_io_desc));
	419	pxa27x_get_clk_frequency_khz(1);
	420	}
	421
1da177e4 LT	422	/*
	423	* device registration specific to PXA27x.
	424	*/
9ba63c4f	425	void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
b7a36701	426	{
bc3a5959 PZ	427	local_irq_disable();
	428	PCFR \|= PCFR_PI2CEN;
	429	local_irq_enable();
14758220	430	pxa_register_device(&pxa27x_device_i2c_power, info);
b7a36701 MR	431	}
b7a36701 MR	432
b95ace54	433	static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = {
b8f649f1 HZ	434	.irq_base = PXA_GPIO_TO_IRQ(0),
b8f649f1 HZ	435	.gpio_set_wake = gpio_set_wake,
b95ace54 RJ	436	};
b95ace54 RJ	437
1da177e4	438	static struct platform_device *devices[] __initdata = {
7a857620	439	&pxa27x_device_udc,
09a5358d	440	&pxa_device_pmu,
e09d02e1	441	&pxa_device_i2s,
f0fba2ad LG	442	&pxa_device_asoc_ssp1,
	443	&pxa_device_asoc_ssp2,
	444	&pxa_device_asoc_ssp3,
	445	&pxa_device_asoc_platform,
72493146	446	&sa1100_device_rtc,
e09d02e1	447	&pxa_device_rtc,
d8e0db11	448	&pxa27x_device_ssp1,
	449	&pxa27x_device_ssp2,
	450	&pxa27x_device_ssp3,
75540c1a	451	&pxa27x_device_pwm0,
75540c1a	452	&pxa27x_device_pwm1,
1da177e4 LT	453	};
	454
	455	static int __init pxa27x_init(void)
	456	{
2eaa03b5	457	int ret = 0;
c0165504	458
e176bb05	459	if (cpu_is_pxa27x()) {
04fef228 EM	460
	461	reset_status = RCSR;
	462
0a0300dc	463	clkdev_add_table(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));
a6dba20c	464
fef1f99a	465	if ((ret = pxa_init_dma(IRQ_DMA, 32)))
f53f066c	466	return ret;
f79299ca	467
711be5cc	468	pxa27x_init_pm();
f79299ca	469
2eaa03b5 RW	470	register_syscore_ops(&pxa_irq_syscore_ops);
2eaa03b5 RW	471	register_syscore_ops(&pxa2xx_mfp_syscore_ops);
2eaa03b5	472	register_syscore_ops(&pxa2xx_clock_syscore_ops);
c0165504	473
2cab0292	474	pxa_register_device(&pxa27x_device_gpio, &pxa27x_gpio_info);
e176bb05 RK	475	ret = platform_add_devices(devices, ARRAY_SIZE(devices));
e176bb05 RK	476	}
c0165504	477
e176bb05	478	return ret;
1da177e4 LT	479	}
1da177e4 LT	480
1c104e0e	481	postcore_initcall(pxa27x_init);