[deliverable/linux.git] / arch / arm / mach-pxa / pxa27x.c

/*
 *  linux/arch/arm/mach-pxa/pxa27x.c
 *
 *  Author:	Nicolas Pitre
 *  Created:	Nov 05, 2002
 *  Copyright:	MontaVista Software Inc.
 *
 * Code specific to PXA27x aka Bulverde.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/suspend.h>
#include <linux/platform_device.h>
#include <linux/sysdev.h>

#include <mach/hardware.h>
#include <asm/irq.h>
#include <mach/irqs.h>
#include <mach/gpio.h>
#include <mach/pxa27x.h>
#include <mach/reset.h>
#include <mach/ohci.h>
#include <mach/pm.h>
#include <mach/dma.h>
#include <plat/i2c.h>

#include "generic.h"
#include "devices.h"
#include "clock.h"

void pxa27x_clear_otgph(void)
{
	if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
		PSSR |= PSSR_OTGPH;
}
EXPORT_SYMBOL(pxa27x_clear_otgph);

/* Crystal clock: 13MHz */
#define BASE_CLK	13000000

/*
 * Get the clock frequency as reflected by CCSR and the turbo flag.
 * We assume these values have been applied via a fcs.
 * If info is not 0 we also display the current settings.
 */
unsigned int pxa27x_get_clk_frequency_khz(int info)
{
	unsigned long ccsr, clkcfg;
	unsigned int l, L, m, M, n2, N, S;
       	int cccr_a, t, ht, b;

	ccsr = CCSR;
	cccr_a = CCCR & (1 << 25);

	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	t  = clkcfg & (1 << 0);
	ht = clkcfg & (1 << 2);
	b  = clkcfg & (1 << 3);

	l  = ccsr & 0x1f;
	n2 = (ccsr>>7) & 0xf;
	m  = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;

	L  = l * BASE_CLK;
	N  = (L * n2) / 2;
	M  = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	S  = (b) ? L : (L/2);

	if (info) {
		printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
			L / 1000000, (L % 1000000) / 10000, l );
		printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
			N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
			(t) ? "" : "in" );
		printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
			M / 1000000, (M % 1000000) / 10000, m );
		printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
			S / 1000000, (S % 1000000) / 10000 );
	}

	return (t) ? (N/1000) : (L/1000);
}

/*
 * Return the current mem clock frequency in units of 10kHz as
 * reflected by CCCR[A], B, and L
 */
unsigned int pxa27x_get_memclk_frequency_10khz(void)
{
	unsigned long ccsr, clkcfg;
	unsigned int l, L, m, M;
       	int cccr_a, b;

	ccsr = CCSR;
	cccr_a = CCCR & (1 << 25);

	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	b = clkcfg & (1 << 3);

	l = ccsr & 0x1f;
	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;

	L = l * BASE_CLK;
	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));

	return (M / 10000);
}

/*
 * Return the current LCD clock frequency in units of 10kHz as
 */
static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
{
	unsigned long ccsr;
	unsigned int l, L, k, K;

	ccsr = CCSR;

	l = ccsr & 0x1f;
	k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;

	L = l * BASE_CLK;
	K = L / k;

	return (K / 10000);
}

static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
{
	return pxa27x_get_lcdclk_frequency_10khz() * 10000;
}

static const struct clkops clk_pxa27x_lcd_ops = {
	.enable		= clk_cken_enable,
	.disable	= clk_cken_disable,
	.getrate	= clk_pxa27x_lcd_getrate,
};

static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
static DEFINE_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
static DEFINE_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
static DEFINE_CKEN(pxa27x_stuart, STUART, 14857000, 1);
static DEFINE_CKEN(pxa27x_i2s, I2S, 14682000, 0);
static DEFINE_CKEN(pxa27x_i2c, I2C, 32842000, 0);
static DEFINE_CKEN(pxa27x_usb, USB, 48000000, 5);
static DEFINE_CKEN(pxa27x_mmc, MMC, 19500000, 0);
static DEFINE_CKEN(pxa27x_ficp, FICP, 48000000, 0);
static DEFINE_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
static DEFINE_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
static DEFINE_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
static DEFINE_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
static DEFINE_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
static DEFINE_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
static DEFINE_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
static DEFINE_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
static DEFINE_CKEN(pxa27x_ac97, AC97, 24576000, 0);
static DEFINE_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
static DEFINE_CKEN(pxa27x_msl, MSL, 48000000, 0);
static DEFINE_CKEN(pxa27x_usim, USIM, 48000000, 0);
static DEFINE_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
static DEFINE_CKEN(pxa27x_im, IM, 0, 0);
static DEFINE_CKEN(pxa27x_memc, MEMC, 0, 0);

static struct clk_lookup pxa27x_clkregs[] = {
	INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
	INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL),
	INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL),
	INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL),
	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL),
	INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL),
	INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL),
	INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL),
	INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL),
	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"),
	INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"),
	INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL),
	INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL),
	INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL),
	INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL),
	INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL),
	INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL),
	INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL),
	INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL),
	INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"),
	INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"),
	INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"),
	INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"),
	INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
	INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
	INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
};

#ifdef CONFIG_PM

#define SAVE(x)		sleep_save[SLEEP_SAVE_##x] = x
#define RESTORE(x)	x = sleep_save[SLEEP_SAVE_##x]

/*
 * allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM
 */
static unsigned int pwrmode = PWRMODE_SLEEP;

int __init pxa27x_set_pwrmode(unsigned int mode)
{
	switch (mode) {
	case PWRMODE_SLEEP:
	case PWRMODE_DEEPSLEEP:
		pwrmode = mode;
		return 0;
	}

	return -EINVAL;
}

/*
 * List of global PXA peripheral registers to preserve.
 * More ones like CP and general purpose register values are preserved
 * with the stack pointer in sleep.S.
 */
enum {
	SLEEP_SAVE_PSTR,
	SLEEP_SAVE_CKEN,
	SLEEP_SAVE_MDREFR,
	SLEEP_SAVE_PCFR,
	SLEEP_SAVE_COUNT
};

void pxa27x_cpu_pm_save(unsigned long *sleep_save)
{
	SAVE(MDREFR);
	SAVE(PCFR);

	SAVE(CKEN);
	SAVE(PSTR);
}

void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
{
	RESTORE(MDREFR);
	RESTORE(PCFR);

	PSSR = PSSR_RDH | PSSR_PH;

	RESTORE(CKEN);
	RESTORE(PSTR);
}

void pxa27x_cpu_pm_enter(suspend_state_t state)
{
	extern void pxa_cpu_standby(void);

	/* ensure voltage-change sequencer not initiated, which hangs */
	PCFR &= ~PCFR_FVC;

	/* Clear edge-detect status register. */
	PEDR = 0xDF12FE1B;

	/* Clear reset status */
	RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;

	switch (state) {
	case PM_SUSPEND_STANDBY:
		pxa_cpu_standby();
		break;
	case PM_SUSPEND_MEM:
		pxa27x_cpu_suspend(pwrmode);
		break;
	}
}

static int pxa27x_cpu_pm_valid(suspend_state_t state)
{
	return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
}

static int pxa27x_cpu_pm_prepare(void)
{
	/* set resume return address */
	PSPR = virt_to_phys(pxa_cpu_resume);
	return 0;
}

static void pxa27x_cpu_pm_finish(void)
{
	/* ensure not to come back here if it wasn't intended */
	PSPR = 0;
}

static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
	.save_count	= SLEEP_SAVE_COUNT,
	.save		= pxa27x_cpu_pm_save,
	.restore	= pxa27x_cpu_pm_restore,
	.valid		= pxa27x_cpu_pm_valid,
	.enter		= pxa27x_cpu_pm_enter,
	.prepare	= pxa27x_cpu_pm_prepare,
	.finish		= pxa27x_cpu_pm_finish,
};

static void __init pxa27x_init_pm(void)
{
	pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
}
#else
static inline void pxa27x_init_pm(void) {}
#endif

/* PXA27x:  Various gpios can issue wakeup events.  This logic only
 * handles the simple cases, not the WEMUX2 and WEMUX3 options
 */
static int pxa27x_set_wake(unsigned int irq, unsigned int on)
{
	int gpio = IRQ_TO_GPIO(irq);
	uint32_t mask;

	if (gpio >= 0 && gpio < 128)
		return gpio_set_wake(gpio, on);

	if (irq == IRQ_KEYPAD)
		return keypad_set_wake(on);

	switch (irq) {
	case IRQ_RTCAlrm:
		mask = PWER_RTC;
		break;
	case IRQ_USB:
		mask = 1u << 26;
		break;
	default:
		return -EINVAL;
	}

	if (on)
		PWER |= mask;
	else
		PWER &=~mask;

	return 0;
}

void __init pxa27x_init_irq(void)
{
	pxa_init_irq(34, pxa27x_set_wake);
	pxa_init_gpio(IRQ_GPIO_2_x, 2, 120, pxa27x_set_wake);
}

/*
 * device registration specific to PXA27x.
 */
void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
{
	local_irq_disable();
	PCFR |= PCFR_PI2CEN;
	local_irq_enable();
	pxa_register_device(&pxa27x_device_i2c_power, info);
}

static struct platform_device *devices[] __initdata = {
	&pxa27x_device_udc,
	&pxa_device_ffuart,
	&pxa_device_btuart,
	&pxa_device_stuart,
	&pxa_device_i2s,
	&sa1100_device_rtc,
	&pxa_device_rtc,
	&pxa27x_device_ssp1,
	&pxa27x_device_ssp2,
	&pxa27x_device_ssp3,
	&pxa27x_device_pwm0,
	&pxa27x_device_pwm1,
};

static struct sys_device pxa27x_sysdev[] = {
	{
		.cls	= &pxa_irq_sysclass,
	}, {
		.cls	= &pxa2xx_mfp_sysclass,
	}, {
		.cls	= &pxa_gpio_sysclass,
	},
};

static int __init pxa27x_init(void)
{
	int i, ret = 0;

	if (cpu_is_pxa27x()) {

		reset_status = RCSR;

		clks_register(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));

		if ((ret = pxa_init_dma(IRQ_DMA, 32)))
			return ret;

		pxa27x_init_pm();

		for (i = 0; i < ARRAY_SIZE(pxa27x_sysdev); i++) {
			ret = sysdev_register(&pxa27x_sysdev[i]);
			if (ret)
				pr_err("failed to register sysdev[%d]\n", i);
		}

		ret = platform_add_devices(devices, ARRAY_SIZE(devices));
	}

	return ret;
}

postcore_initcall(pxa27x_init);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-pxa/pxa27x.c
	3	*
	4	* Author: Nicolas Pitre
	5	* Created: Nov 05, 2002
	6	* Copyright: MontaVista Software Inc.
	7	*
	8	* Code specific to PXA27x aka Bulverde.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
1da177e4 LT	14	#include <linux/module.h>
	15	#include <linux/kernel.h>
	16	#include <linux/init.h>
95d9ffbe	17	#include <linux/suspend.h>
d052d1be	18	#include <linux/platform_device.h>
c0165504	19	#include <linux/sysdev.h>
1da177e4	20
a09e64fb	21	#include <mach/hardware.h>
1da177e4	22	#include <asm/irq.h>
a09e64fb	23	#include <mach/irqs.h>
a58fbcd8	24	#include <mach/gpio.h>
51c62982	25	#include <mach/pxa27x.h>
afd2fc02	26	#include <mach/reset.h>
a09e64fb RK	27	#include <mach/ohci.h>
	28	#include <mach/pm.h>
	29	#include <mach/dma.h>
f0a83701	30	#include <plat/i2c.h>
1da177e4 LT	31
1da177e4 LT	32	#include "generic.h"
46c41e62	33	#include "devices.h"
a6dba20c	34	#include "clock.h"
1da177e4	35
0cb0b0d3 EM	36	void pxa27x_clear_otgph(void)
	37	{
	38	if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
	39	PSSR \|= PSSR_OTGPH;
	40	}
	41	EXPORT_SYMBOL(pxa27x_clear_otgph);
	42
1da177e4 LT	43	/* Crystal clock: 13MHz */
	44	#define BASE_CLK 13000000
	45
	46	/*
	47	* Get the clock frequency as reflected by CCSR and the turbo flag.
	48	* We assume these values have been applied via a fcs.
	49	* If info is not 0 we also display the current settings.
	50	*/
15a40333	51	unsigned int pxa27x_get_clk_frequency_khz(int info)
1da177e4 LT	52	{
	53	unsigned long ccsr, clkcfg;
	54	unsigned int l, L, m, M, n2, N, S;
	55	int cccr_a, t, ht, b;
	56
	57	ccsr = CCSR;
	58	cccr_a = CCCR & (1 << 25);
	59
	60	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	61	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
afe5df20	62	t = clkcfg & (1 << 0);
1da177e4 LT	63	ht = clkcfg & (1 << 2);
	64	b = clkcfg & (1 << 3);
	65
	66	l = ccsr & 0x1f;
	67	n2 = (ccsr>>7) & 0xf;
	68	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
	69
	70	L = l * BASE_CLK;
	71	N = (L * n2) / 2;
	72	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	73	S = (b) ? L : (L/2);
	74
	75	if (info) {
	76	printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
	77	L / 1000000, (L % 1000000) / 10000, l );
	78	printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
	79	N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
	80	(t) ? "" : "in" );
	81	printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
	82	M / 1000000, (M % 1000000) / 10000, m );
	83	printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
	84	S / 1000000, (S % 1000000) / 10000 );
	85	}
	86
	87	return (t) ? (N/1000) : (L/1000);
	88	}
	89
	90	/*
	91	* Return the current mem clock frequency in units of 10kHz as
	92	* reflected by CCCR[A], B, and L
	93	*/
15a40333	94	unsigned int pxa27x_get_memclk_frequency_10khz(void)
1da177e4 LT	95	{
	96	unsigned long ccsr, clkcfg;
	97	unsigned int l, L, m, M;
	98	int cccr_a, b;
	99
	100	ccsr = CCSR;
	101	cccr_a = CCCR & (1 << 25);
	102
	103	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	104	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	105	b = clkcfg & (1 << 3);
	106
	107	l = ccsr & 0x1f;
	108	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
	109
	110	L = l * BASE_CLK;
	111	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	112
	113	return (M / 10000);
	114	}
	115
	116	/*
	117	* Return the current LCD clock frequency in units of 10kHz as
	118	*/
a88a447d	119	static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
1da177e4 LT	120	{
	121	unsigned long ccsr;
	122	unsigned int l, L, k, K;
	123
	124	ccsr = CCSR;
	125
	126	l = ccsr & 0x1f;
	127	k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
	128
	129	L = l * BASE_CLK;
	130	K = L / k;
	131
	132	return (K / 10000);
	133	}
	134
a6dba20c RK	135	static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
	136	{
	137	return pxa27x_get_lcdclk_frequency_10khz() * 10000;
	138	}
	139
	140	static const struct clkops clk_pxa27x_lcd_ops = {
	141	.enable = clk_cken_enable,
	142	.disable = clk_cken_disable,
	143	.getrate = clk_pxa27x_lcd_getrate,
	144	};
	145
8c3abc7d RK	146	static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
	147	static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
	148	static DEFINE_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
	149	static DEFINE_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
	150	static DEFINE_CKEN(pxa27x_stuart, STUART, 14857000, 1);
	151	static DEFINE_CKEN(pxa27x_i2s, I2S, 14682000, 0);
	152	static DEFINE_CKEN(pxa27x_i2c, I2C, 32842000, 0);
	153	static DEFINE_CKEN(pxa27x_usb, USB, 48000000, 5);
	154	static DEFINE_CKEN(pxa27x_mmc, MMC, 19500000, 0);
	155	static DEFINE_CKEN(pxa27x_ficp, FICP, 48000000, 0);
	156	static DEFINE_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
	157	static DEFINE_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
	158	static DEFINE_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
	159	static DEFINE_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
	160	static DEFINE_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
	161	static DEFINE_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
	162	static DEFINE_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
	163	static DEFINE_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
	164	static DEFINE_CKEN(pxa27x_ac97, AC97, 24576000, 0);
	165	static DEFINE_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
	166	static DEFINE_CKEN(pxa27x_msl, MSL, 48000000, 0);
	167	static DEFINE_CKEN(pxa27x_usim, USIM, 48000000, 0);
	168	static DEFINE_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
	169	static DEFINE_CKEN(pxa27x_im, IM, 0, 0);
	170	static DEFINE_CKEN(pxa27x_memc, MEMC, 0, 0);
	171
	172	static struct clk_lookup pxa27x_clkregs[] = {
	173	INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
	174	INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL),
	175	INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL),
	176	INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL),
	177	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL),
	178	INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL),
	179	INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL),
	180	INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL),
	181	INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL),
	182	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"),
	183	INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"),
	184	INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL),
	185	INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL),
	186	INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL),
	187	INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL),
	188	INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL),
	189	INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL),
	190	INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL),
	191	INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL),
	192	INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"),
	193	INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"),
	194	INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"),
	195	INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"),
	196	INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
	197	INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
	198	INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
a6dba20c RK	199	};
a6dba20c RK	200
a8fa3f0c NP	201	#ifdef CONFIG_PM
a8fa3f0c NP	202
711be5cc EM	203	#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
	204	#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
	205
d082d36e MR	206	/*
	207	* allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM
	208	*/
	209	static unsigned int pwrmode = PWRMODE_SLEEP;
	210
	211	int __init pxa27x_set_pwrmode(unsigned int mode)
	212	{
	213	switch (mode) {
	214	case PWRMODE_SLEEP:
	215	case PWRMODE_DEEPSLEEP:
	216	pwrmode = mode;
	217	return 0;
	218	}
	219
	220	return -EINVAL;
	221	}
	222
711be5cc EM	223	/*
	224	* List of global PXA peripheral registers to preserve.
	225	* More ones like CP and general purpose register values are preserved
	226	* with the stack pointer in sleep.S.
	227	*/
5a3d9651	228	enum {
711be5cc	229	SLEEP_SAVE_PSTR,
711be5cc	230	SLEEP_SAVE_CKEN,
711be5cc	231	SLEEP_SAVE_MDREFR,
5a3d9651	232	SLEEP_SAVE_PCFR,
649de51b	233	SLEEP_SAVE_COUNT
711be5cc EM	234	};
	235
	236	void pxa27x_cpu_pm_save(unsigned long *sleep_save)
	237	{
711be5cc	238	SAVE(MDREFR);
5a3d9651	239	SAVE(PCFR);
711be5cc	240
711be5cc EM	241	SAVE(CKEN);
711be5cc EM	242	SAVE(PSTR);
711be5cc EM	243	}
	244
	245	void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
	246	{
711be5cc	247	RESTORE(MDREFR);
5a3d9651	248	RESTORE(PCFR);
711be5cc EM	249
	250	PSSR = PSSR_RDH \| PSSR_PH;
	251
	252	RESTORE(CKEN);
711be5cc EM	253	RESTORE(PSTR);
	254	}
	255
	256	void pxa27x_cpu_pm_enter(suspend_state_t state)
8775420d TP	257	{
8775420d TP	258	extern void pxa_cpu_standby(void);
8775420d	259
8775420d TP	260	/* ensure voltage-change sequencer not initiated, which hangs */
	261	PCFR &= ~PCFR_FVC;
	262
	263	/* Clear edge-detect status register. */
	264	PEDR = 0xDF12FE1B;
	265
dc38e2ad RK	266	/* Clear reset status */
	267	RCSR = RCSR_HWR \| RCSR_WDR \| RCSR_SMR \| RCSR_GPR;
	268
8775420d	269	switch (state) {
26705ca4 TP	270	case PM_SUSPEND_STANDBY:
	271	pxa_cpu_standby();
	272	break;
8775420d	273	case PM_SUSPEND_MEM:
d082d36e	274	pxa27x_cpu_suspend(pwrmode);
8775420d TP	275	break;
	276	}
	277	}
1da177e4	278
711be5cc	279	static int pxa27x_cpu_pm_valid(suspend_state_t state)
88dfe98c RK	280	{
	281	return state == PM_SUSPEND_MEM \|\| state == PM_SUSPEND_STANDBY;
	282	}
	283
4104980a RK	284	static int pxa27x_cpu_pm_prepare(void)
	285	{
	286	/* set resume return address */
	287	PSPR = virt_to_phys(pxa_cpu_resume);
	288	return 0;
	289	}
	290
	291	static void pxa27x_cpu_pm_finish(void)
	292	{
	293	/* ensure not to come back here if it wasn't intended */
	294	PSPR = 0;
	295	}
	296
711be5cc	297	static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
649de51b	298	.save_count = SLEEP_SAVE_COUNT,
711be5cc EM	299	.save = pxa27x_cpu_pm_save,
	300	.restore = pxa27x_cpu_pm_restore,
	301	.valid = pxa27x_cpu_pm_valid,
	302	.enter = pxa27x_cpu_pm_enter,
4104980a RK	303	.prepare = pxa27x_cpu_pm_prepare,
4104980a RK	304	.finish = pxa27x_cpu_pm_finish,
e176bb05	305	};
711be5cc EM	306
	307	static void __init pxa27x_init_pm(void)
	308	{
	309	pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
	310	}
f79299ca	311	#else
f79299ca	312	static inline void pxa27x_init_pm(void) {}
a8fa3f0c NP	313	#endif
a8fa3f0c NP	314
c95530c7	315	/* PXA27x: Various gpios can issue wakeup events. This logic only
	316	* handles the simple cases, not the WEMUX2 and WEMUX3 options
	317	*/
c95530c7	318	static int pxa27x_set_wake(unsigned int irq, unsigned int on)
	319	{
	320	int gpio = IRQ_TO_GPIO(irq);
	321	uint32_t mask;
	322
c0a596d6	323	if (gpio >= 0 && gpio < 128)
c0a596d6	324	return gpio_set_wake(gpio, on);
c95530c7	325
c0a596d6	326	if (irq == IRQ_KEYPAD)
c0a596d6	327	return keypad_set_wake(on);
c95530c7	328
	329	switch (irq) {
	330	case IRQ_RTCAlrm:
	331	mask = PWER_RTC;
	332	break;
	333	case IRQ_USB:
	334	mask = 1u << 26;
	335	break;
	336	default:
	337	return -EINVAL;
	338	}
	339
c95530c7	340	if (on)
	341	PWER \|= mask;
	342	else
	343	PWER &=~mask;
	344
	345	return 0;
	346	}
	347
	348	void __init pxa27x_init_irq(void)
	349	{
b9e25ace	350	pxa_init_irq(34, pxa27x_set_wake);
a58fbcd8	351	pxa_init_gpio(IRQ_GPIO_2_x, 2, 120, pxa27x_set_wake);
c95530c7	352	}
c95530c7	353
1da177e4 LT	354	/*
	355	* device registration specific to PXA27x.
	356	*/
9ba63c4f	357	void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
b7a36701	358	{
bc3a5959 PZ	359	local_irq_disable();
	360	PCFR \|= PCFR_PI2CEN;
	361	local_irq_enable();
14758220	362	pxa_register_device(&pxa27x_device_i2c_power, info);
b7a36701 MR	363	}
b7a36701 MR	364
1da177e4	365	static struct platform_device *devices[] __initdata = {
7a857620	366	&pxa27x_device_udc,
e09d02e1 EM	367	&pxa_device_ffuart,
	368	&pxa_device_btuart,
	369	&pxa_device_stuart,
e09d02e1	370	&pxa_device_i2s,
72493146	371	&sa1100_device_rtc,
e09d02e1	372	&pxa_device_rtc,
d8e0db11	373	&pxa27x_device_ssp1,
	374	&pxa27x_device_ssp2,
	375	&pxa27x_device_ssp3,
75540c1a	376	&pxa27x_device_pwm0,
75540c1a	377	&pxa27x_device_pwm1,
1da177e4 LT	378	};
1da177e4 LT	379
c0165504	380	static struct sys_device pxa27x_sysdev[] = {
c0165504	381	{
c0165504	382	.cls = &pxa_irq_sysclass,
5a3d9651 EM	383	}, {
5a3d9651 EM	384	.cls = &pxa2xx_mfp_sysclass,
16dfdbf0	385	}, {
16dfdbf0	386	.cls = &pxa_gpio_sysclass,
c0165504	387	},
	388	};
	389
1da177e4 LT	390	static int __init pxa27x_init(void)
1da177e4 LT	391	{
c0165504	392	int i, ret = 0;
c0165504	393
e176bb05	394	if (cpu_is_pxa27x()) {
04fef228 EM	395
	396	reset_status = RCSR;
	397
8c3abc7d	398	clks_register(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));
a6dba20c	399
fef1f99a	400	if ((ret = pxa_init_dma(IRQ_DMA, 32)))
f53f066c	401	return ret;
f79299ca	402
711be5cc	403	pxa27x_init_pm();
f79299ca	404
c0165504	405	for (i = 0; i < ARRAY_SIZE(pxa27x_sysdev); i++) {
	406	ret = sysdev_register(&pxa27x_sysdev[i]);
	407	if (ret)
	408	pr_err("failed to register sysdev[%d]\n", i);
	409	}
	410
e176bb05 RK	411	ret = platform_add_devices(devices, ARRAY_SIZE(devices));
e176bb05 RK	412	}
c0165504	413
e176bb05	414	return ret;
1da177e4 LT	415	}
1da177e4 LT	416
1c104e0e	417	postcore_initcall(pxa27x_init);