[deliverable/linux.git] / arch / arm / mach-pxa / pxa27x.c

/*
 *  linux/arch/arm/mach-pxa/pxa27x.c
 *
 *  Author:	Nicolas Pitre
 *  Created:	Nov 05, 2002
 *  Copyright:	MontaVista Software Inc.
 *
 * Code specific to PXA27x aka Bulverde.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/suspend.h>
#include <linux/platform_device.h>
#include <linux/sysdev.h>

#include <mach/hardware.h>
#include <asm/irq.h>
#include <mach/irqs.h>
#include <mach/pxa27x.h>
#include <mach/reset.h>
#include <mach/ohci.h>
#include <mach/pm.h>
#include <mach/dma.h>
#include <mach/i2c.h>

#include "generic.h"
#include "devices.h"
#include "clock.h"

void pxa27x_clear_otgph(void)
{
	if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
		PSSR |= PSSR_OTGPH;
}
EXPORT_SYMBOL(pxa27x_clear_otgph);

/* Crystal clock: 13MHz */
#define BASE_CLK	13000000

/*
 * Get the clock frequency as reflected by CCSR and the turbo flag.
 * We assume these values have been applied via a fcs.
 * If info is not 0 we also display the current settings.
 */
unsigned int pxa27x_get_clk_frequency_khz(int info)
{
	unsigned long ccsr, clkcfg;
	unsigned int l, L, m, M, n2, N, S;
       	int cccr_a, t, ht, b;

	ccsr = CCSR;
	cccr_a = CCCR & (1 << 25);

	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	t  = clkcfg & (1 << 0);
	ht = clkcfg & (1 << 2);
	b  = clkcfg & (1 << 3);

	l  = ccsr & 0x1f;
	n2 = (ccsr>>7) & 0xf;
	m  = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;

	L  = l * BASE_CLK;
	N  = (L * n2) / 2;
	M  = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	S  = (b) ? L : (L/2);

	if (info) {
		printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
			L / 1000000, (L % 1000000) / 10000, l );
		printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
			N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
			(t) ? "" : "in" );
		printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
			M / 1000000, (M % 1000000) / 10000, m );
		printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
			S / 1000000, (S % 1000000) / 10000 );
	}

	return (t) ? (N/1000) : (L/1000);
}

/*
 * Return the current mem clock frequency in units of 10kHz as
 * reflected by CCCR[A], B, and L
 */
unsigned int pxa27x_get_memclk_frequency_10khz(void)
{
	unsigned long ccsr, clkcfg;
	unsigned int l, L, m, M;
       	int cccr_a, b;

	ccsr = CCSR;
	cccr_a = CCCR & (1 << 25);

	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	b = clkcfg & (1 << 3);

	l = ccsr & 0x1f;
	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;

	L = l * BASE_CLK;
	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));

	return (M / 10000);
}

/*
 * Return the current LCD clock frequency in units of 10kHz as
 */
static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
{
	unsigned long ccsr;
	unsigned int l, L, k, K;

	ccsr = CCSR;

	l = ccsr & 0x1f;
	k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;

	L = l * BASE_CLK;
	K = L / k;

	return (K / 10000);
}

static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
{
	return pxa27x_get_lcdclk_frequency_10khz() * 10000;
}

static const struct clkops clk_pxa27x_lcd_ops = {
	.enable		= clk_cken_enable,
	.disable	= clk_cken_disable,
	.getrate	= clk_pxa27x_lcd_getrate,
};

static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
static DEFINE_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
static DEFINE_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
static DEFINE_CKEN(pxa27x_stuart, STUART, 14857000, 1);
static DEFINE_CKEN(pxa27x_i2s, I2S, 14682000, 0);
static DEFINE_CKEN(pxa27x_i2c, I2C, 32842000, 0);
static DEFINE_CKEN(pxa27x_usb, USB, 48000000, 5);
static DEFINE_CKEN(pxa27x_mmc, MMC, 19500000, 0);
static DEFINE_CKEN(pxa27x_ficp, FICP, 48000000, 0);
static DEFINE_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
static DEFINE_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
static DEFINE_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
static DEFINE_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
static DEFINE_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
static DEFINE_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
static DEFINE_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
static DEFINE_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
static DEFINE_CKEN(pxa27x_ac97, AC97, 24576000, 0);
static DEFINE_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
static DEFINE_CKEN(pxa27x_msl, MSL, 48000000, 0);
static DEFINE_CKEN(pxa27x_usim, USIM, 48000000, 0);
static DEFINE_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
static DEFINE_CKEN(pxa27x_im, IM, 0, 0);
static DEFINE_CKEN(pxa27x_memc, MEMC, 0, 0);

static struct clk_lookup pxa27x_clkregs[] = {
	INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
	INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL),
	INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL),
	INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL),
	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL),
	INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL),
	INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL),
	INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL),
	INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL),
	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"),
	INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"),
	INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL),
	INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL),
	INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL),
	INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL),
	INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL),
	INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL),
	INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL),
	INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL),
	INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"),
	INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"),
	INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"),
	INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"),
	INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
	INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
	INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
};

#ifdef CONFIG_PM

#define SAVE(x)		sleep_save[SLEEP_SAVE_##x] = x
#define RESTORE(x)	x = sleep_save[SLEEP_SAVE_##x]

/*
 * List of global PXA peripheral registers to preserve.
 * More ones like CP and general purpose register values are preserved
 * with the stack pointer in sleep.S.
 */
enum {
	SLEEP_SAVE_PSTR,
	SLEEP_SAVE_CKEN,
	SLEEP_SAVE_MDREFR,
	SLEEP_SAVE_PCFR,
	SLEEP_SAVE_COUNT
};

void pxa27x_cpu_pm_save(unsigned long *sleep_save)
{
	SAVE(MDREFR);
	SAVE(PCFR);

	SAVE(CKEN);
	SAVE(PSTR);
}

void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
{
	RESTORE(MDREFR);
	RESTORE(PCFR);

	PSSR = PSSR_RDH | PSSR_PH;

	RESTORE(CKEN);
	RESTORE(PSTR);
}

void pxa27x_cpu_pm_enter(suspend_state_t state)
{
	extern void pxa_cpu_standby(void);

	/* ensure voltage-change sequencer not initiated, which hangs */
	PCFR &= ~PCFR_FVC;

	/* Clear edge-detect status register. */
	PEDR = 0xDF12FE1B;

	/* Clear reset status */
	RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;

	switch (state) {
	case PM_SUSPEND_STANDBY:
		pxa_cpu_standby();
		break;
	case PM_SUSPEND_MEM:
		pxa27x_cpu_suspend(PWRMODE_SLEEP);
		break;
	}
}

static int pxa27x_cpu_pm_valid(suspend_state_t state)
{
	return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
}

static int pxa27x_cpu_pm_prepare(void)
{
	/* set resume return address */
	PSPR = virt_to_phys(pxa_cpu_resume);
	return 0;
}

static void pxa27x_cpu_pm_finish(void)
{
	/* ensure not to come back here if it wasn't intended */
	PSPR = 0;
}

static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
	.save_count	= SLEEP_SAVE_COUNT,
	.save		= pxa27x_cpu_pm_save,
	.restore	= pxa27x_cpu_pm_restore,
	.valid		= pxa27x_cpu_pm_valid,
	.enter		= pxa27x_cpu_pm_enter,
	.prepare	= pxa27x_cpu_pm_prepare,
	.finish		= pxa27x_cpu_pm_finish,
};

static void __init pxa27x_init_pm(void)
{
	pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
}
#else
static inline void pxa27x_init_pm(void) {}
#endif

/* PXA27x:  Various gpios can issue wakeup events.  This logic only
 * handles the simple cases, not the WEMUX2 and WEMUX3 options
 */
static int pxa27x_set_wake(unsigned int irq, unsigned int on)
{
	int gpio = IRQ_TO_GPIO(irq);
	uint32_t mask;

	if (gpio >= 0 && gpio < 128)
		return gpio_set_wake(gpio, on);

	if (irq == IRQ_KEYPAD)
		return keypad_set_wake(on);

	switch (irq) {
	case IRQ_RTCAlrm:
		mask = PWER_RTC;
		break;
	case IRQ_USB:
		mask = 1u << 26;
		break;
	default:
		return -EINVAL;
	}

	if (on)
		PWER |= mask;
	else
		PWER &=~mask;

	return 0;
}

void __init pxa27x_init_irq(void)
{
	pxa_init_irq(34, pxa27x_set_wake);
	pxa_init_gpio(121, pxa27x_set_wake);
}

/*
 * device registration specific to PXA27x.
 */
void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
{
	local_irq_disable();
	PCFR |= PCFR_PI2CEN;
	local_irq_enable();
	pxa_register_device(&pxa27x_device_i2c_power, info);
}

static struct platform_device *devices[] __initdata = {
	&pxa27x_device_udc,
	&pxa_device_ffuart,
	&pxa_device_btuart,
	&pxa_device_stuart,
	&pxa_device_i2s,
	&sa1100_device_rtc,
	&pxa_device_rtc,
	&pxa27x_device_ssp1,
	&pxa27x_device_ssp2,
	&pxa27x_device_ssp3,
	&pxa27x_device_pwm0,
	&pxa27x_device_pwm1,
};

static struct sys_device pxa27x_sysdev[] = {
	{
		.cls	= &pxa_irq_sysclass,
	}, {
		.cls	= &pxa2xx_mfp_sysclass,
	}, {
		.cls	= &pxa_gpio_sysclass,
	},
};

static int __init pxa27x_init(void)
{
	int i, ret = 0;

	if (cpu_is_pxa27x()) {

		reset_status = RCSR;

		clks_register(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));

		if ((ret = pxa_init_dma(32)))
			return ret;

		pxa27x_init_pm();

		for (i = 0; i < ARRAY_SIZE(pxa27x_sysdev); i++) {
			ret = sysdev_register(&pxa27x_sysdev[i]);
			if (ret)
				pr_err("failed to register sysdev[%d]\n", i);
		}

		ret = platform_add_devices(devices, ARRAY_SIZE(devices));
	}

	return ret;
}

postcore_initcall(pxa27x_init);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-pxa/pxa27x.c
	3	*
	4	* Author: Nicolas Pitre
	5	* Created: Nov 05, 2002
	6	* Copyright: MontaVista Software Inc.
	7	*
	8	* Code specific to PXA27x aka Bulverde.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
1da177e4 LT	14	#include <linux/module.h>
	15	#include <linux/kernel.h>
	16	#include <linux/init.h>
95d9ffbe	17	#include <linux/suspend.h>
d052d1be	18	#include <linux/platform_device.h>
c0165504	19	#include <linux/sysdev.h>
1da177e4	20
a09e64fb	21	#include <mach/hardware.h>
1da177e4	22	#include <asm/irq.h>
a09e64fb	23	#include <mach/irqs.h>
51c62982	24	#include <mach/pxa27x.h>
afd2fc02	25	#include <mach/reset.h>
a09e64fb RK	26	#include <mach/ohci.h>
	27	#include <mach/pm.h>
	28	#include <mach/dma.h>
	29	#include <mach/i2c.h>
1da177e4 LT	30
1da177e4 LT	31	#include "generic.h"
46c41e62	32	#include "devices.h"
a6dba20c	33	#include "clock.h"
1da177e4	34
0cb0b0d3 EM	35	void pxa27x_clear_otgph(void)
	36	{
	37	if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
	38	PSSR \|= PSSR_OTGPH;
	39	}
	40	EXPORT_SYMBOL(pxa27x_clear_otgph);
	41
1da177e4 LT	42	/* Crystal clock: 13MHz */
	43	#define BASE_CLK 13000000
	44
	45	/*
	46	* Get the clock frequency as reflected by CCSR and the turbo flag.
	47	* We assume these values have been applied via a fcs.
	48	* If info is not 0 we also display the current settings.
	49	*/
15a40333	50	unsigned int pxa27x_get_clk_frequency_khz(int info)
1da177e4 LT	51	{
	52	unsigned long ccsr, clkcfg;
	53	unsigned int l, L, m, M, n2, N, S;
	54	int cccr_a, t, ht, b;
	55
	56	ccsr = CCSR;
	57	cccr_a = CCCR & (1 << 25);
	58
	59	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	60	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
afe5df20	61	t = clkcfg & (1 << 0);
1da177e4 LT	62	ht = clkcfg & (1 << 2);
	63	b = clkcfg & (1 << 3);
	64
	65	l = ccsr & 0x1f;
	66	n2 = (ccsr>>7) & 0xf;
	67	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
	68
	69	L = l * BASE_CLK;
	70	N = (L * n2) / 2;
	71	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	72	S = (b) ? L : (L/2);
	73
	74	if (info) {
	75	printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
	76	L / 1000000, (L % 1000000) / 10000, l );
	77	printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
	78	N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
	79	(t) ? "" : "in" );
	80	printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
	81	M / 1000000, (M % 1000000) / 10000, m );
	82	printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
	83	S / 1000000, (S % 1000000) / 10000 );
	84	}
	85
	86	return (t) ? (N/1000) : (L/1000);
	87	}
	88
	89	/*
	90	* Return the current mem clock frequency in units of 10kHz as
	91	* reflected by CCCR[A], B, and L
	92	*/
15a40333	93	unsigned int pxa27x_get_memclk_frequency_10khz(void)
1da177e4 LT	94	{
	95	unsigned long ccsr, clkcfg;
	96	unsigned int l, L, m, M;
	97	int cccr_a, b;
	98
	99	ccsr = CCSR;
	100	cccr_a = CCCR & (1 << 25);
	101
	102	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	103	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	104	b = clkcfg & (1 << 3);
	105
	106	l = ccsr & 0x1f;
	107	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
	108
	109	L = l * BASE_CLK;
	110	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	111
	112	return (M / 10000);
	113	}
	114
	115	/*
	116	* Return the current LCD clock frequency in units of 10kHz as
	117	*/
a88a447d	118	static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
1da177e4 LT	119	{
	120	unsigned long ccsr;
	121	unsigned int l, L, k, K;
	122
	123	ccsr = CCSR;
	124
	125	l = ccsr & 0x1f;
	126	k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
	127
	128	L = l * BASE_CLK;
	129	K = L / k;
	130
	131	return (K / 10000);
	132	}
	133
a6dba20c RK	134	static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
	135	{
	136	return pxa27x_get_lcdclk_frequency_10khz() * 10000;
	137	}
	138
	139	static const struct clkops clk_pxa27x_lcd_ops = {
	140	.enable = clk_cken_enable,
	141	.disable = clk_cken_disable,
	142	.getrate = clk_pxa27x_lcd_getrate,
	143	};
	144
8c3abc7d RK	145	static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
	146	static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
	147	static DEFINE_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
	148	static DEFINE_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
	149	static DEFINE_CKEN(pxa27x_stuart, STUART, 14857000, 1);
	150	static DEFINE_CKEN(pxa27x_i2s, I2S, 14682000, 0);
	151	static DEFINE_CKEN(pxa27x_i2c, I2C, 32842000, 0);
	152	static DEFINE_CKEN(pxa27x_usb, USB, 48000000, 5);
	153	static DEFINE_CKEN(pxa27x_mmc, MMC, 19500000, 0);
	154	static DEFINE_CKEN(pxa27x_ficp, FICP, 48000000, 0);
	155	static DEFINE_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
	156	static DEFINE_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
	157	static DEFINE_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
	158	static DEFINE_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
	159	static DEFINE_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
	160	static DEFINE_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
	161	static DEFINE_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
	162	static DEFINE_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
	163	static DEFINE_CKEN(pxa27x_ac97, AC97, 24576000, 0);
	164	static DEFINE_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
	165	static DEFINE_CKEN(pxa27x_msl, MSL, 48000000, 0);
	166	static DEFINE_CKEN(pxa27x_usim, USIM, 48000000, 0);
	167	static DEFINE_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
	168	static DEFINE_CKEN(pxa27x_im, IM, 0, 0);
	169	static DEFINE_CKEN(pxa27x_memc, MEMC, 0, 0);
	170
	171	static struct clk_lookup pxa27x_clkregs[] = {
	172	INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
	173	INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL),
	174	INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL),
	175	INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL),
	176	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL),
	177	INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL),
	178	INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL),
	179	INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL),
	180	INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL),
	181	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"),
	182	INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"),
	183	INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL),
	184	INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL),
	185	INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL),
	186	INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL),
	187	INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL),
	188	INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL),
	189	INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL),
	190	INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL),
	191	INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"),
	192	INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"),
	193	INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"),
	194	INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"),
	195	INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
	196	INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
	197	INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
a6dba20c RK	198	};
a6dba20c RK	199
a8fa3f0c NP	200	#ifdef CONFIG_PM
a8fa3f0c NP	201
711be5cc EM	202	#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
	203	#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
	204
711be5cc EM	205	/*
	206	* List of global PXA peripheral registers to preserve.
	207	* More ones like CP and general purpose register values are preserved
	208	* with the stack pointer in sleep.S.
	209	*/
5a3d9651	210	enum {
711be5cc	211	SLEEP_SAVE_PSTR,
711be5cc	212	SLEEP_SAVE_CKEN,
711be5cc	213	SLEEP_SAVE_MDREFR,
5a3d9651	214	SLEEP_SAVE_PCFR,
649de51b	215	SLEEP_SAVE_COUNT
711be5cc EM	216	};
	217
	218	void pxa27x_cpu_pm_save(unsigned long *sleep_save)
	219	{
711be5cc	220	SAVE(MDREFR);
5a3d9651	221	SAVE(PCFR);
711be5cc	222
711be5cc EM	223	SAVE(CKEN);
711be5cc EM	224	SAVE(PSTR);
711be5cc EM	225	}
	226
	227	void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
	228	{
711be5cc	229	RESTORE(MDREFR);
5a3d9651	230	RESTORE(PCFR);
711be5cc EM	231
	232	PSSR = PSSR_RDH \| PSSR_PH;
	233
	234	RESTORE(CKEN);
711be5cc EM	235	RESTORE(PSTR);
	236	}
	237
	238	void pxa27x_cpu_pm_enter(suspend_state_t state)
8775420d TP	239	{
8775420d TP	240	extern void pxa_cpu_standby(void);
8775420d	241
8775420d TP	242	/* ensure voltage-change sequencer not initiated, which hangs */
	243	PCFR &= ~PCFR_FVC;
	244
	245	/* Clear edge-detect status register. */
	246	PEDR = 0xDF12FE1B;
	247
dc38e2ad RK	248	/* Clear reset status */
	249	RCSR = RCSR_HWR \| RCSR_WDR \| RCSR_SMR \| RCSR_GPR;
	250
8775420d	251	switch (state) {
26705ca4 TP	252	case PM_SUSPEND_STANDBY:
	253	pxa_cpu_standby();
	254	break;
8775420d	255	case PM_SUSPEND_MEM:
b750a093	256	pxa27x_cpu_suspend(PWRMODE_SLEEP);
8775420d TP	257	break;
	258	}
	259	}
1da177e4	260
711be5cc	261	static int pxa27x_cpu_pm_valid(suspend_state_t state)
88dfe98c RK	262	{
	263	return state == PM_SUSPEND_MEM \|\| state == PM_SUSPEND_STANDBY;
	264	}
	265
4104980a RK	266	static int pxa27x_cpu_pm_prepare(void)
	267	{
	268	/* set resume return address */
	269	PSPR = virt_to_phys(pxa_cpu_resume);
	270	return 0;
	271	}
	272
	273	static void pxa27x_cpu_pm_finish(void)
	274	{
	275	/* ensure not to come back here if it wasn't intended */
	276	PSPR = 0;
	277	}
	278
711be5cc	279	static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
649de51b	280	.save_count = SLEEP_SAVE_COUNT,
711be5cc EM	281	.save = pxa27x_cpu_pm_save,
	282	.restore = pxa27x_cpu_pm_restore,
	283	.valid = pxa27x_cpu_pm_valid,
	284	.enter = pxa27x_cpu_pm_enter,
4104980a RK	285	.prepare = pxa27x_cpu_pm_prepare,
4104980a RK	286	.finish = pxa27x_cpu_pm_finish,
e176bb05	287	};
711be5cc EM	288
	289	static void __init pxa27x_init_pm(void)
	290	{
	291	pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
	292	}
f79299ca	293	#else
f79299ca	294	static inline void pxa27x_init_pm(void) {}
a8fa3f0c NP	295	#endif
a8fa3f0c NP	296
c95530c7	297	/* PXA27x: Various gpios can issue wakeup events. This logic only
	298	* handles the simple cases, not the WEMUX2 and WEMUX3 options
	299	*/
c95530c7	300	static int pxa27x_set_wake(unsigned int irq, unsigned int on)
	301	{
	302	int gpio = IRQ_TO_GPIO(irq);
	303	uint32_t mask;
	304
c0a596d6	305	if (gpio >= 0 && gpio < 128)
c0a596d6	306	return gpio_set_wake(gpio, on);
c95530c7	307
c0a596d6	308	if (irq == IRQ_KEYPAD)
c0a596d6	309	return keypad_set_wake(on);
c95530c7	310
	311	switch (irq) {
	312	case IRQ_RTCAlrm:
	313	mask = PWER_RTC;
	314	break;
	315	case IRQ_USB:
	316	mask = 1u << 26;
	317	break;
	318	default:
	319	return -EINVAL;
	320	}
	321
c95530c7	322	if (on)
	323	PWER \|= mask;
	324	else
	325	PWER &=~mask;
	326
	327	return 0;
	328	}
	329
	330	void __init pxa27x_init_irq(void)
	331	{
b9e25ace	332	pxa_init_irq(34, pxa27x_set_wake);
ddd244dd	333	pxa_init_gpio(121, pxa27x_set_wake);
c95530c7	334	}
c95530c7	335
1da177e4 LT	336	/*
	337	* device registration specific to PXA27x.
	338	*/
9ba63c4f	339	void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
b7a36701	340	{
bc3a5959 PZ	341	local_irq_disable();
	342	PCFR \|= PCFR_PI2CEN;
	343	local_irq_enable();
14758220	344	pxa_register_device(&pxa27x_device_i2c_power, info);
b7a36701 MR	345	}
b7a36701 MR	346
1da177e4	347	static struct platform_device *devices[] __initdata = {
7a857620	348	&pxa27x_device_udc,
e09d02e1 EM	349	&pxa_device_ffuart,
	350	&pxa_device_btuart,
	351	&pxa_device_stuart,
e09d02e1	352	&pxa_device_i2s,
72493146	353	&sa1100_device_rtc,
e09d02e1	354	&pxa_device_rtc,
d8e0db11	355	&pxa27x_device_ssp1,
	356	&pxa27x_device_ssp2,
	357	&pxa27x_device_ssp3,
75540c1a	358	&pxa27x_device_pwm0,
75540c1a	359	&pxa27x_device_pwm1,
1da177e4 LT	360	};
1da177e4 LT	361
c0165504	362	static struct sys_device pxa27x_sysdev[] = {
c0165504	363	{
c0165504	364	.cls = &pxa_irq_sysclass,
5a3d9651 EM	365	}, {
5a3d9651 EM	366	.cls = &pxa2xx_mfp_sysclass,
16dfdbf0	367	}, {
16dfdbf0	368	.cls = &pxa_gpio_sysclass,
c0165504	369	},
	370	};
	371
1da177e4 LT	372	static int __init pxa27x_init(void)
1da177e4 LT	373	{
c0165504	374	int i, ret = 0;
c0165504	375
e176bb05	376	if (cpu_is_pxa27x()) {
04fef228 EM	377
	378	reset_status = RCSR;
	379
8c3abc7d	380	clks_register(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));
a6dba20c	381
f53f066c EM	382	if ((ret = pxa_init_dma(32)))
f53f066c EM	383	return ret;
f79299ca	384
711be5cc	385	pxa27x_init_pm();
f79299ca	386
c0165504	387	for (i = 0; i < ARRAY_SIZE(pxa27x_sysdev); i++) {
	388	ret = sysdev_register(&pxa27x_sysdev[i]);
	389	if (ret)
	390	pr_err("failed to register sysdev[%d]\n", i);
	391	}
	392
e176bb05 RK	393	ret = platform_add_devices(devices, ARRAY_SIZE(devices));
e176bb05 RK	394	}
c0165504	395
e176bb05	396	return ret;
1da177e4 LT	397	}
1da177e4 LT	398
1c104e0e	399	postcore_initcall(pxa27x_init);