[deliverable/linux.git] / arch / arm / mach-pxa / pxa27x.c

/*
 *  linux/arch/arm/mach-pxa/pxa27x.c
 *
 *  Author:	Nicolas Pitre
 *  Created:	Nov 05, 2002
 *  Copyright:	MontaVista Software Inc.
 *
 * Code specific to PXA27x aka Bulverde.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/suspend.h>
#include <linux/platform_device.h>
#include <linux/sysdev.h>

#include <mach/hardware.h>
#include <asm/irq.h>
#include <mach/irqs.h>
#include <mach/pxa-regs.h>
#include <mach/pxa2xx-regs.h>
#include <mach/mfp-pxa27x.h>
#include <mach/reset.h>
#include <mach/ohci.h>
#include <mach/pm.h>
#include <mach/dma.h>
#include <mach/i2c.h>

#include "generic.h"
#include "devices.h"
#include "clock.h"

/* Crystal clock: 13MHz */
#define BASE_CLK	13000000

/*
 * Get the clock frequency as reflected by CCSR and the turbo flag.
 * We assume these values have been applied via a fcs.
 * If info is not 0 we also display the current settings.
 */
unsigned int pxa27x_get_clk_frequency_khz(int info)
{
	unsigned long ccsr, clkcfg;
	unsigned int l, L, m, M, n2, N, S;
       	int cccr_a, t, ht, b;

	ccsr = CCSR;
	cccr_a = CCCR & (1 << 25);

	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	t  = clkcfg & (1 << 0);
	ht = clkcfg & (1 << 2);
	b  = clkcfg & (1 << 3);

	l  = ccsr & 0x1f;
	n2 = (ccsr>>7) & 0xf;
	m  = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;

	L  = l * BASE_CLK;
	N  = (L * n2) / 2;
	M  = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	S  = (b) ? L : (L/2);

	if (info) {
		printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
			L / 1000000, (L % 1000000) / 10000, l );
		printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
			N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
			(t) ? "" : "in" );
		printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
			M / 1000000, (M % 1000000) / 10000, m );
		printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
			S / 1000000, (S % 1000000) / 10000 );
	}

	return (t) ? (N/1000) : (L/1000);
}

/*
 * Return the current mem clock frequency in units of 10kHz as
 * reflected by CCCR[A], B, and L
 */
unsigned int pxa27x_get_memclk_frequency_10khz(void)
{
	unsigned long ccsr, clkcfg;
	unsigned int l, L, m, M;
       	int cccr_a, b;

	ccsr = CCSR;
	cccr_a = CCCR & (1 << 25);

	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	b = clkcfg & (1 << 3);

	l = ccsr & 0x1f;
	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;

	L = l * BASE_CLK;
	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));

	return (M / 10000);
}

/*
 * Return the current LCD clock frequency in units of 10kHz as
 */
static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
{
	unsigned long ccsr;
	unsigned int l, L, k, K;

	ccsr = CCSR;

	l = ccsr & 0x1f;
	k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;

	L = l * BASE_CLK;
	K = L / k;

	return (K / 10000);
}

static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
{
	return pxa27x_get_lcdclk_frequency_10khz() * 10000;
}

static const struct clkops clk_pxa27x_lcd_ops = {
	.enable		= clk_cken_enable,
	.disable	= clk_cken_disable,
	.getrate	= clk_pxa27x_lcd_getrate,
};

static struct clk pxa27x_clks[] = {
	INIT_CK("LCDCLK", LCD,    &clk_pxa27x_lcd_ops, &pxa_device_fb.dev),
	INIT_CK("CAMCLK", CAMERA, &clk_pxa27x_lcd_ops, NULL),

	INIT_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
	INIT_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
	INIT_CKEN("UARTCLK", STUART, 14857000, 1, NULL),

	INIT_CKEN("I2SCLK",  I2S,  14682000, 0, &pxa_device_i2s.dev),
	INIT_CKEN("I2CCLK",  I2C,  32842000, 0, &pxa_device_i2c.dev),
	INIT_CKEN("UDCCLK",  USB,  48000000, 5, &pxa27x_device_udc.dev),
	INIT_CKEN("MMCCLK",  MMC,  19500000, 0, &pxa_device_mci.dev),
	INIT_CKEN("FICPCLK", FICP, 48000000, 0, &pxa_device_ficp.dev),

	INIT_CKEN("USBCLK", USBHOST, 48000000, 0, &pxa27x_device_ohci.dev),
	INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev),
	INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, &pxa27x_device_keypad.dev),

	INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
	INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
	INIT_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
	INIT_CKEN("PWMCLK", PWM0, 13000000, 0, &pxa27x_device_pwm0.dev),
	INIT_CKEN("PWMCLK", PWM1, 13000000, 0, &pxa27x_device_pwm1.dev),

	INIT_CKEN("AC97CLK",     AC97,     24576000, 0, NULL),
	INIT_CKEN("AC97CONFCLK", AC97CONF, 24576000, 0, NULL),

	/*
	INIT_CKEN("MSLCLK",  MSL,  48000000, 0, NULL),
	INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL),
	INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL),
	INIT_CKEN("IMCLK",   IM,   0, 0, NULL),
	INIT_CKEN("MEMCLK",  MEMC, 0, 0, NULL),
	*/
};

#ifdef CONFIG_PM

#define SAVE(x)		sleep_save[SLEEP_SAVE_##x] = x
#define RESTORE(x)	x = sleep_save[SLEEP_SAVE_##x]

/*
 * List of global PXA peripheral registers to preserve.
 * More ones like CP and general purpose register values are preserved
 * with the stack pointer in sleep.S.
 */
enum {
	SLEEP_SAVE_PSTR,
	SLEEP_SAVE_CKEN,
	SLEEP_SAVE_MDREFR,
	SLEEP_SAVE_PCFR,
	SLEEP_SAVE_COUNT
};

void pxa27x_cpu_pm_save(unsigned long *sleep_save)
{
	SAVE(MDREFR);
	SAVE(PCFR);

	SAVE(CKEN);
	SAVE(PSTR);
}

void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
{
	/* ensure not to come back here if it wasn't intended */
	PSPR = 0;

	RESTORE(MDREFR);
	RESTORE(PCFR);

	PSSR = PSSR_RDH | PSSR_PH;

	RESTORE(CKEN);
	RESTORE(PSTR);
}

void pxa27x_cpu_pm_enter(suspend_state_t state)
{
	extern void pxa_cpu_standby(void);

	/* ensure voltage-change sequencer not initiated, which hangs */
	PCFR &= ~PCFR_FVC;

	/* Clear edge-detect status register. */
	PEDR = 0xDF12FE1B;

	/* Clear reset status */
	RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;

	switch (state) {
	case PM_SUSPEND_STANDBY:
		pxa_cpu_standby();
		break;
	case PM_SUSPEND_MEM:
		/* set resume return address */
		PSPR = virt_to_phys(pxa_cpu_resume);
		pxa27x_cpu_suspend(PWRMODE_SLEEP);
		break;
	}
}

static int pxa27x_cpu_pm_valid(suspend_state_t state)
{
	return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
}

static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
	.save_count	= SLEEP_SAVE_COUNT,
	.save		= pxa27x_cpu_pm_save,
	.restore	= pxa27x_cpu_pm_restore,
	.valid		= pxa27x_cpu_pm_valid,
	.enter		= pxa27x_cpu_pm_enter,
};

static void __init pxa27x_init_pm(void)
{
	pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
}
#else
static inline void pxa27x_init_pm(void) {}
#endif

/* PXA27x:  Various gpios can issue wakeup events.  This logic only
 * handles the simple cases, not the WEMUX2 and WEMUX3 options
 */
static int pxa27x_set_wake(unsigned int irq, unsigned int on)
{
	int gpio = IRQ_TO_GPIO(irq);
	uint32_t mask;

	if (gpio >= 0 && gpio < 128)
		return gpio_set_wake(gpio, on);

	if (irq == IRQ_KEYPAD)
		return keypad_set_wake(on);

	switch (irq) {
	case IRQ_RTCAlrm:
		mask = PWER_RTC;
		break;
	case IRQ_USB:
		mask = 1u << 26;
		break;
	default:
		return -EINVAL;
	}

	if (on)
		PWER |= mask;
	else
		PWER &=~mask;

	return 0;
}

void __init pxa27x_init_irq(void)
{
	pxa_init_irq(34, pxa27x_set_wake);
	pxa_init_gpio(128, pxa27x_set_wake);
}

/*
 * device registration specific to PXA27x.
 */

static struct resource i2c_power_resources[] = {
	{
		.start	= 0x40f00180,
		.end	= 0x40f001a3,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_PWRI2C,
		.end	= IRQ_PWRI2C,
		.flags	= IORESOURCE_IRQ,
	},
};

struct platform_device pxa27x_device_i2c_power = {
	.name		= "pxa2xx-i2c",
	.id		= 1,
	.resource	= i2c_power_resources,
	.num_resources	= ARRAY_SIZE(i2c_power_resources),
};

void __init pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info)
{
	local_irq_disable();
	PCFR |= PCFR_PI2CEN;
	local_irq_enable();
	pxa27x_device_i2c_power.dev.platform_data = info;
}

static struct platform_device *devices[] __initdata = {
	&pxa27x_device_udc,
	&pxa_device_ffuart,
	&pxa_device_btuart,
	&pxa_device_stuart,
	&pxa_device_i2s,
	&pxa_device_rtc,
	&pxa27x_device_i2c_power,
	&pxa27x_device_ssp1,
	&pxa27x_device_ssp2,
	&pxa27x_device_ssp3,
	&pxa27x_device_pwm0,
	&pxa27x_device_pwm1,
};

static struct sys_device pxa27x_sysdev[] = {
	{
		.cls	= &pxa_irq_sysclass,
	}, {
		.cls	= &pxa2xx_mfp_sysclass,
	}, {
		.cls	= &pxa_gpio_sysclass,
	},
};

static int __init pxa27x_init(void)
{
	int i, ret = 0;

	if (cpu_is_pxa27x()) {

		reset_status = RCSR;

		clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks));

		if ((ret = pxa_init_dma(32)))
			return ret;

		pxa27x_init_pm();

		for (i = 0; i < ARRAY_SIZE(pxa27x_sysdev); i++) {
			ret = sysdev_register(&pxa27x_sysdev[i]);
			if (ret)
				pr_err("failed to register sysdev[%d]\n", i);
		}

		ret = platform_add_devices(devices, ARRAY_SIZE(devices));
	}

	return ret;
}

postcore_initcall(pxa27x_init);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-pxa/pxa27x.c
	3	*
	4	* Author: Nicolas Pitre
	5	* Created: Nov 05, 2002
	6	* Copyright: MontaVista Software Inc.
	7	*
	8	* Code specific to PXA27x aka Bulverde.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
1da177e4 LT	14	#include <linux/module.h>
	15	#include <linux/kernel.h>
	16	#include <linux/init.h>
95d9ffbe	17	#include <linux/suspend.h>
d052d1be	18	#include <linux/platform_device.h>
c0165504	19	#include <linux/sysdev.h>
1da177e4	20
a09e64fb	21	#include <mach/hardware.h>
1da177e4	22	#include <asm/irq.h>
a09e64fb RK	23	#include <mach/irqs.h>
	24	#include <mach/pxa-regs.h>
	25	#include <mach/pxa2xx-regs.h>
	26	#include <mach/mfp-pxa27x.h>
afd2fc02	27	#include <mach/reset.h>
a09e64fb RK	28	#include <mach/ohci.h>
	29	#include <mach/pm.h>
	30	#include <mach/dma.h>
	31	#include <mach/i2c.h>
1da177e4 LT	32
1da177e4 LT	33	#include "generic.h"
46c41e62	34	#include "devices.h"
a6dba20c	35	#include "clock.h"
1da177e4 LT	36
	37	/* Crystal clock: 13MHz */
	38	#define BASE_CLK 13000000
	39
	40	/*
	41	* Get the clock frequency as reflected by CCSR and the turbo flag.
	42	* We assume these values have been applied via a fcs.
	43	* If info is not 0 we also display the current settings.
	44	*/
15a40333	45	unsigned int pxa27x_get_clk_frequency_khz(int info)
1da177e4 LT	46	{
	47	unsigned long ccsr, clkcfg;
	48	unsigned int l, L, m, M, n2, N, S;
	49	int cccr_a, t, ht, b;
	50
	51	ccsr = CCSR;
	52	cccr_a = CCCR & (1 << 25);
	53
	54	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	55	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
afe5df20	56	t = clkcfg & (1 << 0);
1da177e4 LT	57	ht = clkcfg & (1 << 2);
	58	b = clkcfg & (1 << 3);
	59
	60	l = ccsr & 0x1f;
	61	n2 = (ccsr>>7) & 0xf;
	62	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
	63
	64	L = l * BASE_CLK;
	65	N = (L * n2) / 2;
	66	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	67	S = (b) ? L : (L/2);
	68
	69	if (info) {
	70	printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
	71	L / 1000000, (L % 1000000) / 10000, l );
	72	printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
	73	N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
	74	(t) ? "" : "in" );
	75	printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
	76	M / 1000000, (M % 1000000) / 10000, m );
	77	printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
	78	S / 1000000, (S % 1000000) / 10000 );
	79	}
	80
	81	return (t) ? (N/1000) : (L/1000);
	82	}
	83
	84	/*
	85	* Return the current mem clock frequency in units of 10kHz as
	86	* reflected by CCCR[A], B, and L
	87	*/
15a40333	88	unsigned int pxa27x_get_memclk_frequency_10khz(void)
1da177e4 LT	89	{
	90	unsigned long ccsr, clkcfg;
	91	unsigned int l, L, m, M;
	92	int cccr_a, b;
	93
	94	ccsr = CCSR;
	95	cccr_a = CCCR & (1 << 25);
	96
	97	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	98	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	99	b = clkcfg & (1 << 3);
	100
	101	l = ccsr & 0x1f;
	102	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
	103
	104	L = l * BASE_CLK;
	105	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	106
	107	return (M / 10000);
	108	}
	109
	110	/*
	111	* Return the current LCD clock frequency in units of 10kHz as
	112	*/
a88a447d	113	static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
1da177e4 LT	114	{
	115	unsigned long ccsr;
	116	unsigned int l, L, k, K;
	117
	118	ccsr = CCSR;
	119
	120	l = ccsr & 0x1f;
	121	k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
	122
	123	L = l * BASE_CLK;
	124	K = L / k;
	125
	126	return (K / 10000);
	127	}
	128
a6dba20c RK	129	static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
	130	{
	131	return pxa27x_get_lcdclk_frequency_10khz() * 10000;
	132	}
	133
	134	static const struct clkops clk_pxa27x_lcd_ops = {
	135	.enable = clk_cken_enable,
	136	.disable = clk_cken_disable,
	137	.getrate = clk_pxa27x_lcd_getrate,
	138	};
	139
	140	static struct clk pxa27x_clks[] = {
	141	INIT_CK("LCDCLK", LCD, &clk_pxa27x_lcd_ops, &pxa_device_fb.dev),
	142	INIT_CK("CAMCLK", CAMERA, &clk_pxa27x_lcd_ops, NULL),
	143
a6dba20c RK	144	INIT_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
a6dba20c RK	145	INIT_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
435b6e94	146	INIT_CKEN("UARTCLK", STUART, 14857000, 1, NULL),
a6dba20c RK	147
	148	INIT_CKEN("I2SCLK", I2S, 14682000, 0, &pxa_device_i2s.dev),
	149	INIT_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev),
7a857620	150	INIT_CKEN("UDCCLK", USB, 48000000, 5, &pxa27x_device_udc.dev),
a6dba20c RK	151	INIT_CKEN("MMCCLK", MMC, 19500000, 0, &pxa_device_mci.dev),
	152	INIT_CKEN("FICPCLK", FICP, 48000000, 0, &pxa_device_ficp.dev),
	153
8854cb49	154	INIT_CKEN("USBCLK", USBHOST, 48000000, 0, &pxa27x_device_ohci.dev),
a6dba20c	155	INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev),
37320980	156	INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, &pxa27x_device_keypad.dev),
a6dba20c	157
d8e0db11	158	INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
	159	INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
	160	INIT_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
75540c1a	161	INIT_CKEN("PWMCLK", PWM0, 13000000, 0, &pxa27x_device_pwm0.dev),
75540c1a	162	INIT_CKEN("PWMCLK", PWM1, 13000000, 0, &pxa27x_device_pwm1.dev),
d8e0db11	163
27b98a67 MB	164	INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL),
	165	INIT_CKEN("AC97CONFCLK", AC97CONF, 24576000, 0, NULL),
	166
a6dba20c	167	/*
a6dba20c RK	168	INIT_CKEN("MSLCLK", MSL, 48000000, 0, NULL),
	169	INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL),
	170	INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL),
	171	INIT_CKEN("IMCLK", IM, 0, 0, NULL),
	172	INIT_CKEN("MEMCLK", MEMC, 0, 0, NULL),
	173	*/
	174	};
	175
a8fa3f0c NP	176	#ifdef CONFIG_PM
a8fa3f0c NP	177
711be5cc EM	178	#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
	179	#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
	180
711be5cc EM	181	/*
	182	* List of global PXA peripheral registers to preserve.
	183	* More ones like CP and general purpose register values are preserved
	184	* with the stack pointer in sleep.S.
	185	*/
5a3d9651	186	enum {
711be5cc	187	SLEEP_SAVE_PSTR,
711be5cc	188	SLEEP_SAVE_CKEN,
711be5cc	189	SLEEP_SAVE_MDREFR,
5a3d9651	190	SLEEP_SAVE_PCFR,
649de51b	191	SLEEP_SAVE_COUNT
711be5cc EM	192	};
	193
	194	void pxa27x_cpu_pm_save(unsigned long *sleep_save)
	195	{
711be5cc	196	SAVE(MDREFR);
5a3d9651	197	SAVE(PCFR);
711be5cc	198
711be5cc EM	199	SAVE(CKEN);
711be5cc EM	200	SAVE(PSTR);
711be5cc EM	201	}
	202
	203	void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
	204	{
	205	/* ensure not to come back here if it wasn't intended */
	206	PSPR = 0;
	207
711be5cc	208	RESTORE(MDREFR);
5a3d9651	209	RESTORE(PCFR);
711be5cc EM	210
	211	PSSR = PSSR_RDH \| PSSR_PH;
	212
	213	RESTORE(CKEN);
711be5cc EM	214	RESTORE(PSTR);
	215	}
	216
	217	void pxa27x_cpu_pm_enter(suspend_state_t state)
8775420d TP	218	{
8775420d TP	219	extern void pxa_cpu_standby(void);
8775420d	220
8775420d TP	221	/* ensure voltage-change sequencer not initiated, which hangs */
	222	PCFR &= ~PCFR_FVC;
	223
	224	/* Clear edge-detect status register. */
	225	PEDR = 0xDF12FE1B;
	226
dc38e2ad RK	227	/* Clear reset status */
	228	RCSR = RCSR_HWR \| RCSR_WDR \| RCSR_SMR \| RCSR_GPR;
	229
8775420d	230	switch (state) {
26705ca4 TP	231	case PM_SUSPEND_STANDBY:
	232	pxa_cpu_standby();
	233	break;
8775420d TP	234	case PM_SUSPEND_MEM:
	235	/* set resume return address */
	236	PSPR = virt_to_phys(pxa_cpu_resume);
b750a093	237	pxa27x_cpu_suspend(PWRMODE_SLEEP);
8775420d TP	238	break;
	239	}
	240	}
1da177e4	241
711be5cc	242	static int pxa27x_cpu_pm_valid(suspend_state_t state)
88dfe98c RK	243	{
	244	return state == PM_SUSPEND_MEM \|\| state == PM_SUSPEND_STANDBY;
	245	}
	246
711be5cc	247	static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
649de51b	248	.save_count = SLEEP_SAVE_COUNT,
711be5cc EM	249	.save = pxa27x_cpu_pm_save,
	250	.restore = pxa27x_cpu_pm_restore,
	251	.valid = pxa27x_cpu_pm_valid,
	252	.enter = pxa27x_cpu_pm_enter,
e176bb05	253	};
711be5cc EM	254
	255	static void __init pxa27x_init_pm(void)
	256	{
	257	pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
	258	}
f79299ca	259	#else
f79299ca	260	static inline void pxa27x_init_pm(void) {}
a8fa3f0c NP	261	#endif
a8fa3f0c NP	262
c95530c7	263	/* PXA27x: Various gpios can issue wakeup events. This logic only
	264	* handles the simple cases, not the WEMUX2 and WEMUX3 options
	265	*/
c95530c7	266	static int pxa27x_set_wake(unsigned int irq, unsigned int on)
	267	{
	268	int gpio = IRQ_TO_GPIO(irq);
	269	uint32_t mask;
	270
c0a596d6	271	if (gpio >= 0 && gpio < 128)
c0a596d6	272	return gpio_set_wake(gpio, on);
c95530c7	273
c0a596d6	274	if (irq == IRQ_KEYPAD)
c0a596d6	275	return keypad_set_wake(on);
c95530c7	276
	277	switch (irq) {
	278	case IRQ_RTCAlrm:
	279	mask = PWER_RTC;
	280	break;
	281	case IRQ_USB:
	282	mask = 1u << 26;
	283	break;
	284	default:
	285	return -EINVAL;
	286	}
	287
c95530c7	288	if (on)
	289	PWER \|= mask;
	290	else
	291	PWER &=~mask;
	292
	293	return 0;
	294	}
	295
	296	void __init pxa27x_init_irq(void)
	297	{
b9e25ace	298	pxa_init_irq(34, pxa27x_set_wake);
b9e25ace	299	pxa_init_gpio(128, pxa27x_set_wake);
c95530c7	300	}
c95530c7	301
1da177e4 LT	302	/*
	303	* device registration specific to PXA27x.
	304	*/
	305
34f3231f RK	306	static struct resource i2c_power_resources[] = {
	307	{
	308	.start = 0x40f00180,
	309	.end = 0x40f001a3,
	310	.flags = IORESOURCE_MEM,
	311	}, {
	312	.start = IRQ_PWRI2C,
	313	.end = IRQ_PWRI2C,
	314	.flags = IORESOURCE_IRQ,
	315	},
	316	};
	317
00dc4f94	318	struct platform_device pxa27x_device_i2c_power = {
34f3231f RK	319	.name = "pxa2xx-i2c",
	320	.id = 1,
	321	.resource = i2c_power_resources,
	322	.num_resources = ARRAY_SIZE(i2c_power_resources),
	323	};
	324
b7a36701 MR	325	void __init pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info)
b7a36701 MR	326	{
bc3a5959 PZ	327	local_irq_disable();
	328	PCFR \|= PCFR_PI2CEN;
	329	local_irq_enable();
b7a36701 MR	330	pxa27x_device_i2c_power.dev.platform_data = info;
	331	}
	332
1da177e4	333	static struct platform_device *devices[] __initdata = {
7a857620	334	&pxa27x_device_udc,
e09d02e1 EM	335	&pxa_device_ffuart,
	336	&pxa_device_btuart,
	337	&pxa_device_stuart,
e09d02e1	338	&pxa_device_i2s,
e09d02e1 EM	339	&pxa_device_rtc,
e09d02e1 EM	340	&pxa27x_device_i2c_power,
d8e0db11	341	&pxa27x_device_ssp1,
	342	&pxa27x_device_ssp2,
	343	&pxa27x_device_ssp3,
75540c1a	344	&pxa27x_device_pwm0,
75540c1a	345	&pxa27x_device_pwm1,
1da177e4 LT	346	};
1da177e4 LT	347
c0165504	348	static struct sys_device pxa27x_sysdev[] = {
c0165504	349	{
c0165504	350	.cls = &pxa_irq_sysclass,
5a3d9651 EM	351	}, {
5a3d9651 EM	352	.cls = &pxa2xx_mfp_sysclass,
16dfdbf0	353	}, {
16dfdbf0	354	.cls = &pxa_gpio_sysclass,
c0165504	355	},
	356	};
	357
1da177e4 LT	358	static int __init pxa27x_init(void)
1da177e4 LT	359	{
c0165504	360	int i, ret = 0;
c0165504	361
e176bb05	362	if (cpu_is_pxa27x()) {
04fef228 EM	363
	364	reset_status = RCSR;
	365
a6dba20c RK	366	clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks));
a6dba20c RK	367
f53f066c EM	368	if ((ret = pxa_init_dma(32)))
f53f066c EM	369	return ret;
f79299ca	370
711be5cc	371	pxa27x_init_pm();
f79299ca	372
c0165504	373	for (i = 0; i < ARRAY_SIZE(pxa27x_sysdev); i++) {
	374	ret = sysdev_register(&pxa27x_sysdev[i]);
	375	if (ret)
	376	pr_err("failed to register sysdev[%d]\n", i);
	377	}
	378
e176bb05 RK	379	ret = platform_add_devices(devices, ARRAY_SIZE(devices));
e176bb05 RK	380	}
c0165504	381
e176bb05	382	return ret;
1da177e4 LT	383	}
1da177e4 LT	384
1c104e0e	385	postcore_initcall(pxa27x_init);