Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-pxa/pxa27x.c | |
3 | * | |
4 | * Author: Nicolas Pitre | |
5 | * Created: Nov 05, 2002 | |
6 | * Copyright: MontaVista Software Inc. | |
7 | * | |
8 | * Code specific to PXA27x aka Bulverde. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
1da177e4 LT |
14 | #include <linux/module.h> |
15 | #include <linux/kernel.h> | |
16 | #include <linux/init.h> | |
95d9ffbe | 17 | #include <linux/suspend.h> |
d052d1be | 18 | #include <linux/platform_device.h> |
c0165504 | 19 | #include <linux/sysdev.h> |
1da177e4 | 20 | |
a09e64fb | 21 | #include <mach/hardware.h> |
1da177e4 | 22 | #include <asm/irq.h> |
a09e64fb RK |
23 | #include <mach/irqs.h> |
24 | #include <mach/pxa-regs.h> | |
25 | #include <mach/pxa2xx-regs.h> | |
26 | #include <mach/mfp-pxa27x.h> | |
afd2fc02 | 27 | #include <mach/reset.h> |
a09e64fb RK |
28 | #include <mach/ohci.h> |
29 | #include <mach/pm.h> | |
30 | #include <mach/dma.h> | |
31 | #include <mach/i2c.h> | |
1da177e4 LT |
32 | |
33 | #include "generic.h" | |
46c41e62 | 34 | #include "devices.h" |
a6dba20c | 35 | #include "clock.h" |
1da177e4 | 36 | |
0cb0b0d3 EM |
37 | void pxa27x_clear_otgph(void) |
38 | { | |
39 | if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH)) | |
40 | PSSR |= PSSR_OTGPH; | |
41 | } | |
42 | EXPORT_SYMBOL(pxa27x_clear_otgph); | |
43 | ||
1da177e4 LT |
44 | /* Crystal clock: 13MHz */ |
45 | #define BASE_CLK 13000000 | |
46 | ||
47 | /* | |
48 | * Get the clock frequency as reflected by CCSR and the turbo flag. | |
49 | * We assume these values have been applied via a fcs. | |
50 | * If info is not 0 we also display the current settings. | |
51 | */ | |
15a40333 | 52 | unsigned int pxa27x_get_clk_frequency_khz(int info) |
1da177e4 LT |
53 | { |
54 | unsigned long ccsr, clkcfg; | |
55 | unsigned int l, L, m, M, n2, N, S; | |
56 | int cccr_a, t, ht, b; | |
57 | ||
58 | ccsr = CCSR; | |
59 | cccr_a = CCCR & (1 << 25); | |
60 | ||
61 | /* Read clkcfg register: it has turbo, b, half-turbo (and f) */ | |
62 | asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) ); | |
afe5df20 | 63 | t = clkcfg & (1 << 0); |
1da177e4 LT |
64 | ht = clkcfg & (1 << 2); |
65 | b = clkcfg & (1 << 3); | |
66 | ||
67 | l = ccsr & 0x1f; | |
68 | n2 = (ccsr>>7) & 0xf; | |
69 | m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4; | |
70 | ||
71 | L = l * BASE_CLK; | |
72 | N = (L * n2) / 2; | |
73 | M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2)); | |
74 | S = (b) ? L : (L/2); | |
75 | ||
76 | if (info) { | |
77 | printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n", | |
78 | L / 1000000, (L % 1000000) / 10000, l ); | |
79 | printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n", | |
80 | N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5, | |
81 | (t) ? "" : "in" ); | |
82 | printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n", | |
83 | M / 1000000, (M % 1000000) / 10000, m ); | |
84 | printk( KERN_INFO "System bus clock: %d.%02dMHz \n", | |
85 | S / 1000000, (S % 1000000) / 10000 ); | |
86 | } | |
87 | ||
88 | return (t) ? (N/1000) : (L/1000); | |
89 | } | |
90 | ||
91 | /* | |
92 | * Return the current mem clock frequency in units of 10kHz as | |
93 | * reflected by CCCR[A], B, and L | |
94 | */ | |
15a40333 | 95 | unsigned int pxa27x_get_memclk_frequency_10khz(void) |
1da177e4 LT |
96 | { |
97 | unsigned long ccsr, clkcfg; | |
98 | unsigned int l, L, m, M; | |
99 | int cccr_a, b; | |
100 | ||
101 | ccsr = CCSR; | |
102 | cccr_a = CCCR & (1 << 25); | |
103 | ||
104 | /* Read clkcfg register: it has turbo, b, half-turbo (and f) */ | |
105 | asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) ); | |
106 | b = clkcfg & (1 << 3); | |
107 | ||
108 | l = ccsr & 0x1f; | |
109 | m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4; | |
110 | ||
111 | L = l * BASE_CLK; | |
112 | M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2)); | |
113 | ||
114 | return (M / 10000); | |
115 | } | |
116 | ||
117 | /* | |
118 | * Return the current LCD clock frequency in units of 10kHz as | |
119 | */ | |
a88a447d | 120 | static unsigned int pxa27x_get_lcdclk_frequency_10khz(void) |
1da177e4 LT |
121 | { |
122 | unsigned long ccsr; | |
123 | unsigned int l, L, k, K; | |
124 | ||
125 | ccsr = CCSR; | |
126 | ||
127 | l = ccsr & 0x1f; | |
128 | k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4; | |
129 | ||
130 | L = l * BASE_CLK; | |
131 | K = L / k; | |
132 | ||
133 | return (K / 10000); | |
134 | } | |
135 | ||
a6dba20c RK |
136 | static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk) |
137 | { | |
138 | return pxa27x_get_lcdclk_frequency_10khz() * 10000; | |
139 | } | |
140 | ||
141 | static const struct clkops clk_pxa27x_lcd_ops = { | |
142 | .enable = clk_cken_enable, | |
143 | .disable = clk_cken_disable, | |
144 | .getrate = clk_pxa27x_lcd_getrate, | |
145 | }; | |
146 | ||
147 | static struct clk pxa27x_clks[] = { | |
148 | INIT_CK("LCDCLK", LCD, &clk_pxa27x_lcd_ops, &pxa_device_fb.dev), | |
149 | INIT_CK("CAMCLK", CAMERA, &clk_pxa27x_lcd_ops, NULL), | |
150 | ||
a6dba20c RK |
151 | INIT_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), |
152 | INIT_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), | |
435b6e94 | 153 | INIT_CKEN("UARTCLK", STUART, 14857000, 1, NULL), |
a6dba20c RK |
154 | |
155 | INIT_CKEN("I2SCLK", I2S, 14682000, 0, &pxa_device_i2s.dev), | |
156 | INIT_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), | |
7a857620 | 157 | INIT_CKEN("UDCCLK", USB, 48000000, 5, &pxa27x_device_udc.dev), |
a6dba20c RK |
158 | INIT_CKEN("MMCCLK", MMC, 19500000, 0, &pxa_device_mci.dev), |
159 | INIT_CKEN("FICPCLK", FICP, 48000000, 0, &pxa_device_ficp.dev), | |
160 | ||
8854cb49 | 161 | INIT_CKEN("USBCLK", USBHOST, 48000000, 0, &pxa27x_device_ohci.dev), |
a6dba20c | 162 | INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev), |
37320980 | 163 | INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, &pxa27x_device_keypad.dev), |
a6dba20c | 164 | |
d8e0db11 | 165 | INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), |
166 | INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), | |
167 | INIT_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev), | |
75540c1a | 168 | INIT_CKEN("PWMCLK", PWM0, 13000000, 0, &pxa27x_device_pwm0.dev), |
169 | INIT_CKEN("PWMCLK", PWM1, 13000000, 0, &pxa27x_device_pwm1.dev), | |
d8e0db11 | 170 | |
27b98a67 MB |
171 | INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL), |
172 | INIT_CKEN("AC97CONFCLK", AC97CONF, 24576000, 0, NULL), | |
173 | ||
a6dba20c | 174 | /* |
a6dba20c RK |
175 | INIT_CKEN("MSLCLK", MSL, 48000000, 0, NULL), |
176 | INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL), | |
177 | INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL), | |
178 | INIT_CKEN("IMCLK", IM, 0, 0, NULL), | |
179 | INIT_CKEN("MEMCLK", MEMC, 0, 0, NULL), | |
180 | */ | |
181 | }; | |
182 | ||
a8fa3f0c NP |
183 | #ifdef CONFIG_PM |
184 | ||
711be5cc EM |
185 | #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x |
186 | #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] | |
187 | ||
711be5cc EM |
188 | /* |
189 | * List of global PXA peripheral registers to preserve. | |
190 | * More ones like CP and general purpose register values are preserved | |
191 | * with the stack pointer in sleep.S. | |
192 | */ | |
5a3d9651 | 193 | enum { |
711be5cc | 194 | SLEEP_SAVE_PSTR, |
711be5cc | 195 | SLEEP_SAVE_CKEN, |
711be5cc | 196 | SLEEP_SAVE_MDREFR, |
5a3d9651 | 197 | SLEEP_SAVE_PCFR, |
649de51b | 198 | SLEEP_SAVE_COUNT |
711be5cc EM |
199 | }; |
200 | ||
201 | void pxa27x_cpu_pm_save(unsigned long *sleep_save) | |
202 | { | |
711be5cc | 203 | SAVE(MDREFR); |
5a3d9651 | 204 | SAVE(PCFR); |
711be5cc | 205 | |
711be5cc EM |
206 | SAVE(CKEN); |
207 | SAVE(PSTR); | |
711be5cc EM |
208 | } |
209 | ||
210 | void pxa27x_cpu_pm_restore(unsigned long *sleep_save) | |
211 | { | |
711be5cc | 212 | RESTORE(MDREFR); |
5a3d9651 | 213 | RESTORE(PCFR); |
711be5cc EM |
214 | |
215 | PSSR = PSSR_RDH | PSSR_PH; | |
216 | ||
217 | RESTORE(CKEN); | |
711be5cc EM |
218 | RESTORE(PSTR); |
219 | } | |
220 | ||
221 | void pxa27x_cpu_pm_enter(suspend_state_t state) | |
8775420d TP |
222 | { |
223 | extern void pxa_cpu_standby(void); | |
8775420d | 224 | |
8775420d TP |
225 | /* ensure voltage-change sequencer not initiated, which hangs */ |
226 | PCFR &= ~PCFR_FVC; | |
227 | ||
228 | /* Clear edge-detect status register. */ | |
229 | PEDR = 0xDF12FE1B; | |
230 | ||
dc38e2ad RK |
231 | /* Clear reset status */ |
232 | RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR; | |
233 | ||
8775420d | 234 | switch (state) { |
26705ca4 TP |
235 | case PM_SUSPEND_STANDBY: |
236 | pxa_cpu_standby(); | |
237 | break; | |
8775420d | 238 | case PM_SUSPEND_MEM: |
b750a093 | 239 | pxa27x_cpu_suspend(PWRMODE_SLEEP); |
8775420d TP |
240 | break; |
241 | } | |
242 | } | |
1da177e4 | 243 | |
711be5cc | 244 | static int pxa27x_cpu_pm_valid(suspend_state_t state) |
88dfe98c RK |
245 | { |
246 | return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; | |
247 | } | |
248 | ||
4104980a RK |
249 | static int pxa27x_cpu_pm_prepare(void) |
250 | { | |
251 | /* set resume return address */ | |
252 | PSPR = virt_to_phys(pxa_cpu_resume); | |
253 | return 0; | |
254 | } | |
255 | ||
256 | static void pxa27x_cpu_pm_finish(void) | |
257 | { | |
258 | /* ensure not to come back here if it wasn't intended */ | |
259 | PSPR = 0; | |
260 | } | |
261 | ||
711be5cc | 262 | static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = { |
649de51b | 263 | .save_count = SLEEP_SAVE_COUNT, |
711be5cc EM |
264 | .save = pxa27x_cpu_pm_save, |
265 | .restore = pxa27x_cpu_pm_restore, | |
266 | .valid = pxa27x_cpu_pm_valid, | |
267 | .enter = pxa27x_cpu_pm_enter, | |
4104980a RK |
268 | .prepare = pxa27x_cpu_pm_prepare, |
269 | .finish = pxa27x_cpu_pm_finish, | |
e176bb05 | 270 | }; |
711be5cc EM |
271 | |
272 | static void __init pxa27x_init_pm(void) | |
273 | { | |
274 | pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns; | |
275 | } | |
f79299ca | 276 | #else |
277 | static inline void pxa27x_init_pm(void) {} | |
a8fa3f0c NP |
278 | #endif |
279 | ||
c95530c7 | 280 | /* PXA27x: Various gpios can issue wakeup events. This logic only |
281 | * handles the simple cases, not the WEMUX2 and WEMUX3 options | |
282 | */ | |
c95530c7 | 283 | static int pxa27x_set_wake(unsigned int irq, unsigned int on) |
284 | { | |
285 | int gpio = IRQ_TO_GPIO(irq); | |
286 | uint32_t mask; | |
287 | ||
c0a596d6 | 288 | if (gpio >= 0 && gpio < 128) |
289 | return gpio_set_wake(gpio, on); | |
c95530c7 | 290 | |
c0a596d6 | 291 | if (irq == IRQ_KEYPAD) |
292 | return keypad_set_wake(on); | |
c95530c7 | 293 | |
294 | switch (irq) { | |
295 | case IRQ_RTCAlrm: | |
296 | mask = PWER_RTC; | |
297 | break; | |
298 | case IRQ_USB: | |
299 | mask = 1u << 26; | |
300 | break; | |
301 | default: | |
302 | return -EINVAL; | |
303 | } | |
304 | ||
c95530c7 | 305 | if (on) |
306 | PWER |= mask; | |
307 | else | |
308 | PWER &=~mask; | |
309 | ||
310 | return 0; | |
311 | } | |
312 | ||
313 | void __init pxa27x_init_irq(void) | |
314 | { | |
b9e25ace | 315 | pxa_init_irq(34, pxa27x_set_wake); |
316 | pxa_init_gpio(128, pxa27x_set_wake); | |
c95530c7 | 317 | } |
318 | ||
1da177e4 LT |
319 | /* |
320 | * device registration specific to PXA27x. | |
321 | */ | |
322 | ||
34f3231f RK |
323 | static struct resource i2c_power_resources[] = { |
324 | { | |
325 | .start = 0x40f00180, | |
326 | .end = 0x40f001a3, | |
327 | .flags = IORESOURCE_MEM, | |
328 | }, { | |
329 | .start = IRQ_PWRI2C, | |
330 | .end = IRQ_PWRI2C, | |
331 | .flags = IORESOURCE_IRQ, | |
332 | }, | |
333 | }; | |
334 | ||
00dc4f94 | 335 | struct platform_device pxa27x_device_i2c_power = { |
34f3231f RK |
336 | .name = "pxa2xx-i2c", |
337 | .id = 1, | |
338 | .resource = i2c_power_resources, | |
339 | .num_resources = ARRAY_SIZE(i2c_power_resources), | |
340 | }; | |
341 | ||
9ba63c4f | 342 | void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info) |
b7a36701 | 343 | { |
bc3a5959 PZ |
344 | local_irq_disable(); |
345 | PCFR |= PCFR_PI2CEN; | |
346 | local_irq_enable(); | |
b7a36701 MR |
347 | pxa27x_device_i2c_power.dev.platform_data = info; |
348 | } | |
349 | ||
1da177e4 | 350 | static struct platform_device *devices[] __initdata = { |
7a857620 | 351 | &pxa27x_device_udc, |
e09d02e1 EM |
352 | &pxa_device_ffuart, |
353 | &pxa_device_btuart, | |
354 | &pxa_device_stuart, | |
e09d02e1 | 355 | &pxa_device_i2s, |
e09d02e1 EM |
356 | &pxa_device_rtc, |
357 | &pxa27x_device_i2c_power, | |
d8e0db11 | 358 | &pxa27x_device_ssp1, |
359 | &pxa27x_device_ssp2, | |
360 | &pxa27x_device_ssp3, | |
75540c1a | 361 | &pxa27x_device_pwm0, |
362 | &pxa27x_device_pwm1, | |
1da177e4 LT |
363 | }; |
364 | ||
c0165504 | 365 | static struct sys_device pxa27x_sysdev[] = { |
366 | { | |
c0165504 | 367 | .cls = &pxa_irq_sysclass, |
5a3d9651 EM |
368 | }, { |
369 | .cls = &pxa2xx_mfp_sysclass, | |
16dfdbf0 | 370 | }, { |
371 | .cls = &pxa_gpio_sysclass, | |
c0165504 | 372 | }, |
373 | }; | |
374 | ||
1da177e4 LT |
375 | static int __init pxa27x_init(void) |
376 | { | |
c0165504 | 377 | int i, ret = 0; |
378 | ||
e176bb05 | 379 | if (cpu_is_pxa27x()) { |
04fef228 EM |
380 | |
381 | reset_status = RCSR; | |
382 | ||
a6dba20c RK |
383 | clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks)); |
384 | ||
f53f066c EM |
385 | if ((ret = pxa_init_dma(32))) |
386 | return ret; | |
f79299ca | 387 | |
711be5cc | 388 | pxa27x_init_pm(); |
f79299ca | 389 | |
c0165504 | 390 | for (i = 0; i < ARRAY_SIZE(pxa27x_sysdev); i++) { |
391 | ret = sysdev_register(&pxa27x_sysdev[i]); | |
392 | if (ret) | |
393 | pr_err("failed to register sysdev[%d]\n", i); | |
394 | } | |
395 | ||
e176bb05 RK |
396 | ret = platform_add_devices(devices, ARRAY_SIZE(devices)); |
397 | } | |
c0165504 | 398 | |
e176bb05 | 399 | return ret; |
1da177e4 LT |
400 | } |
401 | ||
1c104e0e | 402 | postcore_initcall(pxa27x_init); |