[deliverable/linux.git] / arch / arm / mach-pxa / pxa27x.c

/*
 *  linux/arch/arm/mach-pxa/pxa27x.c
 *
 *  Author:	Nicolas Pitre
 *  Created:	Nov 05, 2002
 *  Copyright:	MontaVista Software Inc.
 *
 * Code specific to PXA27x aka Bulverde.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/gpio.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/suspend.h>
#include <linux/platform_device.h>
#include <linux/syscore_ops.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/i2c/pxa-i2c.h>
#include <linux/gpio.h>

#include <asm/mach/map.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/suspend.h>
#include <mach/irqs.h>
#include <mach/pxa27x.h>
#include <mach/reset.h>
#include <mach/ohci.h>
#include <mach/pm.h>
#include <mach/dma.h>
#include <mach/smemc.h>

#include "generic.h"
#include "devices.h"
#include "clock.h"

void pxa27x_clear_otgph(void)
{
	if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
		PSSR |= PSSR_OTGPH;
}
EXPORT_SYMBOL(pxa27x_clear_otgph);

static unsigned long ac97_reset_config[] = {
	GPIO113_GPIO,
	GPIO113_AC97_nRESET,
	GPIO95_GPIO,
	GPIO95_AC97_nRESET,
};

void pxa27x_assert_ac97reset(int reset_gpio, int on)
{
	if (reset_gpio == 113)
		pxa2xx_mfp_config(on ? &ac97_reset_config[0] :
				       &ac97_reset_config[1], 1);

	if (reset_gpio == 95)
		pxa2xx_mfp_config(on ? &ac97_reset_config[2] :
				       &ac97_reset_config[3], 1);
}
EXPORT_SYMBOL_GPL(pxa27x_assert_ac97reset);

/* Crystal clock: 13MHz */
#define BASE_CLK	13000000

/*
 * Get the clock frequency as reflected by CCSR and the turbo flag.
 * We assume these values have been applied via a fcs.
 * If info is not 0 we also display the current settings.
 */
unsigned int pxa27x_get_clk_frequency_khz(int info)
{
	unsigned long ccsr, clkcfg;
	unsigned int l, L, m, M, n2, N, S;
       	int cccr_a, t, ht, b;

	ccsr = CCSR;
	cccr_a = CCCR & (1 << 25);

	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	t  = clkcfg & (1 << 0);
	ht = clkcfg & (1 << 2);
	b  = clkcfg & (1 << 3);

	l  = ccsr & 0x1f;
	n2 = (ccsr>>7) & 0xf;
	m  = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;

	L  = l * BASE_CLK;
	N  = (L * n2) / 2;
	M  = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	S  = (b) ? L : (L/2);

	if (info) {
		printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
			L / 1000000, (L % 1000000) / 10000, l );
		printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
			N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
			(t) ? "" : "in" );
		printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
			M / 1000000, (M % 1000000) / 10000, m );
		printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
			S / 1000000, (S % 1000000) / 10000 );
	}

	return (t) ? (N/1000) : (L/1000);
}

/*
 * Return the current mem clock frequency as reflected by CCCR[A], B, and L
 */
static unsigned long clk_pxa27x_mem_getrate(struct clk *clk)
{
	unsigned long ccsr, clkcfg;
	unsigned int l, L, m, M;
       	int cccr_a, b;

	ccsr = CCSR;
	cccr_a = CCCR & (1 << 25);

	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	b = clkcfg & (1 << 3);

	l = ccsr & 0x1f;
	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;

	L = l * BASE_CLK;
	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));

	return M;
}

static const struct clkops clk_pxa27x_mem_ops = {
	.enable		= clk_dummy_enable,
	.disable	= clk_dummy_disable,
	.getrate	= clk_pxa27x_mem_getrate,
};

/*
 * Return the current LCD clock frequency in units of 10kHz as
 */
static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
{
	unsigned long ccsr;
	unsigned int l, L, k, K;

	ccsr = CCSR;

	l = ccsr & 0x1f;
	k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;

	L = l * BASE_CLK;
	K = L / k;

	return (K / 10000);
}

static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
{
	return pxa27x_get_lcdclk_frequency_10khz() * 10000;
}

static const struct clkops clk_pxa27x_lcd_ops = {
	.enable		= clk_pxa2xx_cken_enable,
	.disable	= clk_pxa2xx_cken_disable,
	.getrate	= clk_pxa27x_lcd_getrate,
};

static DEFINE_PXA2_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
static DEFINE_PXA2_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
static DEFINE_PXA2_CKEN(pxa27x_stuart, STUART, 14857000, 1);
static DEFINE_PXA2_CKEN(pxa27x_i2s, I2S, 14682000, 0);
static DEFINE_PXA2_CKEN(pxa27x_i2c, I2C, 32842000, 0);
static DEFINE_PXA2_CKEN(pxa27x_usb, USB, 48000000, 5);
static DEFINE_PXA2_CKEN(pxa27x_mmc, MMC, 19500000, 0);
static DEFINE_PXA2_CKEN(pxa27x_ficp, FICP, 48000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
static DEFINE_PXA2_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_ac97, AC97, 24576000, 0);
static DEFINE_PXA2_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
static DEFINE_PXA2_CKEN(pxa27x_msl, MSL, 48000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_usim, USIM, 48000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
static DEFINE_PXA2_CKEN(pxa27x_im, IM, 0, 0);
static DEFINE_PXA2_CKEN(pxa27x_memc, MEMC, 0, 0);

static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
static DEFINE_CLK(pxa27x_mem, &clk_pxa27x_mem_ops, 0, 0);

static struct clk_lookup pxa27x_clkregs[] = {
	INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
	INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL),
	INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL),
	INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL),
	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL),
	INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL),
	INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL),
	INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL),
	INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL),
	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"),
	INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"),
	INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL),
	INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL),
	INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL),
	INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL),
	INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL),
	INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL),
	INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL),
	INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL),
	INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"),
	INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"),
	INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"),
	INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"),
	INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
	INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
	INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
	INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
	INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
	INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
};

#ifdef CONFIG_PM

#define SAVE(x)		sleep_save[SLEEP_SAVE_##x] = x
#define RESTORE(x)	x = sleep_save[SLEEP_SAVE_##x]

/*
 * allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM
 */
static unsigned int pwrmode = PWRMODE_SLEEP;

int __init pxa27x_set_pwrmode(unsigned int mode)
{
	switch (mode) {
	case PWRMODE_SLEEP:
	case PWRMODE_DEEPSLEEP:
		pwrmode = mode;
		return 0;
	}

	return -EINVAL;
}

/*
 * List of global PXA peripheral registers to preserve.
 * More ones like CP and general purpose register values are preserved
 * with the stack pointer in sleep.S.
 */
enum {
	SLEEP_SAVE_PSTR,
	SLEEP_SAVE_MDREFR,
	SLEEP_SAVE_PCFR,
	SLEEP_SAVE_COUNT
};

void pxa27x_cpu_pm_save(unsigned long *sleep_save)
{
	sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR);
	SAVE(PCFR);

	SAVE(PSTR);
}

void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
{
	__raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR);
	RESTORE(PCFR);

	PSSR = PSSR_RDH | PSSR_PH;

	RESTORE(PSTR);
}

void pxa27x_cpu_pm_enter(suspend_state_t state)
{
	extern void pxa_cpu_standby(void);
#ifndef CONFIG_IWMMXT
	u64 acc0;

	asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0));
#endif

	/* ensure voltage-change sequencer not initiated, which hangs */
	PCFR &= ~PCFR_FVC;

	/* Clear edge-detect status register. */
	PEDR = 0xDF12FE1B;

	/* Clear reset status */
	RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;

	switch (state) {
	case PM_SUSPEND_STANDBY:
		pxa_cpu_standby();
		break;
	case PM_SUSPEND_MEM:
		cpu_suspend(pwrmode, pxa27x_finish_suspend);
#ifndef CONFIG_IWMMXT
		asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0));
#endif
		break;
	}
}

static int pxa27x_cpu_pm_valid(suspend_state_t state)
{
	return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
}

static int pxa27x_cpu_pm_prepare(void)
{
	/* set resume return address */
	PSPR = virt_to_phys(cpu_resume);
	return 0;
}

static void pxa27x_cpu_pm_finish(void)
{
	/* ensure not to come back here if it wasn't intended */
	PSPR = 0;
}

static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
	.save_count	= SLEEP_SAVE_COUNT,
	.save		= pxa27x_cpu_pm_save,
	.restore	= pxa27x_cpu_pm_restore,
	.valid		= pxa27x_cpu_pm_valid,
	.enter		= pxa27x_cpu_pm_enter,
	.prepare	= pxa27x_cpu_pm_prepare,
	.finish		= pxa27x_cpu_pm_finish,
};

static void __init pxa27x_init_pm(void)
{
	pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
}
#else
static inline void pxa27x_init_pm(void) {}
#endif

/* PXA27x:  Various gpios can issue wakeup events.  This logic only
 * handles the simple cases, not the WEMUX2 and WEMUX3 options
 */
static int pxa27x_set_wake(struct irq_data *d, unsigned int on)
{
	int gpio = irq_to_gpio(d->irq);
	uint32_t mask;

	if (gpio >= 0 && gpio < 128)
		return gpio_set_wake(gpio, on);

	if (d->irq == IRQ_KEYPAD)
		return keypad_set_wake(on);

	switch (d->irq) {
	case IRQ_RTCAlrm:
		mask = PWER_RTC;
		break;
	case IRQ_USB:
		mask = 1u << 26;
		break;
	default:
		return -EINVAL;
	}

	if (on)
		PWER |= mask;
	else
		PWER &=~mask;

	return 0;
}

void __init pxa27x_init_irq(void)
{
	pxa_init_irq(34, pxa27x_set_wake);
	pxa_init_gpio(IRQ_GPIO_2_x, 2, 120, pxa27x_set_wake);
}

static struct map_desc pxa27x_io_desc[] __initdata = {
	{	/* Mem Ctl */
		.virtual	= (unsigned long)SMEMC_VIRT,
		.pfn		= __phys_to_pfn(PXA2XX_SMEMC_BASE),
		.length		= 0x00200000,
		.type		= MT_DEVICE
	}, {	/* IMem ctl */
		.virtual	=  0xfe000000,
		.pfn		= __phys_to_pfn(0x58000000),
		.length		= 0x00100000,
		.type		= MT_DEVICE
	},
};

void __init pxa27x_map_io(void)
{
	pxa_map_io();
	iotable_init(ARRAY_AND_SIZE(pxa27x_io_desc));
	pxa27x_get_clk_frequency_khz(1);
}

/*
 * device registration specific to PXA27x.
 */
void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
{
	local_irq_disable();
	PCFR |= PCFR_PI2CEN;
	local_irq_enable();
	pxa_register_device(&pxa27x_device_i2c_power, info);
}

static struct platform_device *devices[] __initdata = {
	&pxa27x_device_udc,
	&pxa_device_pmu,
	&pxa_device_i2s,
	&pxa_device_asoc_ssp1,
	&pxa_device_asoc_ssp2,
	&pxa_device_asoc_ssp3,
	&pxa_device_asoc_platform,
	&sa1100_device_rtc,
	&pxa_device_rtc,
	&pxa27x_device_ssp1,
	&pxa27x_device_ssp2,
	&pxa27x_device_ssp3,
	&pxa27x_device_pwm0,
	&pxa27x_device_pwm1,
};

static int __init pxa27x_init(void)
{
	int ret = 0;

	if (cpu_is_pxa27x()) {

		reset_status = RCSR;

		clkdev_add_table(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));

		if ((ret = pxa_init_dma(IRQ_DMA, 32)))
			return ret;

		pxa27x_init_pm();

		register_syscore_ops(&pxa_irq_syscore_ops);
		register_syscore_ops(&pxa2xx_mfp_syscore_ops);
		register_syscore_ops(&pxa_gpio_syscore_ops);
		register_syscore_ops(&pxa2xx_clock_syscore_ops);

		ret = platform_add_devices(devices, ARRAY_SIZE(devices));
	}

	return ret;
}

postcore_initcall(pxa27x_init);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-pxa/pxa27x.c
	3	*
	4	* Author: Nicolas Pitre
	5	* Created: Nov 05, 2002
	6	* Copyright: MontaVista Software Inc.
	7	*
	8	* Code specific to PXA27x aka Bulverde.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
2f8163ba	14	#include <linux/gpio.h>
1da177e4 LT	15	#include <linux/module.h>
	16	#include <linux/kernel.h>
	17	#include <linux/init.h>
95d9ffbe	18	#include <linux/suspend.h>
d052d1be	19	#include <linux/platform_device.h>
2eaa03b5	20	#include <linux/syscore_ops.h>
ad68bb9f	21	#include <linux/io.h>
a3f4c927	22	#include <linux/irq.h>
b459396e	23	#include <linux/i2c/pxa-i2c.h>
f55be1bf	24	#include <linux/gpio.h>
1da177e4	25
851982c1	26	#include <asm/mach/map.h>
a09e64fb	27	#include <mach/hardware.h>
1da177e4	28	#include <asm/irq.h>
2c74a0ce	29	#include <asm/suspend.h>
a09e64fb	30	#include <mach/irqs.h>
51c62982	31	#include <mach/pxa27x.h>
afd2fc02	32	#include <mach/reset.h>
a09e64fb RK	33	#include <mach/ohci.h>
	34	#include <mach/pm.h>
	35	#include <mach/dma.h>
ad68bb9f MV	36	#include <mach/smemc.h>
ad68bb9f MV	37
1da177e4	38	#include "generic.h"
46c41e62	39	#include "devices.h"
a6dba20c	40	#include "clock.h"
1da177e4	41
0cb0b0d3 EM	42	void pxa27x_clear_otgph(void)
	43	{
	44	if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
	45	PSSR \|= PSSR_OTGPH;
	46	}
	47	EXPORT_SYMBOL(pxa27x_clear_otgph);
	48
fb1bf8cd	49	static unsigned long ac97_reset_config[] = {
fb1bf8cd	50	GPIO113_GPIO,
5e16e3cb EM	51	GPIO113_AC97_nRESET,
	52	GPIO95_GPIO,
	53	GPIO95_AC97_nRESET,
fb1bf8cd EM	54	};
	55
	56	void pxa27x_assert_ac97reset(int reset_gpio, int on)
	57	{
	58	if (reset_gpio == 113)
	59	pxa2xx_mfp_config(on ? &ac97_reset_config[0] :
	60	&ac97_reset_config[1], 1);
	61
	62	if (reset_gpio == 95)
	63	pxa2xx_mfp_config(on ? &ac97_reset_config[2] :
	64	&ac97_reset_config[3], 1);
	65	}
	66	EXPORT_SYMBOL_GPL(pxa27x_assert_ac97reset);
	67
1da177e4 LT	68	/* Crystal clock: 13MHz */
	69	#define BASE_CLK 13000000
	70
	71	/*
	72	* Get the clock frequency as reflected by CCSR and the turbo flag.
	73	* We assume these values have been applied via a fcs.
	74	* If info is not 0 we also display the current settings.
	75	*/
15a40333	76	unsigned int pxa27x_get_clk_frequency_khz(int info)
1da177e4 LT	77	{
	78	unsigned long ccsr, clkcfg;
	79	unsigned int l, L, m, M, n2, N, S;
	80	int cccr_a, t, ht, b;
	81
	82	ccsr = CCSR;
	83	cccr_a = CCCR & (1 << 25);
	84
	85	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	86	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
afe5df20	87	t = clkcfg & (1 << 0);
1da177e4 LT	88	ht = clkcfg & (1 << 2);
	89	b = clkcfg & (1 << 3);
	90
	91	l = ccsr & 0x1f;
	92	n2 = (ccsr>>7) & 0xf;
	93	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
	94
	95	L = l * BASE_CLK;
	96	N = (L * n2) / 2;
	97	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	98	S = (b) ? L : (L/2);
	99
	100	if (info) {
	101	printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
	102	L / 1000000, (L % 1000000) / 10000, l );
	103	printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
	104	N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
	105	(t) ? "" : "in" );
	106	printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
	107	M / 1000000, (M % 1000000) / 10000, m );
	108	printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
	109	S / 1000000, (S % 1000000) / 10000 );
	110	}
	111
	112	return (t) ? (N/1000) : (L/1000);
	113	}
	114
	115	/*
2a125dd5	116	* Return the current mem clock frequency as reflected by CCCR[A], B, and L
1da177e4	117	*/
2a125dd5	118	static unsigned long clk_pxa27x_mem_getrate(struct clk *clk)
1da177e4 LT	119	{
	120	unsigned long ccsr, clkcfg;
	121	unsigned int l, L, m, M;
	122	int cccr_a, b;
	123
	124	ccsr = CCSR;
	125	cccr_a = CCCR & (1 << 25);
	126
	127	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	128	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	129	b = clkcfg & (1 << 3);
	130
	131	l = ccsr & 0x1f;
	132	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
	133
	134	L = l * BASE_CLK;
	135	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	136
2a125dd5	137	return M;
1da177e4 LT	138	}
1da177e4 LT	139
2a125dd5 EM	140	static const struct clkops clk_pxa27x_mem_ops = {
	141	.enable = clk_dummy_enable,
	142	.disable = clk_dummy_disable,
	143	.getrate = clk_pxa27x_mem_getrate,
	144	};
	145
1da177e4 LT	146	/*
	147	* Return the current LCD clock frequency in units of 10kHz as
	148	*/
a88a447d	149	static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
1da177e4 LT	150	{
	151	unsigned long ccsr;
	152	unsigned int l, L, k, K;
	153
	154	ccsr = CCSR;
	155
	156	l = ccsr & 0x1f;
	157	k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
	158
	159	L = l * BASE_CLK;
	160	K = L / k;
	161
	162	return (K / 10000);
	163	}
	164
a6dba20c RK	165	static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
	166	{
	167	return pxa27x_get_lcdclk_frequency_10khz() * 10000;
	168	}
	169
	170	static const struct clkops clk_pxa27x_lcd_ops = {
4029813c EM	171	.enable = clk_pxa2xx_cken_enable,
4029813c EM	172	.disable = clk_pxa2xx_cken_disable,
a6dba20c RK	173	.getrate = clk_pxa27x_lcd_getrate,
	174	};
	175
4029813c EM	176	static DEFINE_PXA2_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
	177	static DEFINE_PXA2_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
	178	static DEFINE_PXA2_CKEN(pxa27x_stuart, STUART, 14857000, 1);
	179	static DEFINE_PXA2_CKEN(pxa27x_i2s, I2S, 14682000, 0);
	180	static DEFINE_PXA2_CKEN(pxa27x_i2c, I2C, 32842000, 0);
	181	static DEFINE_PXA2_CKEN(pxa27x_usb, USB, 48000000, 5);
	182	static DEFINE_PXA2_CKEN(pxa27x_mmc, MMC, 19500000, 0);
	183	static DEFINE_PXA2_CKEN(pxa27x_ficp, FICP, 48000000, 0);
	184	static DEFINE_PXA2_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
	185	static DEFINE_PXA2_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
	186	static DEFINE_PXA2_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
	187	static DEFINE_PXA2_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
	188	static DEFINE_PXA2_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
	189	static DEFINE_PXA2_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
	190	static DEFINE_PXA2_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
	191	static DEFINE_PXA2_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
	192	static DEFINE_PXA2_CKEN(pxa27x_ac97, AC97, 24576000, 0);
	193	static DEFINE_PXA2_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
	194	static DEFINE_PXA2_CKEN(pxa27x_msl, MSL, 48000000, 0);
	195	static DEFINE_PXA2_CKEN(pxa27x_usim, USIM, 48000000, 0);
	196	static DEFINE_PXA2_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
	197	static DEFINE_PXA2_CKEN(pxa27x_im, IM, 0, 0);
	198	static DEFINE_PXA2_CKEN(pxa27x_memc, MEMC, 0, 0);
	199
8c3abc7d RK	200	static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
8c3abc7d RK	201	static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
2a125dd5	202	static DEFINE_CLK(pxa27x_mem, &clk_pxa27x_mem_ops, 0, 0);
8c3abc7d RK	203
	204	static struct clk_lookup pxa27x_clkregs[] = {
	205	INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
	206	INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL),
	207	INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL),
	208	INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL),
	209	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL),
	210	INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL),
	211	INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL),
	212	INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL),
	213	INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL),
	214	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"),
	215	INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"),
	216	INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL),
	217	INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL),
	218	INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL),
	219	INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL),
	220	INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL),
	221	INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL),
	222	INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL),
	223	INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL),
	224	INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"),
	225	INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"),
	226	INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"),
	227	INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"),
	228	INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
	229	INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
	230	INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
2a125dd5	231	INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
7557c175 JZ	232	INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
7557c175 JZ	233	INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
a6dba20c RK	234	};
a6dba20c RK	235
a8fa3f0c NP	236	#ifdef CONFIG_PM
a8fa3f0c NP	237
711be5cc EM	238	#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
	239	#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
	240
d082d36e MR	241	/*
	242	* allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM
	243	*/
	244	static unsigned int pwrmode = PWRMODE_SLEEP;
	245
	246	int __init pxa27x_set_pwrmode(unsigned int mode)
	247	{
	248	switch (mode) {
	249	case PWRMODE_SLEEP:
	250	case PWRMODE_DEEPSLEEP:
	251	pwrmode = mode;
	252	return 0;
	253	}
	254
	255	return -EINVAL;
	256	}
	257
711be5cc EM	258	/*
	259	* List of global PXA peripheral registers to preserve.
	260	* More ones like CP and general purpose register values are preserved
	261	* with the stack pointer in sleep.S.
	262	*/
5a3d9651	263	enum {
711be5cc	264	SLEEP_SAVE_PSTR,
711be5cc	265	SLEEP_SAVE_MDREFR,
5a3d9651	266	SLEEP_SAVE_PCFR,
649de51b	267	SLEEP_SAVE_COUNT
711be5cc EM	268	};
	269
	270	void pxa27x_cpu_pm_save(unsigned long *sleep_save)
	271	{
ad68bb9f	272	sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR);
5a3d9651	273	SAVE(PCFR);
711be5cc	274
711be5cc	275	SAVE(PSTR);
711be5cc EM	276	}
	277
	278	void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
	279	{
ad68bb9f	280	__raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR);
5a3d9651	281	RESTORE(PCFR);
711be5cc EM	282
	283	PSSR = PSSR_RDH \| PSSR_PH;
	284
711be5cc EM	285	RESTORE(PSTR);
	286	}
	287
	288	void pxa27x_cpu_pm_enter(suspend_state_t state)
8775420d TP	289	{
8775420d TP	290	extern void pxa_cpu_standby(void);
a9503d21 RK	291	#ifndef CONFIG_IWMMXT
	292	u64 acc0;
	293
	294	asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0));
	295	#endif
8775420d	296
8775420d TP	297	/* ensure voltage-change sequencer not initiated, which hangs */
	298	PCFR &= ~PCFR_FVC;
	299
	300	/* Clear edge-detect status register. */
	301	PEDR = 0xDF12FE1B;
	302
dc38e2ad RK	303	/* Clear reset status */
	304	RCSR = RCSR_HWR \| RCSR_WDR \| RCSR_SMR \| RCSR_GPR;
	305
8775420d	306	switch (state) {
26705ca4 TP	307	case PM_SUSPEND_STANDBY:
	308	pxa_cpu_standby();
	309	break;
8775420d	310	case PM_SUSPEND_MEM:
2c74a0ce	311	cpu_suspend(pwrmode, pxa27x_finish_suspend);
a9503d21 RK	312	#ifndef CONFIG_IWMMXT
	313	asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0));
	314	#endif
8775420d TP	315	break;
	316	}
	317	}
1da177e4	318
711be5cc	319	static int pxa27x_cpu_pm_valid(suspend_state_t state)
88dfe98c RK	320	{
	321	return state == PM_SUSPEND_MEM \|\| state == PM_SUSPEND_STANDBY;
	322	}
	323
4104980a RK	324	static int pxa27x_cpu_pm_prepare(void)
	325	{
	326	/* set resume return address */
4f5ad99b	327	PSPR = virt_to_phys(cpu_resume);
4104980a RK	328	return 0;
	329	}
	330
	331	static void pxa27x_cpu_pm_finish(void)
	332	{
	333	/* ensure not to come back here if it wasn't intended */
	334	PSPR = 0;
	335	}
	336
711be5cc	337	static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
649de51b	338	.save_count = SLEEP_SAVE_COUNT,
711be5cc EM	339	.save = pxa27x_cpu_pm_save,
	340	.restore = pxa27x_cpu_pm_restore,
	341	.valid = pxa27x_cpu_pm_valid,
	342	.enter = pxa27x_cpu_pm_enter,
4104980a RK	343	.prepare = pxa27x_cpu_pm_prepare,
4104980a RK	344	.finish = pxa27x_cpu_pm_finish,
e176bb05	345	};
711be5cc EM	346
	347	static void __init pxa27x_init_pm(void)
	348	{
	349	pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
	350	}
f79299ca	351	#else
f79299ca	352	static inline void pxa27x_init_pm(void) {}
a8fa3f0c NP	353	#endif
a8fa3f0c NP	354
c95530c7	355	/* PXA27x: Various gpios can issue wakeup events. This logic only
	356	* handles the simple cases, not the WEMUX2 and WEMUX3 options
	357	*/
a3f4c927	358	static int pxa27x_set_wake(struct irq_data *d, unsigned int on)
c95530c7	359	{
7db6a7fa	360	int gpio = irq_to_gpio(d->irq);
c95530c7	361	uint32_t mask;
c95530c7	362
c0a596d6	363	if (gpio >= 0 && gpio < 128)
c0a596d6	364	return gpio_set_wake(gpio, on);
c95530c7	365
a3f4c927	366	if (d->irq == IRQ_KEYPAD)
c0a596d6	367	return keypad_set_wake(on);
c95530c7	368
a3f4c927	369	switch (d->irq) {
c95530c7	370	case IRQ_RTCAlrm:
	371	mask = PWER_RTC;
	372	break;
	373	case IRQ_USB:
	374	mask = 1u << 26;
	375	break;
	376	default:
	377	return -EINVAL;
	378	}
	379
c95530c7	380	if (on)
	381	PWER \|= mask;
	382	else
	383	PWER &=~mask;
	384
	385	return 0;
	386	}
	387
	388	void __init pxa27x_init_irq(void)
	389	{
b9e25ace	390	pxa_init_irq(34, pxa27x_set_wake);
a58fbcd8	391	pxa_init_gpio(IRQ_GPIO_2_x, 2, 120, pxa27x_set_wake);
c95530c7	392	}
c95530c7	393
851982c1 MV	394	static struct map_desc pxa27x_io_desc[] __initdata = {
851982c1 MV	395	{ /* Mem Ctl */
97b09da4	396	.virtual = (unsigned long)SMEMC_VIRT,
ad68bb9f	397	.pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE),
851982c1 MV	398	.length = 0x00200000,
	399	.type = MT_DEVICE
	400	}, { /* IMem ctl */
	401	.virtual = 0xfe000000,
	402	.pfn = __phys_to_pfn(0x58000000),
	403	.length = 0x00100000,
	404	.type = MT_DEVICE
	405	},
	406	};
	407
	408	void __init pxa27x_map_io(void)
	409	{
	410	pxa_map_io();
	411	iotable_init(ARRAY_AND_SIZE(pxa27x_io_desc));
	412	pxa27x_get_clk_frequency_khz(1);
	413	}
	414
1da177e4 LT	415	/*
	416	* device registration specific to PXA27x.
	417	*/
9ba63c4f	418	void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
b7a36701	419	{
bc3a5959 PZ	420	local_irq_disable();
	421	PCFR \|= PCFR_PI2CEN;
	422	local_irq_enable();
14758220	423	pxa_register_device(&pxa27x_device_i2c_power, info);
b7a36701 MR	424	}
b7a36701 MR	425
1da177e4	426	static struct platform_device *devices[] __initdata = {
7a857620	427	&pxa27x_device_udc,
09a5358d	428	&pxa_device_pmu,
e09d02e1	429	&pxa_device_i2s,
f0fba2ad LG	430	&pxa_device_asoc_ssp1,
	431	&pxa_device_asoc_ssp2,
	432	&pxa_device_asoc_ssp3,
	433	&pxa_device_asoc_platform,
72493146	434	&sa1100_device_rtc,
e09d02e1	435	&pxa_device_rtc,
d8e0db11	436	&pxa27x_device_ssp1,
	437	&pxa27x_device_ssp2,
	438	&pxa27x_device_ssp3,
75540c1a	439	&pxa27x_device_pwm0,
75540c1a	440	&pxa27x_device_pwm1,
1da177e4 LT	441	};
	442
	443	static int __init pxa27x_init(void)
	444	{
2eaa03b5	445	int ret = 0;
c0165504	446
e176bb05	447	if (cpu_is_pxa27x()) {
04fef228 EM	448
	449	reset_status = RCSR;
	450
0a0300dc	451	clkdev_add_table(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));
a6dba20c	452
fef1f99a	453	if ((ret = pxa_init_dma(IRQ_DMA, 32)))
f53f066c	454	return ret;
f79299ca	455
711be5cc	456	pxa27x_init_pm();
f79299ca	457
2eaa03b5 RW	458	register_syscore_ops(&pxa_irq_syscore_ops);
	459	register_syscore_ops(&pxa2xx_mfp_syscore_ops);
	460	register_syscore_ops(&pxa_gpio_syscore_ops);
	461	register_syscore_ops(&pxa2xx_clock_syscore_ops);
c0165504	462
e176bb05 RK	463	ret = platform_add_devices(devices, ARRAY_SIZE(devices));
e176bb05 RK	464	}
c0165504	465
e176bb05	466	return ret;
1da177e4 LT	467	}
1da177e4 LT	468
1c104e0e	469	postcore_initcall(pxa27x_init);