[deliverable/linux.git] / arch / arm / mach-pxa / pxa27x.c

/*
 *  linux/arch/arm/mach-pxa/pxa27x.c
 *
 *  Author:	Nicolas Pitre
 *  Created:	Nov 05, 2002
 *  Copyright:	MontaVista Software Inc.
 *
 * Code specific to PXA27x aka Bulverde.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/suspend.h>
#include <linux/platform_device.h>
#include <linux/sysdev.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/i2c/pxa-i2c.h>

#include <asm/mach/map.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <mach/irqs.h>
#include <mach/gpio.h>
#include <mach/pxa27x.h>
#include <mach/reset.h>
#include <mach/ohci.h>
#include <mach/pm.h>
#include <mach/dma.h>
#include <mach/smemc.h>

#include "generic.h"
#include "devices.h"
#include "clock.h"

void pxa27x_clear_otgph(void)
{
	if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
		PSSR |= PSSR_OTGPH;
}
EXPORT_SYMBOL(pxa27x_clear_otgph);

static unsigned long ac97_reset_config[] = {
	GPIO113_GPIO,
	GPIO113_AC97_nRESET,
	GPIO95_GPIO,
	GPIO95_AC97_nRESET,
};

void pxa27x_assert_ac97reset(int reset_gpio, int on)
{
	if (reset_gpio == 113)
		pxa2xx_mfp_config(on ? &ac97_reset_config[0] :
				       &ac97_reset_config[1], 1);

	if (reset_gpio == 95)
		pxa2xx_mfp_config(on ? &ac97_reset_config[2] :
				       &ac97_reset_config[3], 1);
}
EXPORT_SYMBOL_GPL(pxa27x_assert_ac97reset);

/* Crystal clock: 13MHz */
#define BASE_CLK	13000000

/*
 * Get the clock frequency as reflected by CCSR and the turbo flag.
 * We assume these values have been applied via a fcs.
 * If info is not 0 we also display the current settings.
 */
unsigned int pxa27x_get_clk_frequency_khz(int info)
{
	unsigned long ccsr, clkcfg;
	unsigned int l, L, m, M, n2, N, S;
       	int cccr_a, t, ht, b;

	ccsr = CCSR;
	cccr_a = CCCR & (1 << 25);

	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	t  = clkcfg & (1 << 0);
	ht = clkcfg & (1 << 2);
	b  = clkcfg & (1 << 3);

	l  = ccsr & 0x1f;
	n2 = (ccsr>>7) & 0xf;
	m  = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;

	L  = l * BASE_CLK;
	N  = (L * n2) / 2;
	M  = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	S  = (b) ? L : (L/2);

	if (info) {
		printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
			L / 1000000, (L % 1000000) / 10000, l );
		printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
			N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
			(t) ? "" : "in" );
		printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
			M / 1000000, (M % 1000000) / 10000, m );
		printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
			S / 1000000, (S % 1000000) / 10000 );
	}

	return (t) ? (N/1000) : (L/1000);
}

/*
 * Return the current mem clock frequency as reflected by CCCR[A], B, and L
 */
static unsigned long clk_pxa27x_mem_getrate(struct clk *clk)
{
	unsigned long ccsr, clkcfg;
	unsigned int l, L, m, M;
       	int cccr_a, b;

	ccsr = CCSR;
	cccr_a = CCCR & (1 << 25);

	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	b = clkcfg & (1 << 3);

	l = ccsr & 0x1f;
	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;

	L = l * BASE_CLK;
	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));

	return M;
}

static const struct clkops clk_pxa27x_mem_ops = {
	.enable		= clk_dummy_enable,
	.disable	= clk_dummy_disable,
	.getrate	= clk_pxa27x_mem_getrate,
};

/*
 * Return the current LCD clock frequency in units of 10kHz as
 */
static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
{
	unsigned long ccsr;
	unsigned int l, L, k, K;

	ccsr = CCSR;

	l = ccsr & 0x1f;
	k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;

	L = l * BASE_CLK;
	K = L / k;

	return (K / 10000);
}

static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
{
	return pxa27x_get_lcdclk_frequency_10khz() * 10000;
}

static const struct clkops clk_pxa27x_lcd_ops = {
	.enable		= clk_pxa2xx_cken_enable,
	.disable	= clk_pxa2xx_cken_disable,
	.getrate	= clk_pxa27x_lcd_getrate,
};

static DEFINE_PXA2_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
static DEFINE_PXA2_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
static DEFINE_PXA2_CKEN(pxa27x_stuart, STUART, 14857000, 1);
static DEFINE_PXA2_CKEN(pxa27x_i2s, I2S, 14682000, 0);
static DEFINE_PXA2_CKEN(pxa27x_i2c, I2C, 32842000, 0);
static DEFINE_PXA2_CKEN(pxa27x_usb, USB, 48000000, 5);
static DEFINE_PXA2_CKEN(pxa27x_mmc, MMC, 19500000, 0);
static DEFINE_PXA2_CKEN(pxa27x_ficp, FICP, 48000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
static DEFINE_PXA2_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_ac97, AC97, 24576000, 0);
static DEFINE_PXA2_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
static DEFINE_PXA2_CKEN(pxa27x_msl, MSL, 48000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_usim, USIM, 48000000, 0);
static DEFINE_PXA2_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
static DEFINE_PXA2_CKEN(pxa27x_im, IM, 0, 0);
static DEFINE_PXA2_CKEN(pxa27x_memc, MEMC, 0, 0);

static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
static DEFINE_CLK(pxa27x_mem, &clk_pxa27x_mem_ops, 0, 0);

static struct clk_lookup pxa27x_clkregs[] = {
	INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
	INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL),
	INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL),
	INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL),
	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL),
	INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL),
	INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL),
	INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL),
	INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL),
	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"),
	INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"),
	INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL),
	INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL),
	INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL),
	INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL),
	INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL),
	INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL),
	INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL),
	INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL),
	INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"),
	INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"),
	INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"),
	INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"),
	INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
	INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
	INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
	INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
};

#ifdef CONFIG_PM

#define SAVE(x)		sleep_save[SLEEP_SAVE_##x] = x
#define RESTORE(x)	x = sleep_save[SLEEP_SAVE_##x]

/*
 * allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM
 */
static unsigned int pwrmode = PWRMODE_SLEEP;

int __init pxa27x_set_pwrmode(unsigned int mode)
{
	switch (mode) {
	case PWRMODE_SLEEP:
	case PWRMODE_DEEPSLEEP:
		pwrmode = mode;
		return 0;
	}

	return -EINVAL;
}

/*
 * List of global PXA peripheral registers to preserve.
 * More ones like CP and general purpose register values are preserved
 * with the stack pointer in sleep.S.
 */
enum {
	SLEEP_SAVE_PSTR,
	SLEEP_SAVE_MDREFR,
	SLEEP_SAVE_PCFR,
	SLEEP_SAVE_COUNT
};

void pxa27x_cpu_pm_save(unsigned long *sleep_save)
{
	sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR);
	SAVE(PCFR);

	SAVE(PSTR);
}

void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
{
	__raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR);
	RESTORE(PCFR);

	PSSR = PSSR_RDH | PSSR_PH;

	RESTORE(PSTR);
}

void pxa27x_cpu_pm_enter(suspend_state_t state)
{
	extern void pxa_cpu_standby(void);

	/* ensure voltage-change sequencer not initiated, which hangs */
	PCFR &= ~PCFR_FVC;

	/* Clear edge-detect status register. */
	PEDR = 0xDF12FE1B;

	/* Clear reset status */
	RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;

	switch (state) {
	case PM_SUSPEND_STANDBY:
		pxa_cpu_standby();
		break;
	case PM_SUSPEND_MEM:
		pxa27x_cpu_suspend(pwrmode, PLAT_PHYS_OFFSET - PAGE_OFFSET);
		break;
	}
}

static int pxa27x_cpu_pm_valid(suspend_state_t state)
{
	return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
}

static int pxa27x_cpu_pm_prepare(void)
{
	/* set resume return address */
	PSPR = virt_to_phys(cpu_resume);
	return 0;
}

static void pxa27x_cpu_pm_finish(void)
{
	/* ensure not to come back here if it wasn't intended */
	PSPR = 0;
}

static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
	.save_count	= SLEEP_SAVE_COUNT,
	.save		= pxa27x_cpu_pm_save,
	.restore	= pxa27x_cpu_pm_restore,
	.valid		= pxa27x_cpu_pm_valid,
	.enter		= pxa27x_cpu_pm_enter,
	.prepare	= pxa27x_cpu_pm_prepare,
	.finish		= pxa27x_cpu_pm_finish,
};

static void __init pxa27x_init_pm(void)
{
	pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
}
#else
static inline void pxa27x_init_pm(void) {}
#endif

/* PXA27x:  Various gpios can issue wakeup events.  This logic only
 * handles the simple cases, not the WEMUX2 and WEMUX3 options
 */
static int pxa27x_set_wake(struct irq_data *d, unsigned int on)
{
	int gpio = irq_to_gpio(d->irq);
	uint32_t mask;

	if (gpio >= 0 && gpio < 128)
		return gpio_set_wake(gpio, on);

	if (d->irq == IRQ_KEYPAD)
		return keypad_set_wake(on);

	switch (d->irq) {
	case IRQ_RTCAlrm:
		mask = PWER_RTC;
		break;
	case IRQ_USB:
		mask = 1u << 26;
		break;
	default:
		return -EINVAL;
	}

	if (on)
		PWER |= mask;
	else
		PWER &=~mask;

	return 0;
}

void __init pxa27x_init_irq(void)
{
	pxa_init_irq(34, pxa27x_set_wake);
	pxa_init_gpio(IRQ_GPIO_2_x, 2, 120, pxa27x_set_wake);
}

static struct map_desc pxa27x_io_desc[] __initdata = {
	{	/* Mem Ctl */
		.virtual	= SMEMC_VIRT,
		.pfn		= __phys_to_pfn(PXA2XX_SMEMC_BASE),
		.length		= 0x00200000,
		.type		= MT_DEVICE
	}, {	/* IMem ctl */
		.virtual	=  0xfe000000,
		.pfn		= __phys_to_pfn(0x58000000),
		.length		= 0x00100000,
		.type		= MT_DEVICE
	},
};

void __init pxa27x_map_io(void)
{
	pxa_map_io();
	iotable_init(ARRAY_AND_SIZE(pxa27x_io_desc));
	pxa27x_get_clk_frequency_khz(1);
}

/*
 * device registration specific to PXA27x.
 */
void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
{
	local_irq_disable();
	PCFR |= PCFR_PI2CEN;
	local_irq_enable();
	pxa_register_device(&pxa27x_device_i2c_power, info);
}

static struct platform_device *devices[] __initdata = {
	&pxa27x_device_udc,
	&pxa_device_pmu,
	&pxa_device_i2s,
	&pxa_device_asoc_ssp1,
	&pxa_device_asoc_ssp2,
	&pxa_device_asoc_ssp3,
	&pxa_device_asoc_platform,
	&sa1100_device_rtc,
	&pxa_device_rtc,
	&pxa27x_device_ssp1,
	&pxa27x_device_ssp2,
	&pxa27x_device_ssp3,
	&pxa27x_device_pwm0,
	&pxa27x_device_pwm1,
};

static struct sys_device pxa27x_sysdev[] = {
	{
		.cls	= &pxa_irq_sysclass,
	}, {
		.cls	= &pxa2xx_mfp_sysclass,
	}, {
		.cls	= &pxa_gpio_sysclass,
	}, {
		.cls	= &pxa2xx_clock_sysclass,
	}
};

static int __init pxa27x_init(void)
{
	int i, ret = 0;

	if (cpu_is_pxa27x()) {

		reset_status = RCSR;

		clkdev_add_table(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));

		if ((ret = pxa_init_dma(IRQ_DMA, 32)))
			return ret;

		pxa27x_init_pm();

		for (i = 0; i < ARRAY_SIZE(pxa27x_sysdev); i++) {
			ret = sysdev_register(&pxa27x_sysdev[i]);
			if (ret)
				pr_err("failed to register sysdev[%d]\n", i);
		}

		ret = platform_add_devices(devices, ARRAY_SIZE(devices));
	}

	return ret;
}

postcore_initcall(pxa27x_init);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-pxa/pxa27x.c
	3	*
	4	* Author: Nicolas Pitre
	5	* Created: Nov 05, 2002
	6	* Copyright: MontaVista Software Inc.
	7	*
	8	* Code specific to PXA27x aka Bulverde.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
1da177e4 LT	14	#include <linux/module.h>
	15	#include <linux/kernel.h>
	16	#include <linux/init.h>
95d9ffbe	17	#include <linux/suspend.h>
d052d1be	18	#include <linux/platform_device.h>
c0165504	19	#include <linux/sysdev.h>
ad68bb9f	20	#include <linux/io.h>
a3f4c927	21	#include <linux/irq.h>
b459396e	22	#include <linux/i2c/pxa-i2c.h>
1da177e4	23
851982c1	24	#include <asm/mach/map.h>
a09e64fb	25	#include <mach/hardware.h>
1da177e4	26	#include <asm/irq.h>
a09e64fb	27	#include <mach/irqs.h>
a58fbcd8	28	#include <mach/gpio.h>
51c62982	29	#include <mach/pxa27x.h>
afd2fc02	30	#include <mach/reset.h>
a09e64fb RK	31	#include <mach/ohci.h>
	32	#include <mach/pm.h>
	33	#include <mach/dma.h>
ad68bb9f MV	34	#include <mach/smemc.h>
ad68bb9f MV	35
1da177e4	36	#include "generic.h"
46c41e62	37	#include "devices.h"
a6dba20c	38	#include "clock.h"
1da177e4	39
0cb0b0d3 EM	40	void pxa27x_clear_otgph(void)
	41	{
	42	if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
	43	PSSR \|= PSSR_OTGPH;
	44	}
	45	EXPORT_SYMBOL(pxa27x_clear_otgph);
	46
fb1bf8cd	47	static unsigned long ac97_reset_config[] = {
fb1bf8cd	48	GPIO113_GPIO,
5e16e3cb EM	49	GPIO113_AC97_nRESET,
	50	GPIO95_GPIO,
	51	GPIO95_AC97_nRESET,
fb1bf8cd EM	52	};
	53
	54	void pxa27x_assert_ac97reset(int reset_gpio, int on)
	55	{
	56	if (reset_gpio == 113)
	57	pxa2xx_mfp_config(on ? &ac97_reset_config[0] :
	58	&ac97_reset_config[1], 1);
	59
	60	if (reset_gpio == 95)
	61	pxa2xx_mfp_config(on ? &ac97_reset_config[2] :
	62	&ac97_reset_config[3], 1);
	63	}
	64	EXPORT_SYMBOL_GPL(pxa27x_assert_ac97reset);
	65
1da177e4 LT	66	/* Crystal clock: 13MHz */
	67	#define BASE_CLK 13000000
	68
	69	/*
	70	* Get the clock frequency as reflected by CCSR and the turbo flag.
	71	* We assume these values have been applied via a fcs.
	72	* If info is not 0 we also display the current settings.
	73	*/
15a40333	74	unsigned int pxa27x_get_clk_frequency_khz(int info)
1da177e4 LT	75	{
	76	unsigned long ccsr, clkcfg;
	77	unsigned int l, L, m, M, n2, N, S;
	78	int cccr_a, t, ht, b;
	79
	80	ccsr = CCSR;
	81	cccr_a = CCCR & (1 << 25);
	82
	83	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	84	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
afe5df20	85	t = clkcfg & (1 << 0);
1da177e4 LT	86	ht = clkcfg & (1 << 2);
	87	b = clkcfg & (1 << 3);
	88
	89	l = ccsr & 0x1f;
	90	n2 = (ccsr>>7) & 0xf;
	91	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
	92
	93	L = l * BASE_CLK;
	94	N = (L * n2) / 2;
	95	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	96	S = (b) ? L : (L/2);
	97
	98	if (info) {
	99	printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
	100	L / 1000000, (L % 1000000) / 10000, l );
	101	printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
	102	N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
	103	(t) ? "" : "in" );
	104	printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
	105	M / 1000000, (M % 1000000) / 10000, m );
	106	printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
	107	S / 1000000, (S % 1000000) / 10000 );
	108	}
	109
	110	return (t) ? (N/1000) : (L/1000);
	111	}
	112
	113	/*
2a125dd5	114	* Return the current mem clock frequency as reflected by CCCR[A], B, and L
1da177e4	115	*/
2a125dd5	116	static unsigned long clk_pxa27x_mem_getrate(struct clk *clk)
1da177e4 LT	117	{
	118	unsigned long ccsr, clkcfg;
	119	unsigned int l, L, m, M;
	120	int cccr_a, b;
	121
	122	ccsr = CCSR;
	123	cccr_a = CCCR & (1 << 25);
	124
	125	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	126	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	127	b = clkcfg & (1 << 3);
	128
	129	l = ccsr & 0x1f;
	130	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
	131
	132	L = l * BASE_CLK;
	133	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	134
2a125dd5	135	return M;
1da177e4 LT	136	}
1da177e4 LT	137
2a125dd5 EM	138	static const struct clkops clk_pxa27x_mem_ops = {
	139	.enable = clk_dummy_enable,
	140	.disable = clk_dummy_disable,
	141	.getrate = clk_pxa27x_mem_getrate,
	142	};
	143
1da177e4 LT	144	/*
	145	* Return the current LCD clock frequency in units of 10kHz as
	146	*/
a88a447d	147	static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
1da177e4 LT	148	{
	149	unsigned long ccsr;
	150	unsigned int l, L, k, K;
	151
	152	ccsr = CCSR;
	153
	154	l = ccsr & 0x1f;
	155	k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
	156
	157	L = l * BASE_CLK;
	158	K = L / k;
	159
	160	return (K / 10000);
	161	}
	162
a6dba20c RK	163	static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
	164	{
	165	return pxa27x_get_lcdclk_frequency_10khz() * 10000;
	166	}
	167
	168	static const struct clkops clk_pxa27x_lcd_ops = {
4029813c EM	169	.enable = clk_pxa2xx_cken_enable,
4029813c EM	170	.disable = clk_pxa2xx_cken_disable,
a6dba20c RK	171	.getrate = clk_pxa27x_lcd_getrate,
	172	};
	173
4029813c EM	174	static DEFINE_PXA2_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
	175	static DEFINE_PXA2_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
	176	static DEFINE_PXA2_CKEN(pxa27x_stuart, STUART, 14857000, 1);
	177	static DEFINE_PXA2_CKEN(pxa27x_i2s, I2S, 14682000, 0);
	178	static DEFINE_PXA2_CKEN(pxa27x_i2c, I2C, 32842000, 0);
	179	static DEFINE_PXA2_CKEN(pxa27x_usb, USB, 48000000, 5);
	180	static DEFINE_PXA2_CKEN(pxa27x_mmc, MMC, 19500000, 0);
	181	static DEFINE_PXA2_CKEN(pxa27x_ficp, FICP, 48000000, 0);
	182	static DEFINE_PXA2_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
	183	static DEFINE_PXA2_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
	184	static DEFINE_PXA2_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
	185	static DEFINE_PXA2_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
	186	static DEFINE_PXA2_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
	187	static DEFINE_PXA2_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
	188	static DEFINE_PXA2_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
	189	static DEFINE_PXA2_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
	190	static DEFINE_PXA2_CKEN(pxa27x_ac97, AC97, 24576000, 0);
	191	static DEFINE_PXA2_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
	192	static DEFINE_PXA2_CKEN(pxa27x_msl, MSL, 48000000, 0);
	193	static DEFINE_PXA2_CKEN(pxa27x_usim, USIM, 48000000, 0);
	194	static DEFINE_PXA2_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
	195	static DEFINE_PXA2_CKEN(pxa27x_im, IM, 0, 0);
	196	static DEFINE_PXA2_CKEN(pxa27x_memc, MEMC, 0, 0);
	197
8c3abc7d RK	198	static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
8c3abc7d RK	199	static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
2a125dd5	200	static DEFINE_CLK(pxa27x_mem, &clk_pxa27x_mem_ops, 0, 0);
8c3abc7d RK	201
	202	static struct clk_lookup pxa27x_clkregs[] = {
	203	INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
	204	INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL),
	205	INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL),
	206	INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL),
	207	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL),
	208	INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL),
	209	INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL),
	210	INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL),
	211	INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL),
	212	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"),
	213	INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"),
	214	INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL),
	215	INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL),
	216	INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL),
	217	INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL),
	218	INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL),
	219	INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL),
	220	INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL),
	221	INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL),
	222	INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"),
	223	INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"),
	224	INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"),
	225	INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"),
	226	INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
	227	INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
	228	INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
2a125dd5	229	INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
a6dba20c RK	230	};
a6dba20c RK	231
a8fa3f0c NP	232	#ifdef CONFIG_PM
a8fa3f0c NP	233
711be5cc EM	234	#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
	235	#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
	236
d082d36e MR	237	/*
	238	* allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM
	239	*/
	240	static unsigned int pwrmode = PWRMODE_SLEEP;
	241
	242	int __init pxa27x_set_pwrmode(unsigned int mode)
	243	{
	244	switch (mode) {
	245	case PWRMODE_SLEEP:
	246	case PWRMODE_DEEPSLEEP:
	247	pwrmode = mode;
	248	return 0;
	249	}
	250
	251	return -EINVAL;
	252	}
	253
711be5cc EM	254	/*
	255	* List of global PXA peripheral registers to preserve.
	256	* More ones like CP and general purpose register values are preserved
	257	* with the stack pointer in sleep.S.
	258	*/
5a3d9651	259	enum {
711be5cc	260	SLEEP_SAVE_PSTR,
711be5cc	261	SLEEP_SAVE_MDREFR,
5a3d9651	262	SLEEP_SAVE_PCFR,
649de51b	263	SLEEP_SAVE_COUNT
711be5cc EM	264	};
	265
	266	void pxa27x_cpu_pm_save(unsigned long *sleep_save)
	267	{
ad68bb9f	268	sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR);
5a3d9651	269	SAVE(PCFR);
711be5cc	270
711be5cc	271	SAVE(PSTR);
711be5cc EM	272	}
	273
	274	void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
	275	{
ad68bb9f	276	__raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR);
5a3d9651	277	RESTORE(PCFR);
711be5cc EM	278
	279	PSSR = PSSR_RDH \| PSSR_PH;
	280
711be5cc EM	281	RESTORE(PSTR);
	282	}
	283
	284	void pxa27x_cpu_pm_enter(suspend_state_t state)
8775420d TP	285	{
8775420d TP	286	extern void pxa_cpu_standby(void);
8775420d	287
8775420d TP	288	/* ensure voltage-change sequencer not initiated, which hangs */
	289	PCFR &= ~PCFR_FVC;
	290
	291	/* Clear edge-detect status register. */
	292	PEDR = 0xDF12FE1B;
	293
dc38e2ad RK	294	/* Clear reset status */
	295	RCSR = RCSR_HWR \| RCSR_WDR \| RCSR_SMR \| RCSR_GPR;
	296
8775420d	297	switch (state) {
26705ca4 TP	298	case PM_SUSPEND_STANDBY:
	299	pxa_cpu_standby();
	300	break;
8775420d	301	case PM_SUSPEND_MEM:
4f5ad99b	302	pxa27x_cpu_suspend(pwrmode, PLAT_PHYS_OFFSET - PAGE_OFFSET);
8775420d TP	303	break;
	304	}
	305	}
1da177e4	306
711be5cc	307	static int pxa27x_cpu_pm_valid(suspend_state_t state)
88dfe98c RK	308	{
	309	return state == PM_SUSPEND_MEM \|\| state == PM_SUSPEND_STANDBY;
	310	}
	311
4104980a RK	312	static int pxa27x_cpu_pm_prepare(void)
	313	{
	314	/* set resume return address */
4f5ad99b	315	PSPR = virt_to_phys(cpu_resume);
4104980a RK	316	return 0;
	317	}
	318
	319	static void pxa27x_cpu_pm_finish(void)
	320	{
	321	/* ensure not to come back here if it wasn't intended */
	322	PSPR = 0;
	323	}
	324
711be5cc	325	static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
649de51b	326	.save_count = SLEEP_SAVE_COUNT,
711be5cc EM	327	.save = pxa27x_cpu_pm_save,
	328	.restore = pxa27x_cpu_pm_restore,
	329	.valid = pxa27x_cpu_pm_valid,
	330	.enter = pxa27x_cpu_pm_enter,
4104980a RK	331	.prepare = pxa27x_cpu_pm_prepare,
4104980a RK	332	.finish = pxa27x_cpu_pm_finish,
e176bb05	333	};
711be5cc EM	334
	335	static void __init pxa27x_init_pm(void)
	336	{
	337	pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
	338	}
f79299ca	339	#else
f79299ca	340	static inline void pxa27x_init_pm(void) {}
a8fa3f0c NP	341	#endif
a8fa3f0c NP	342
c95530c7	343	/* PXA27x: Various gpios can issue wakeup events. This logic only
	344	* handles the simple cases, not the WEMUX2 and WEMUX3 options
	345	*/
a3f4c927	346	static int pxa27x_set_wake(struct irq_data *d, unsigned int on)
c95530c7	347	{
7db6a7fa	348	int gpio = irq_to_gpio(d->irq);
c95530c7	349	uint32_t mask;
c95530c7	350
c0a596d6	351	if (gpio >= 0 && gpio < 128)
c0a596d6	352	return gpio_set_wake(gpio, on);
c95530c7	353
a3f4c927	354	if (d->irq == IRQ_KEYPAD)
c0a596d6	355	return keypad_set_wake(on);
c95530c7	356
a3f4c927	357	switch (d->irq) {
c95530c7	358	case IRQ_RTCAlrm:
	359	mask = PWER_RTC;
	360	break;
	361	case IRQ_USB:
	362	mask = 1u << 26;
	363	break;
	364	default:
	365	return -EINVAL;
	366	}
	367
c95530c7	368	if (on)
	369	PWER \|= mask;
	370	else
	371	PWER &=~mask;
	372
	373	return 0;
	374	}
	375
	376	void __init pxa27x_init_irq(void)
	377	{
b9e25ace	378	pxa_init_irq(34, pxa27x_set_wake);
a58fbcd8	379	pxa_init_gpio(IRQ_GPIO_2_x, 2, 120, pxa27x_set_wake);
c95530c7	380	}
c95530c7	381
851982c1 MV	382	static struct map_desc pxa27x_io_desc[] __initdata = {
851982c1 MV	383	{ /* Mem Ctl */
ad68bb9f MV	384	.virtual = SMEMC_VIRT,
ad68bb9f MV	385	.pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE),
851982c1 MV	386	.length = 0x00200000,
	387	.type = MT_DEVICE
	388	}, { /* IMem ctl */
	389	.virtual = 0xfe000000,
	390	.pfn = __phys_to_pfn(0x58000000),
	391	.length = 0x00100000,
	392	.type = MT_DEVICE
	393	},
	394	};
	395
	396	void __init pxa27x_map_io(void)
	397	{
	398	pxa_map_io();
	399	iotable_init(ARRAY_AND_SIZE(pxa27x_io_desc));
	400	pxa27x_get_clk_frequency_khz(1);
	401	}
	402
1da177e4 LT	403	/*
	404	* device registration specific to PXA27x.
	405	*/
9ba63c4f	406	void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
b7a36701	407	{
bc3a5959 PZ	408	local_irq_disable();
	409	PCFR \|= PCFR_PI2CEN;
	410	local_irq_enable();
14758220	411	pxa_register_device(&pxa27x_device_i2c_power, info);
b7a36701 MR	412	}
b7a36701 MR	413
1da177e4	414	static struct platform_device *devices[] __initdata = {
7a857620	415	&pxa27x_device_udc,
09a5358d	416	&pxa_device_pmu,
e09d02e1	417	&pxa_device_i2s,
f0fba2ad LG	418	&pxa_device_asoc_ssp1,
	419	&pxa_device_asoc_ssp2,
	420	&pxa_device_asoc_ssp3,
	421	&pxa_device_asoc_platform,
72493146	422	&sa1100_device_rtc,
e09d02e1	423	&pxa_device_rtc,
d8e0db11	424	&pxa27x_device_ssp1,
	425	&pxa27x_device_ssp2,
	426	&pxa27x_device_ssp3,
75540c1a	427	&pxa27x_device_pwm0,
75540c1a	428	&pxa27x_device_pwm1,
1da177e4 LT	429	};
1da177e4 LT	430
c0165504	431	static struct sys_device pxa27x_sysdev[] = {
c0165504	432	{
c0165504	433	.cls = &pxa_irq_sysclass,
5a3d9651 EM	434	}, {
5a3d9651 EM	435	.cls = &pxa2xx_mfp_sysclass,
16dfdbf0	436	}, {
16dfdbf0	437	.cls = &pxa_gpio_sysclass,
f113fe4e EM	438	}, {
	439	.cls = &pxa2xx_clock_sysclass,
	440	}
c0165504	441	};
c0165504	442
1da177e4 LT	443	static int __init pxa27x_init(void)
1da177e4 LT	444	{
c0165504	445	int i, ret = 0;
c0165504	446
e176bb05	447	if (cpu_is_pxa27x()) {
04fef228 EM	448
	449	reset_status = RCSR;
	450
0a0300dc	451	clkdev_add_table(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));
a6dba20c	452
fef1f99a	453	if ((ret = pxa_init_dma(IRQ_DMA, 32)))
f53f066c	454	return ret;
f79299ca	455
711be5cc	456	pxa27x_init_pm();
f79299ca	457
c0165504	458	for (i = 0; i < ARRAY_SIZE(pxa27x_sysdev); i++) {
	459	ret = sysdev_register(&pxa27x_sysdev[i]);
	460	if (ret)
	461	pr_err("failed to register sysdev[%d]\n", i);
	462	}
	463
e176bb05 RK	464	ret = platform_add_devices(devices, ARRAY_SIZE(devices));
e176bb05 RK	465	}
c0165504	466
e176bb05	467	return ret;
1da177e4 LT	468	}
1da177e4 LT	469
1c104e0e	470	postcore_initcall(pxa27x_init);