[deliverable/linux.git] / arch / arm / mach-pxa / pxa27x.c

/*
 *  linux/arch/arm/mach-pxa/pxa27x.c
 *
 *  Author:	Nicolas Pitre
 *  Created:	Nov 05, 2002
 *  Copyright:	MontaVista Software Inc.
 *
 * Code specific to PXA27x aka Bulverde.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pm.h>
#include <linux/platform_device.h>

#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/arch/irqs.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/ohci.h>
#include <asm/arch/pm.h>
#include <asm/arch/dma.h>

#include "generic.h"
#include "devices.h"

/* Crystal clock: 13MHz */
#define BASE_CLK	13000000

/*
 * Get the clock frequency as reflected by CCSR and the turbo flag.
 * We assume these values have been applied via a fcs.
 * If info is not 0 we also display the current settings.
 */
unsigned int get_clk_frequency_khz( int info)
{
	unsigned long ccsr, clkcfg;
	unsigned int l, L, m, M, n2, N, S;
       	int cccr_a, t, ht, b;

	ccsr = CCSR;
	cccr_a = CCCR & (1 << 25);

	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	t  = clkcfg & (1 << 0);
	ht = clkcfg & (1 << 2);
	b  = clkcfg & (1 << 3);

	l  = ccsr & 0x1f;
	n2 = (ccsr>>7) & 0xf;
	m  = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;

	L  = l * BASE_CLK;
	N  = (L * n2) / 2;
	M  = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	S  = (b) ? L : (L/2);

	if (info) {
		printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
			L / 1000000, (L % 1000000) / 10000, l );
		printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
			N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
			(t) ? "" : "in" );
		printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
			M / 1000000, (M % 1000000) / 10000, m );
		printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
			S / 1000000, (S % 1000000) / 10000 );
	}

	return (t) ? (N/1000) : (L/1000);
}

/*
 * Return the current mem clock frequency in units of 10kHz as
 * reflected by CCCR[A], B, and L
 */
unsigned int get_memclk_frequency_10khz(void)
{
	unsigned long ccsr, clkcfg;
	unsigned int l, L, m, M;
       	int cccr_a, b;

	ccsr = CCSR;
	cccr_a = CCCR & (1 << 25);

	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	b = clkcfg & (1 << 3);

	l = ccsr & 0x1f;
	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;

	L = l * BASE_CLK;
	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));

	return (M / 10000);
}

/*
 * Return the current LCD clock frequency in units of 10kHz as
 */
unsigned int get_lcdclk_frequency_10khz(void)
{
	unsigned long ccsr;
	unsigned int l, L, k, K;

	ccsr = CCSR;

	l = ccsr & 0x1f;
	k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;

	L = l * BASE_CLK;
	K = L / k;

	return (K / 10000);
}

EXPORT_SYMBOL(get_clk_frequency_khz);
EXPORT_SYMBOL(get_memclk_frequency_10khz);
EXPORT_SYMBOL(get_lcdclk_frequency_10khz);

#ifdef CONFIG_PM

void pxa_cpu_pm_enter(suspend_state_t state)
{
	extern void pxa_cpu_standby(void);
	extern void pxa_cpu_suspend(unsigned int);
	extern void pxa_cpu_resume(void);

	if (state == PM_SUSPEND_STANDBY)
		CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER) | (1 << CKEN_LCD) | (1 << CKEN_PWM0);
	else
		CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER);

	/* ensure voltage-change sequencer not initiated, which hangs */
	PCFR &= ~PCFR_FVC;

	/* Clear edge-detect status register. */
	PEDR = 0xDF12FE1B;

	switch (state) {
	case PM_SUSPEND_STANDBY:
		pxa_cpu_standby();
		break;
	case PM_SUSPEND_MEM:
		/* set resume return address */
		PSPR = virt_to_phys(pxa_cpu_resume);
		pxa_cpu_suspend(PWRMODE_SLEEP);
		break;
	}
}

static int pxa27x_pm_valid(suspend_state_t state)
{
	return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
}

static struct pm_ops pxa27x_pm_ops = {
	.enter		= pxa_pm_enter,
	.valid		= pxa27x_pm_valid,
};
#endif

/*
 * device registration specific to PXA27x.
 */

static u64 pxa27x_dmamask = 0xffffffffUL;

static struct resource pxa27x_ohci_resources[] = {
	[0] = {
		.start  = 0x4C000000,
		.end    = 0x4C00ff6f,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = IRQ_USBH1,
		.end    = IRQ_USBH1,
		.flags  = IORESOURCE_IRQ,
	},
};

static struct platform_device pxaohci_device = {
	.name		= "pxa27x-ohci",
	.id		= -1,
	.dev		= {
		.dma_mask = &pxa27x_dmamask,
		.coherent_dma_mask = 0xffffffff,
	},
	.num_resources  = ARRAY_SIZE(pxa27x_ohci_resources),
	.resource       = pxa27x_ohci_resources,
};

void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
{
	pxaohci_device.dev.platform_data = info;
}

static struct resource i2c_power_resources[] = {
	{
		.start	= 0x40f00180,
		.end	= 0x40f001a3,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_PWRI2C,
		.end	= IRQ_PWRI2C,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device pxai2c_power_device = {
	.name		= "pxa2xx-i2c",
	.id		= 1,
	.resource	= i2c_power_resources,
	.num_resources	= ARRAY_SIZE(i2c_power_resources),
};

static struct platform_device *devices[] __initdata = {
	&pxamci_device,
	&pxaudc_device,
	&pxafb_device,
	&ffuart_device,
	&btuart_device,
	&stuart_device,
	&pxai2c_device,
	&pxai2c_power_device,
	&pxai2s_device,
	&pxaficp_device,
	&pxartc_device,
	&pxaohci_device,
};

void __init pxa27x_init_irq(void)
{
	pxa_init_irq_low();
	pxa_init_irq_high();
	pxa_init_irq_gpio(128);
}

static int __init pxa27x_init(void)
{
	int ret = 0;
	if (cpu_is_pxa27x()) {
		if ((ret = pxa_init_dma(32)))
			return ret;
#ifdef CONFIG_PM
		pm_set_ops(&pxa27x_pm_ops);
#endif
		ret = platform_add_devices(devices, ARRAY_SIZE(devices));
	}
	return ret;
}

subsys_initcall(pxa27x_init);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-pxa/pxa27x.c
	3	*
	4	* Author: Nicolas Pitre
	5	* Created: Nov 05, 2002
	6	* Copyright: MontaVista Software Inc.
	7	*
	8	* Code specific to PXA27x aka Bulverde.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
1da177e4 LT	14	#include <linux/module.h>
	15	#include <linux/kernel.h>
	16	#include <linux/init.h>
	17	#include <linux/pm.h>
d052d1be	18	#include <linux/platform_device.h>
1da177e4 LT	19
	20	#include <asm/hardware.h>
	21	#include <asm/irq.h>
cd49104d	22	#include <asm/arch/irqs.h>
1da177e4	23	#include <asm/arch/pxa-regs.h>
81f280e2	24	#include <asm/arch/ohci.h>
e176bb05	25	#include <asm/arch/pm.h>
f53f066c	26	#include <asm/arch/dma.h>
1da177e4 LT	27
1da177e4 LT	28	#include "generic.h"
46c41e62	29	#include "devices.h"
1da177e4 LT	30
	31	/* Crystal clock: 13MHz */
	32	#define BASE_CLK 13000000
	33
	34	/*
	35	* Get the clock frequency as reflected by CCSR and the turbo flag.
	36	* We assume these values have been applied via a fcs.
	37	* If info is not 0 we also display the current settings.
	38	*/
	39	unsigned int get_clk_frequency_khz( int info)
	40	{
	41	unsigned long ccsr, clkcfg;
	42	unsigned int l, L, m, M, n2, N, S;
	43	int cccr_a, t, ht, b;
	44
	45	ccsr = CCSR;
	46	cccr_a = CCCR & (1 << 25);
	47
	48	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	49	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
afe5df20	50	t = clkcfg & (1 << 0);
1da177e4 LT	51	ht = clkcfg & (1 << 2);
	52	b = clkcfg & (1 << 3);
	53
	54	l = ccsr & 0x1f;
	55	n2 = (ccsr>>7) & 0xf;
	56	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
	57
	58	L = l * BASE_CLK;
	59	N = (L * n2) / 2;
	60	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	61	S = (b) ? L : (L/2);
	62
	63	if (info) {
	64	printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
	65	L / 1000000, (L % 1000000) / 10000, l );
	66	printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
	67	N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
	68	(t) ? "" : "in" );
	69	printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
	70	M / 1000000, (M % 1000000) / 10000, m );
	71	printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
	72	S / 1000000, (S % 1000000) / 10000 );
	73	}
	74
	75	return (t) ? (N/1000) : (L/1000);
	76	}
	77
	78	/*
	79	* Return the current mem clock frequency in units of 10kHz as
	80	* reflected by CCCR[A], B, and L
	81	*/
	82	unsigned int get_memclk_frequency_10khz(void)
	83	{
	84	unsigned long ccsr, clkcfg;
	85	unsigned int l, L, m, M;
	86	int cccr_a, b;
	87
	88	ccsr = CCSR;
	89	cccr_a = CCCR & (1 << 25);
	90
	91	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	92	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	93	b = clkcfg & (1 << 3);
	94
	95	l = ccsr & 0x1f;
	96	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
	97
	98	L = l * BASE_CLK;
	99	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	100
	101	return (M / 10000);
	102	}
	103
	104	/*
	105	* Return the current LCD clock frequency in units of 10kHz as
	106	*/
	107	unsigned int get_lcdclk_frequency_10khz(void)
	108	{
	109	unsigned long ccsr;
	110	unsigned int l, L, k, K;
	111
	112	ccsr = CCSR;
	113
	114	l = ccsr & 0x1f;
115	k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
116
117	L = l * BASE_CLK;
118	K = L / k;
119
120	return (K / 10000);
121	}
122
123	EXPORT_SYMBOL(get_clk_frequency_khz);
124	EXPORT_SYMBOL(get_memclk_frequency_10khz);
125	EXPORT_SYMBOL(get_lcdclk_frequency_10khz);
126
a8fa3f0c NP	127	#ifdef CONFIG_PM
a8fa3f0c NP	128
8775420d TP	129	void pxa_cpu_pm_enter(suspend_state_t state)
	130	{
	131	extern void pxa_cpu_standby(void);
	132	extern void pxa_cpu_suspend(unsigned int);
	133	extern void pxa_cpu_resume(void);
	134
26705ca4	135	if (state == PM_SUSPEND_STANDBY)
1f750a78	136	CKEN = (1 << CKEN_MEMC) \| (1 << CKEN_OSTIMER) \| (1 << CKEN_LCD) \| (1 << CKEN_PWM0);
26705ca4	137	else
1f750a78	138	CKEN = (1 << CKEN_MEMC) \| (1 << CKEN_OSTIMER);
8775420d TP	139
	140	/* ensure voltage-change sequencer not initiated, which hangs */
	141	PCFR &= ~PCFR_FVC;
	142
	143	/* Clear edge-detect status register. */
	144	PEDR = 0xDF12FE1B;
	145
	146	switch (state) {
26705ca4 TP	147	case PM_SUSPEND_STANDBY:
	148	pxa_cpu_standby();
	149	break;
8775420d TP	150	case PM_SUSPEND_MEM:
	151	/* set resume return address */
	152	PSPR = virt_to_phys(pxa_cpu_resume);
80a18573	153	pxa_cpu_suspend(PWRMODE_SLEEP);
8775420d TP	154	break;
	155	}
	156	}
1da177e4	157
88dfe98c RK	158	static int pxa27x_pm_valid(suspend_state_t state)
	159	{
	160	return state == PM_SUSPEND_MEM \|\| state == PM_SUSPEND_STANDBY;
	161	}
	162
e176bb05	163	static struct pm_ops pxa27x_pm_ops = {
e176bb05	164	.enter = pxa_pm_enter,
88dfe98c	165	.valid = pxa27x_pm_valid,
e176bb05	166	};
a8fa3f0c NP	167	#endif
a8fa3f0c NP	168
1da177e4 LT	169	/*
	170	* device registration specific to PXA27x.
	171	*/
	172
	173	static u64 pxa27x_dmamask = 0xffffffffUL;
	174
	175	static struct resource pxa27x_ohci_resources[] = {
	176	[0] = {
	177	.start = 0x4C000000,
	178	.end = 0x4C00ff6f,
	179	.flags = IORESOURCE_MEM,
	180	},
	181	[1] = {
	182	.start = IRQ_USBH1,
	183	.end = IRQ_USBH1,
	184	.flags = IORESOURCE_IRQ,
	185	},
	186	};
	187
34f3231f	188	static struct platform_device pxaohci_device = {
1da177e4 LT	189	.name = "pxa27x-ohci",
	190	.id = -1,
	191	.dev = {
	192	.dma_mask = &pxa27x_dmamask,
	193	.coherent_dma_mask = 0xffffffff,
	194	},
	195	.num_resources = ARRAY_SIZE(pxa27x_ohci_resources),
	196	.resource = pxa27x_ohci_resources,
	197	};
	198
81f280e2 RP	199	void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
81f280e2 RP	200	{
34f3231f	201	pxaohci_device.dev.platform_data = info;
81f280e2 RP	202	}
81f280e2 RP	203
34f3231f RK	204	static struct resource i2c_power_resources[] = {
	205	{
	206	.start = 0x40f00180,
	207	.end = 0x40f001a3,
	208	.flags = IORESOURCE_MEM,
	209	}, {
	210	.start = IRQ_PWRI2C,
	211	.end = IRQ_PWRI2C,
	212	.flags = IORESOURCE_IRQ,
	213	},
	214	};
	215
	216	static struct platform_device pxai2c_power_device = {
	217	.name = "pxa2xx-i2c",
	218	.id = 1,
	219	.resource = i2c_power_resources,
	220	.num_resources = ARRAY_SIZE(i2c_power_resources),
	221	};
	222
1da177e4	223	static struct platform_device *devices[] __initdata = {
34f3231f RK	224	&pxamci_device,
	225	&pxaudc_device,
	226	&pxafb_device,
	227	&ffuart_device,
	228	&btuart_device,
	229	&stuart_device,
	230	&pxai2c_device,
	231	&pxai2c_power_device,
	232	&pxai2s_device,
	233	&pxaficp_device,
	234	&pxartc_device,
	235	&pxaohci_device,
1da177e4 LT	236	};
1da177e4 LT	237
cd49104d EM	238	void __init pxa27x_init_irq(void)
	239	{
	240	pxa_init_irq_low();
	241	pxa_init_irq_high();
	242	pxa_init_irq_gpio(128);
	243	}
	244
1da177e4 LT	245	static int __init pxa27x_init(void)
1da177e4 LT	246	{
e176bb05 RK	247	int ret = 0;
e176bb05 RK	248	if (cpu_is_pxa27x()) {
f53f066c EM	249	if ((ret = pxa_init_dma(32)))
f53f066c EM	250	return ret;
e176bb05 RK	251	#ifdef CONFIG_PM
	252	pm_set_ops(&pxa27x_pm_ops);
	253	#endif
	254	ret = platform_add_devices(devices, ARRAY_SIZE(devices));
	255	}
	256	return ret;
1da177e4 LT	257	}
	258
	259	subsys_initcall(pxa27x_init);