[deliverable/linux.git] / arch / arm / mach-pxa / pxa27x.c

/*
 *  linux/arch/arm/mach-pxa/pxa27x.c
 *
 *  Author:	Nicolas Pitre
 *  Created:	Nov 05, 2002
 *  Copyright:	MontaVista Software Inc.
 *
 * Code specific to PXA27x aka Bulverde.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pm.h>
#include <linux/platform_device.h>

#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/arch/irqs.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/ohci.h>
#include <asm/arch/pm.h>

#include "generic.h"

/* Crystal clock: 13MHz */
#define BASE_CLK	13000000

/*
 * Get the clock frequency as reflected by CCSR and the turbo flag.
 * We assume these values have been applied via a fcs.
 * If info is not 0 we also display the current settings.
 */
unsigned int get_clk_frequency_khz( int info)
{
	unsigned long ccsr, clkcfg;
	unsigned int l, L, m, M, n2, N, S;
       	int cccr_a, t, ht, b;

	ccsr = CCSR;
	cccr_a = CCCR & (1 << 25);

	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	t  = clkcfg & (1 << 0);
	ht = clkcfg & (1 << 2);
	b  = clkcfg & (1 << 3);

	l  = ccsr & 0x1f;
	n2 = (ccsr>>7) & 0xf;
	m  = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;

	L  = l * BASE_CLK;
	N  = (L * n2) / 2;
	M  = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	S  = (b) ? L : (L/2);

	if (info) {
		printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
			L / 1000000, (L % 1000000) / 10000, l );
		printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
			N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
			(t) ? "" : "in" );
		printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
			M / 1000000, (M % 1000000) / 10000, m );
		printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
			S / 1000000, (S % 1000000) / 10000 );
	}

	return (t) ? (N/1000) : (L/1000);
}

/*
 * Return the current mem clock frequency in units of 10kHz as
 * reflected by CCCR[A], B, and L
 */
unsigned int get_memclk_frequency_10khz(void)
{
	unsigned long ccsr, clkcfg;
	unsigned int l, L, m, M;
       	int cccr_a, b;

	ccsr = CCSR;
	cccr_a = CCCR & (1 << 25);

	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	b = clkcfg & (1 << 3);

	l = ccsr & 0x1f;
	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;

	L = l * BASE_CLK;
	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));

	return (M / 10000);
}

/*
 * Return the current LCD clock frequency in units of 10kHz as
 */
unsigned int get_lcdclk_frequency_10khz(void)
{
	unsigned long ccsr;
	unsigned int l, L, k, K;

	ccsr = CCSR;

	l = ccsr & 0x1f;
	k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;

	L = l * BASE_CLK;
	K = L / k;

	return (K / 10000);
}

EXPORT_SYMBOL(get_clk_frequency_khz);
EXPORT_SYMBOL(get_memclk_frequency_10khz);
EXPORT_SYMBOL(get_lcdclk_frequency_10khz);

#ifdef CONFIG_PM

void pxa_cpu_pm_enter(suspend_state_t state)
{
	extern void pxa_cpu_standby(void);
	extern void pxa_cpu_suspend(unsigned int);
	extern void pxa_cpu_resume(void);

	if (state == PM_SUSPEND_STANDBY)
		CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER) | (1 << CKEN_LCD) | (1 << CKEN_PWM0);
	else
		CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER);

	/* ensure voltage-change sequencer not initiated, which hangs */
	PCFR &= ~PCFR_FVC;

	/* Clear edge-detect status register. */
	PEDR = 0xDF12FE1B;

	switch (state) {
	case PM_SUSPEND_STANDBY:
		pxa_cpu_standby();
		break;
	case PM_SUSPEND_MEM:
		/* set resume return address */
		PSPR = virt_to_phys(pxa_cpu_resume);
		pxa_cpu_suspend(PWRMODE_SLEEP);
		break;
	}
}

static int pxa27x_pm_valid(suspend_state_t state)
{
	return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
}

static struct pm_ops pxa27x_pm_ops = {
	.enter		= pxa_pm_enter,
	.valid		= pxa27x_pm_valid,
};
#endif

/*
 * device registration specific to PXA27x.
 */

static u64 pxa27x_dmamask = 0xffffffffUL;

static struct resource pxa27x_ohci_resources[] = {
	[0] = {
		.start  = 0x4C000000,
		.end    = 0x4C00ff6f,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = IRQ_USBH1,
		.end    = IRQ_USBH1,
		.flags  = IORESOURCE_IRQ,
	},
};

static struct platform_device ohci_device = {
	.name		= "pxa27x-ohci",
	.id		= -1,
	.dev		= {
		.dma_mask = &pxa27x_dmamask,
		.coherent_dma_mask = 0xffffffff,
	},
	.num_resources  = ARRAY_SIZE(pxa27x_ohci_resources),
	.resource       = pxa27x_ohci_resources,
};

void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
{
	ohci_device.dev.platform_data = info;
}

static struct platform_device *devices[] __initdata = {
	&ohci_device,
};

void __init pxa27x_init_irq(void)
{
	pxa_init_irq_low();
	pxa_init_irq_high();
	pxa_init_irq_gpio(128);
}

static int __init pxa27x_init(void)
{
	int ret = 0;
	if (cpu_is_pxa27x()) {
#ifdef CONFIG_PM
		pm_set_ops(&pxa27x_pm_ops);
#endif
		ret = platform_add_devices(devices, ARRAY_SIZE(devices));
	}
	return ret;
}

subsys_initcall(pxa27x_init);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-pxa/pxa27x.c
	3	*
	4	* Author: Nicolas Pitre
	5	* Created: Nov 05, 2002
	6	* Copyright: MontaVista Software Inc.
	7	*
	8	* Code specific to PXA27x aka Bulverde.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
1da177e4 LT	14	#include <linux/module.h>
	15	#include <linux/kernel.h>
	16	#include <linux/init.h>
	17	#include <linux/pm.h>
d052d1be	18	#include <linux/platform_device.h>
1da177e4 LT	19
	20	#include <asm/hardware.h>
	21	#include <asm/irq.h>
cd49104d	22	#include <asm/arch/irqs.h>
1da177e4	23	#include <asm/arch/pxa-regs.h>
81f280e2	24	#include <asm/arch/ohci.h>
e176bb05	25	#include <asm/arch/pm.h>
1da177e4 LT	26
	27	#include "generic.h"
	28
	29	/* Crystal clock: 13MHz */
	30	#define BASE_CLK 13000000
	31
	32	/*
	33	* Get the clock frequency as reflected by CCSR and the turbo flag.
	34	* We assume these values have been applied via a fcs.
	35	* If info is not 0 we also display the current settings.
	36	*/
	37	unsigned int get_clk_frequency_khz( int info)
	38	{
	39	unsigned long ccsr, clkcfg;
	40	unsigned int l, L, m, M, n2, N, S;
	41	int cccr_a, t, ht, b;
	42
	43	ccsr = CCSR;
	44	cccr_a = CCCR & (1 << 25);
	45
	46	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	47	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
afe5df20	48	t = clkcfg & (1 << 0);
1da177e4 LT	49	ht = clkcfg & (1 << 2);
	50	b = clkcfg & (1 << 3);
	51
	52	l = ccsr & 0x1f;
	53	n2 = (ccsr>>7) & 0xf;
	54	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
	55
	56	L = l * BASE_CLK;
	57	N = (L * n2) / 2;
	58	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	59	S = (b) ? L : (L/2);
	60
	61	if (info) {
	62	printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
	63	L / 1000000, (L % 1000000) / 10000, l );
	64	printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
	65	N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
	66	(t) ? "" : "in" );
	67	printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
	68	M / 1000000, (M % 1000000) / 10000, m );
	69	printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
	70	S / 1000000, (S % 1000000) / 10000 );
	71	}
	72
	73	return (t) ? (N/1000) : (L/1000);
	74	}
	75
	76	/*
	77	* Return the current mem clock frequency in units of 10kHz as
	78	* reflected by CCCR[A], B, and L
	79	*/
	80	unsigned int get_memclk_frequency_10khz(void)
	81	{
	82	unsigned long ccsr, clkcfg;
	83	unsigned int l, L, m, M;
	84	int cccr_a, b;
	85
	86	ccsr = CCSR;
	87	cccr_a = CCCR & (1 << 25);
	88
	89	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
	90	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
	91	b = clkcfg & (1 << 3);
	92
	93	l = ccsr & 0x1f;
	94	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
	95
	96	L = l * BASE_CLK;
	97	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
	98
	99	return (M / 10000);
	100	}
	101
	102	/*
	103	* Return the current LCD clock frequency in units of 10kHz as
	104	*/
	105	unsigned int get_lcdclk_frequency_10khz(void)
	106	{
	107	unsigned long ccsr;
	108	unsigned int l, L, k, K;
	109
	110	ccsr = CCSR;
	111
	112	l = ccsr & 0x1f;
113	k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
114
115	L = l * BASE_CLK;
116	K = L / k;
117
118	return (K / 10000);
119	}
120
121	EXPORT_SYMBOL(get_clk_frequency_khz);
122	EXPORT_SYMBOL(get_memclk_frequency_10khz);
123	EXPORT_SYMBOL(get_lcdclk_frequency_10khz);
124
a8fa3f0c NP	125	#ifdef CONFIG_PM
a8fa3f0c NP	126
8775420d TP	127	void pxa_cpu_pm_enter(suspend_state_t state)
	128	{
	129	extern void pxa_cpu_standby(void);
	130	extern void pxa_cpu_suspend(unsigned int);
	131	extern void pxa_cpu_resume(void);
	132
26705ca4	133	if (state == PM_SUSPEND_STANDBY)
1f750a78	134	CKEN = (1 << CKEN_MEMC) \| (1 << CKEN_OSTIMER) \| (1 << CKEN_LCD) \| (1 << CKEN_PWM0);
26705ca4	135	else
1f750a78	136	CKEN = (1 << CKEN_MEMC) \| (1 << CKEN_OSTIMER);
8775420d TP	137
	138	/* ensure voltage-change sequencer not initiated, which hangs */
	139	PCFR &= ~PCFR_FVC;
	140
	141	/* Clear edge-detect status register. */
	142	PEDR = 0xDF12FE1B;
	143
	144	switch (state) {
26705ca4 TP	145	case PM_SUSPEND_STANDBY:
	146	pxa_cpu_standby();
	147	break;
8775420d TP	148	case PM_SUSPEND_MEM:
	149	/* set resume return address */
	150	PSPR = virt_to_phys(pxa_cpu_resume);
80a18573	151	pxa_cpu_suspend(PWRMODE_SLEEP);
8775420d TP	152	break;
	153	}
	154	}
1da177e4	155
88dfe98c RK	156	static int pxa27x_pm_valid(suspend_state_t state)
	157	{
	158	return state == PM_SUSPEND_MEM \|\| state == PM_SUSPEND_STANDBY;
	159	}
	160
e176bb05	161	static struct pm_ops pxa27x_pm_ops = {
e176bb05	162	.enter = pxa_pm_enter,
88dfe98c	163	.valid = pxa27x_pm_valid,
e176bb05	164	};
a8fa3f0c NP	165	#endif
a8fa3f0c NP	166
1da177e4 LT	167	/*
	168	* device registration specific to PXA27x.
	169	*/
	170
	171	static u64 pxa27x_dmamask = 0xffffffffUL;
	172
	173	static struct resource pxa27x_ohci_resources[] = {
	174	[0] = {
	175	.start = 0x4C000000,
	176	.end = 0x4C00ff6f,
	177	.flags = IORESOURCE_MEM,
	178	},
	179	[1] = {
	180	.start = IRQ_USBH1,
	181	.end = IRQ_USBH1,
	182	.flags = IORESOURCE_IRQ,
	183	},
	184	};
	185
	186	static struct platform_device ohci_device = {
	187	.name = "pxa27x-ohci",
	188	.id = -1,
	189	.dev = {
	190	.dma_mask = &pxa27x_dmamask,
	191	.coherent_dma_mask = 0xffffffff,
	192	},
	193	.num_resources = ARRAY_SIZE(pxa27x_ohci_resources),
	194	.resource = pxa27x_ohci_resources,
	195	};
	196
81f280e2 RP	197	void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
	198	{
	199	ohci_device.dev.platform_data = info;
	200	}
	201
1da177e4 LT	202	static struct platform_device *devices[] __initdata = {
	203	&ohci_device,
	204	};
	205
cd49104d EM	206	void __init pxa27x_init_irq(void)
	207	{
	208	pxa_init_irq_low();
	209	pxa_init_irq_high();
	210	pxa_init_irq_gpio(128);
	211	}
	212
1da177e4 LT	213	static int __init pxa27x_init(void)
1da177e4 LT	214	{
e176bb05 RK	215	int ret = 0;
	216	if (cpu_is_pxa27x()) {
	217	#ifdef CONFIG_PM
	218	pm_set_ops(&pxa27x_pm_ops);
	219	#endif
	220	ret = platform_add_devices(devices, ARRAY_SIZE(devices));
	221	}
	222	return ret;
1da177e4 LT	223	}
	224
	225	subsys_initcall(pxa27x_init);