[deliverable/linux.git] / arch / arm / mach-pxa / pxa3xx.c

/*
 * linux/arch/arm/mach-pxa/pxa3xx.c
 *
 * code specific to pxa3xx aka Monahans
 *
 * Copyright (C) 2006 Marvell International Ltd.
 *
 * 2007-09-02: eric miao <eric.miao@marvell.com>
 *             initial version
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pm.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/sysdev.h>

#include <mach/hardware.h>
#include <mach/pxa3xx-regs.h>
#include <mach/reset.h>
#include <mach/ohci.h>
#include <mach/pm.h>
#include <mach/dma.h>
#include <mach/ssp.h>
#include <mach/i2c.h>

#include "generic.h"
#include "devices.h"
#include "clock.h"

/* Crystal clock: 13MHz */
#define BASE_CLK	13000000

/* Ring Oscillator Clock: 60MHz */
#define RO_CLK		60000000

#define ACCR_D0CS	(1 << 26)
#define ACCR_PCCE	(1 << 11)

/* crystal frequency to static memory controller multiplier (SMCFS) */
static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };

/* crystal frequency to HSIO bus frequency multiplier (HSS) */
static unsigned char hss_mult[4] = { 8, 12, 16, 0 };

/*
 * Get the clock frequency as reflected by CCSR and the turbo flag.
 * We assume these values have been applied via a fcs.
 * If info is not 0 we also display the current settings.
 */
unsigned int pxa3xx_get_clk_frequency_khz(int info)
{
	unsigned long acsr, xclkcfg;
	unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;

	/* Read XCLKCFG register turbo bit */
	__asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
	t = xclkcfg & 0x1;

	acsr = ACSR;

	xl  = acsr & 0x1f;
	xn  = (acsr >> 8) & 0x7;
	hss = (acsr >> 14) & 0x3;

	XL = xl * BASE_CLK;
	XN = xn * XL;

	ro = acsr & ACCR_D0CS;

	CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
	HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;

	if (info) {
		pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
			RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
			(ro) ? "" : "in");
		pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
			XL / 1000000, (XL % 1000000) / 10000, xl);
		pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
			XN / 1000000, (XN % 1000000) / 10000, xn,
			(t) ? "" : "in");
		pr_info("HSIO bus clock: %d.%02dMHz\n",
			HSS / 1000000, (HSS % 1000000) / 10000);
	}

	return CLK / 1000;
}

/*
 * Return the current static memory controller clock frequency
 * in units of 10kHz
 */
unsigned int pxa3xx_get_memclk_frequency_10khz(void)
{
	unsigned long acsr;
	unsigned int smcfs, clk = 0;

	acsr = ACSR;

	smcfs = (acsr >> 23) & 0x7;
	clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;

	return (clk / 10000);
}

void pxa3xx_clear_reset_status(unsigned int mask)
{
	/* RESET_STATUS_* has a 1:1 mapping with ARSR */
	ARSR = mask;
}

/*
 * Return the current AC97 clock frequency.
 */
static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
{
	unsigned long rate = 312000000;
	unsigned long ac97_div;

	ac97_div = AC97_DIV;

	/* This may loose precision for some rates but won't for the
	 * standard 24.576MHz.
	 */
	rate /= (ac97_div >> 12) & 0x7fff;
	rate *= (ac97_div & 0xfff);

	return rate;
}

/*
 * Return the current HSIO bus clock frequency
 */
static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
{
	unsigned long acsr;
	unsigned int hss, hsio_clk;

	acsr = ACSR;

	hss = (acsr >> 14) & 0x3;
	hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;

	return hsio_clk;
}

void clk_pxa3xx_cken_enable(struct clk *clk)
{
	unsigned long mask = 1ul << (clk->cken & 0x1f);

	if (clk->cken < 32)
		CKENA |= mask;
	else
		CKENB |= mask;
}

void clk_pxa3xx_cken_disable(struct clk *clk)
{
	unsigned long mask = 1ul << (clk->cken & 0x1f);

	if (clk->cken < 32)
		CKENA &= ~mask;
	else
		CKENB &= ~mask;
}

const struct clkops clk_pxa3xx_cken_ops = {
	.enable		= clk_pxa3xx_cken_enable,
	.disable	= clk_pxa3xx_cken_disable,
};

static const struct clkops clk_pxa3xx_hsio_ops = {
	.enable		= clk_pxa3xx_cken_enable,
	.disable	= clk_pxa3xx_cken_disable,
	.getrate	= clk_pxa3xx_hsio_getrate,
};

static const struct clkops clk_pxa3xx_ac97_ops = {
	.enable		= clk_pxa3xx_cken_enable,
	.disable	= clk_pxa3xx_cken_disable,
	.getrate	= clk_pxa3xx_ac97_getrate,
};

static void clk_pout_enable(struct clk *clk)
{
	OSCC |= OSCC_PEN;
}

static void clk_pout_disable(struct clk *clk)
{
	OSCC &= ~OSCC_PEN;
}

static const struct clkops clk_pout_ops = {
	.enable		= clk_pout_enable,
	.disable	= clk_pout_disable,
};

static void clk_dummy_enable(struct clk *clk)
{
}

static void clk_dummy_disable(struct clk *clk)
{
}

static const struct clkops clk_dummy_ops = {
	.enable		= clk_dummy_enable,
	.disable	= clk_dummy_disable,
};

static struct clk pxa3xx_clks[] = {
	{
		.name           = "CLK_POUT",
		.ops            = &clk_pout_ops,
		.rate           = 13000000,
		.delay          = 70,
	},

	/* Power I2C clock is always on */
	{
		.name		= "I2CCLK",
		.ops		= &clk_dummy_ops,
		.dev		= &pxa3xx_device_i2c_power.dev,
	},

	PXA3xx_CK("LCDCLK",  LCD,    &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
	PXA3xx_CK("CAMCLK",  CAMERA, &clk_pxa3xx_hsio_ops, NULL),
	PXA3xx_CK("AC97CLK", AC97,   &clk_pxa3xx_ac97_ops, NULL),

	PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
	PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
	PXA3xx_CKEN("UARTCLK", STUART, 14857000, 1, NULL),

	PXA3xx_CKEN("I2CCLK", I2C,  32842000, 0, &pxa_device_i2c.dev),
	PXA3xx_CKEN("UDCCLK", UDC,  48000000, 5, &pxa27x_device_udc.dev),
	PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev),
	PXA3xx_CKEN("KBDCLK", KEYPAD,  32768, 0, &pxa27x_device_keypad.dev),

	PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
	PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
	PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
	PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev),
	PXA3xx_CKEN("PWMCLK", PWM0, 13000000, 0, &pxa27x_device_pwm0.dev),
	PXA3xx_CKEN("PWMCLK", PWM1, 13000000, 0, &pxa27x_device_pwm1.dev),

	PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev),
	PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev),
};

#ifdef CONFIG_PM

#define ISRAM_START	0x5c000000
#define ISRAM_SIZE	SZ_256K

static void __iomem *sram;
static unsigned long wakeup_src;

#define SAVE(x)		sleep_save[SLEEP_SAVE_##x] = x
#define RESTORE(x)	x = sleep_save[SLEEP_SAVE_##x]

enum {	SLEEP_SAVE_CKENA,
	SLEEP_SAVE_CKENB,
	SLEEP_SAVE_ACCR,

	SLEEP_SAVE_COUNT,
};

static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
{
	SAVE(CKENA);
	SAVE(CKENB);
	SAVE(ACCR);
}

static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
{
	RESTORE(ACCR);
	RESTORE(CKENA);
	RESTORE(CKENB);
}

/*
 * Enter a standby mode (S0D1C2 or S0D2C2).  Upon wakeup, the dynamic
 * memory controller has to be reinitialised, so we place some code
 * in the SRAM to perform this function.
 *
 * We disable FIQs across the standby - otherwise, we might receive a
 * FIQ while the SDRAM is unavailable.
 */
static void pxa3xx_cpu_standby(unsigned int pwrmode)
{
	extern const char pm_enter_standby_start[], pm_enter_standby_end[];
	void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);

	memcpy_toio(sram + 0x8000, pm_enter_standby_start,
		    pm_enter_standby_end - pm_enter_standby_start);

	AD2D0SR = ~0;
	AD2D1SR = ~0;
	AD2D0ER = wakeup_src;
	AD2D1ER = 0;
	ASCR = ASCR;
	ARSR = ARSR;

	local_fiq_disable();
	fn(pwrmode);
	local_fiq_enable();

	AD2D0ER = 0;
	AD2D1ER = 0;
}

/*
 * NOTE:  currently, the OBM (OEM Boot Module) binary comes along with
 * PXA3xx development kits assumes that the resuming process continues
 * with the address stored within the first 4 bytes of SDRAM. The PSPR
 * register is used privately by BootROM and OBM, and _must_ be set to
 * 0x5c014000 for the moment.
 */
static void pxa3xx_cpu_pm_suspend(void)
{
	volatile unsigned long *p = (volatile void *)0xc0000000;
	unsigned long saved_data = *p;

	extern void pxa3xx_cpu_suspend(void);
	extern void pxa3xx_cpu_resume(void);

	/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
	CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
	CKENB |= 1 << (CKEN_HSIO2 & 0x1f);

	/* clear and setup wakeup source */
	AD3SR = ~0;
	AD3ER = wakeup_src;
	ASCR = ASCR;
	ARSR = ARSR;

	PCFR |= (1u << 13);			/* L1_DIS */
	PCFR &= ~((1u << 12) | (1u << 1));	/* L0_EN | SL_ROD */

	PSPR = 0x5c014000;

	/* overwrite with the resume address */
	*p = virt_to_phys(pxa3xx_cpu_resume);

	pxa3xx_cpu_suspend();

	*p = saved_data;

	AD3ER = 0;
}

static void pxa3xx_cpu_pm_enter(suspend_state_t state)
{
	/*
	 * Don't sleep if no wakeup sources are defined
	 */
	if (wakeup_src == 0) {
		printk(KERN_ERR "Not suspending: no wakeup sources\n");
		return;
	}

	switch (state) {
	case PM_SUSPEND_STANDBY:
		pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
		break;

	case PM_SUSPEND_MEM:
		pxa3xx_cpu_pm_suspend();
		break;
	}
}

static int pxa3xx_cpu_pm_valid(suspend_state_t state)
{
	return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
}

static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
	.save_count	= SLEEP_SAVE_COUNT,
	.save		= pxa3xx_cpu_pm_save,
	.restore	= pxa3xx_cpu_pm_restore,
	.valid		= pxa3xx_cpu_pm_valid,
	.enter		= pxa3xx_cpu_pm_enter,
};

static void __init pxa3xx_init_pm(void)
{
	sram = ioremap(ISRAM_START, ISRAM_SIZE);
	if (!sram) {
		printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
		return;
	}

	/*
	 * Since we copy wakeup code into the SRAM, we need to ensure
	 * that it is preserved over the low power modes.  Note: bit 8
	 * is undocumented in the developer manual, but must be set.
	 */
	AD1R |= ADXR_L2 | ADXR_R0;
	AD2R |= ADXR_L2 | ADXR_R0;
	AD3R |= ADXR_L2 | ADXR_R0;

	/*
	 * Clear the resume enable registers.
	 */
	AD1D0ER = 0;
	AD2D0ER = 0;
	AD2D1ER = 0;
	AD3ER = 0;

	pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
}

static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
{
	unsigned long flags, mask = 0;

	switch (irq) {
	case IRQ_SSP3:
		mask = ADXER_MFP_WSSP3;
		break;
	case IRQ_MSL:
		mask = ADXER_WMSL0;
		break;
	case IRQ_USBH2:
	case IRQ_USBH1:
		mask = ADXER_WUSBH;
		break;
	case IRQ_KEYPAD:
		mask = ADXER_WKP;
		break;
	case IRQ_AC97:
		mask = ADXER_MFP_WAC97;
		break;
	case IRQ_USIM:
		mask = ADXER_WUSIM0;
		break;
	case IRQ_SSP2:
		mask = ADXER_MFP_WSSP2;
		break;
	case IRQ_I2C:
		mask = ADXER_MFP_WI2C;
		break;
	case IRQ_STUART:
		mask = ADXER_MFP_WUART3;
		break;
	case IRQ_BTUART:
		mask = ADXER_MFP_WUART2;
		break;
	case IRQ_FFUART:
		mask = ADXER_MFP_WUART1;
		break;
	case IRQ_MMC:
		mask = ADXER_MFP_WMMC1;
		break;
	case IRQ_SSP:
		mask = ADXER_MFP_WSSP1;
		break;
	case IRQ_RTCAlrm:
		mask = ADXER_WRTC;
		break;
	case IRQ_SSP4:
		mask = ADXER_MFP_WSSP4;
		break;
	case IRQ_TSI:
		mask = ADXER_WTSI;
		break;
	case IRQ_USIM2:
		mask = ADXER_WUSIM1;
		break;
	case IRQ_MMC2:
		mask = ADXER_MFP_WMMC2;
		break;
	case IRQ_NAND:
		mask = ADXER_MFP_WFLASH;
		break;
	case IRQ_USB2:
		mask = ADXER_WUSB2;
		break;
	case IRQ_WAKEUP0:
		mask = ADXER_WEXTWAKE0;
		break;
	case IRQ_WAKEUP1:
		mask = ADXER_WEXTWAKE1;
		break;
	case IRQ_MMC3:
		mask = ADXER_MFP_GEN12;
		break;
	default:
		return -EINVAL;
	}

	local_irq_save(flags);
	if (on)
		wakeup_src |= mask;
	else
		wakeup_src &= ~mask;
	local_irq_restore(flags);

	return 0;
}
#else
static inline void pxa3xx_init_pm(void) {}
#define pxa3xx_set_wake	NULL
#endif

void __init pxa3xx_init_irq(void)
{
	/* enable CP6 access */
	u32 value;
	__asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
	value |= (1 << 6);
	__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));

	pxa_init_irq(56, pxa3xx_set_wake);
	pxa_init_gpio(128, NULL);
}

/*
 * device registration specific to PXA3xx.
 */

void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
{
	pxa_register_device(&pxa3xx_device_i2c_power, info);
}

static struct platform_device *devices[] __initdata = {
/*	&pxa_device_udc,	The UDC driver is PXA25x only */
	&pxa_device_ffuart,
	&pxa_device_btuart,
	&pxa_device_stuart,
	&pxa_device_i2s,
	&pxa_device_rtc,
	&pxa27x_device_ssp1,
	&pxa27x_device_ssp2,
	&pxa27x_device_ssp3,
	&pxa3xx_device_ssp4,
	&pxa27x_device_pwm0,
	&pxa27x_device_pwm1,
};

static struct sys_device pxa3xx_sysdev[] = {
	{
		.cls	= &pxa_irq_sysclass,
	}, {
		.cls	= &pxa3xx_mfp_sysclass,
	}, {
		.cls	= &pxa_gpio_sysclass,
	},
};

static int __init pxa3xx_init(void)
{
	int i, ret = 0;

	if (cpu_is_pxa3xx()) {

		reset_status = ARSR;

		/*
		 * clear RDH bit every time after reset
		 *
		 * Note: the last 3 bits DxS are write-1-to-clear so carefully
		 * preserve them here in case they will be referenced later
		 */
		ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);

		clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks));

		if ((ret = pxa_init_dma(32)))
			return ret;

		pxa3xx_init_pm();

		for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) {
			ret = sysdev_register(&pxa3xx_sysdev[i]);
			if (ret)
				pr_err("failed to register sysdev[%d]\n", i);
		}

		ret = platform_add_devices(devices, ARRAY_SIZE(devices));
	}

	return ret;
}

postcore_initcall(pxa3xx_init);
Commit	Line	Data
2c8086a5	1	/*
	2	* linux/arch/arm/mach-pxa/pxa3xx.c
	3	*
	4	* code specific to pxa3xx aka Monahans
	5	*
	6	* Copyright (C) 2006 Marvell International Ltd.
	7	*
e9bba8ee	8	* 2007-09-02: eric miao <eric.miao@marvell.com>
2c8086a5	9	* initial version
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#include <linux/module.h>
	17	#include <linux/kernel.h>
	18	#include <linux/init.h>
	19	#include <linux/pm.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/irq.h>
7b5dea12	22	#include <linux/io.h>
c0165504	23	#include <linux/sysdev.h>
2c8086a5	24
a09e64fb RK	25	#include <mach/hardware.h>
a09e64fb RK	26	#include <mach/pxa3xx-regs.h>
afd2fc02	27	#include <mach/reset.h>
a09e64fb RK	28	#include <mach/ohci.h>
	29	#include <mach/pm.h>
	30	#include <mach/dma.h>
	31	#include <mach/ssp.h>
14758220	32	#include <mach/i2c.h>
2c8086a5	33
	34	#include "generic.h"
	35	#include "devices.h"
	36	#include "clock.h"
	37
	38	/* Crystal clock: 13MHz */
	39	#define BASE_CLK 13000000
	40
	41	/* Ring Oscillator Clock: 60MHz */
	42	#define RO_CLK 60000000
	43
	44	#define ACCR_D0CS (1 << 26)
c4d1fb62	45	#define ACCR_PCCE (1 << 11)
2c8086a5	46
	47	/* crystal frequency to static memory controller multiplier (SMCFS) */
	48	static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
	49
	50	/* crystal frequency to HSIO bus frequency multiplier (HSS) */
	51	static unsigned char hss_mult[4] = { 8, 12, 16, 0 };
	52
	53	/*
	54	* Get the clock frequency as reflected by CCSR and the turbo flag.
	55	* We assume these values have been applied via a fcs.
	56	* If info is not 0 we also display the current settings.
	57	*/
	58	unsigned int pxa3xx_get_clk_frequency_khz(int info)
	59	{
	60	unsigned long acsr, xclkcfg;
	61	unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
	62
	63	/* Read XCLKCFG register turbo bit */
	64	__asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
	65	t = xclkcfg & 0x1;
	66
	67	acsr = ACSR;
	68
	69	xl = acsr & 0x1f;
	70	xn = (acsr >> 8) & 0x7;
	71	hss = (acsr >> 14) & 0x3;
	72
	73	XL = xl * BASE_CLK;
	74	XN = xn * XL;
	75
	76	ro = acsr & ACCR_D0CS;
	77
	78	CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
	79	HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
	80
	81	if (info) {
	82	pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
	83	RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
	84	(ro) ? "" : "in");
	85	pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
	86	XL / 1000000, (XL % 1000000) / 10000, xl);
	87	pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
	88	XN / 1000000, (XN % 1000000) / 10000, xn,
	89	(t) ? "" : "in");
	90	pr_info("HSIO bus clock: %d.%02dMHz\n",
	91	HSS / 1000000, (HSS % 1000000) / 10000);
	92	}
	93
6232be32	94	return CLK / 1000;
2c8086a5	95	}
	96
	97	/*
	98	* Return the current static memory controller clock frequency
	99	* in units of 10kHz
	100	*/
	101	unsigned int pxa3xx_get_memclk_frequency_10khz(void)
	102	{
	103	unsigned long acsr;
	104	unsigned int smcfs, clk = 0;
	105
	106	acsr = ACSR;
	107
	108	smcfs = (acsr >> 23) & 0x7;
	109	clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;
	110
	111	return (clk / 10000);
	112	}
	113
04fef228 EM	114	void pxa3xx_clear_reset_status(unsigned int mask)
	115	{
	116	/* RESET_STATUS_* has a 1:1 mapping with ARSR */
	117	ARSR = mask;
	118	}
	119
60bfe7fa MB	120	/*
	121	* Return the current AC97 clock frequency.
	122	*/
	123	static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
	124	{
	125	unsigned long rate = 312000000;
	126	unsigned long ac97_div;
	127
	128	ac97_div = AC97_DIV;
	129
	130	/* This may loose precision for some rates but won't for the
	131	* standard 24.576MHz.
	132	*/
	133	rate /= (ac97_div >> 12) & 0x7fff;
	134	rate *= (ac97_div & 0xfff);
	135
	136	return rate;
	137	}
	138
2c8086a5	139	/*
	140	* Return the current HSIO bus clock frequency
	141	*/
	142	static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
	143	{
	144	unsigned long acsr;
	145	unsigned int hss, hsio_clk;
	146
	147	acsr = ACSR;
	148
	149	hss = (acsr >> 14) & 0x3;
	150	hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
	151
	152	return hsio_clk;
	153	}
	154
7a2c5cb0	155	void clk_pxa3xx_cken_enable(struct clk *clk)
2c8086a5	156	{
	157	unsigned long mask = 1ul << (clk->cken & 0x1f);
	158
2c8086a5	159	if (clk->cken < 32)
	160	CKENA \|= mask;
	161	else
	162	CKENB \|= mask;
2c8086a5	163	}
2c8086a5	164
7a2c5cb0	165	void clk_pxa3xx_cken_disable(struct clk *clk)
2c8086a5	166	{
	167	unsigned long mask = 1ul << (clk->cken & 0x1f);
	168
2c8086a5	169	if (clk->cken < 32)
	170	CKENA &= ~mask;
	171	else
	172	CKENB &= ~mask;
2c8086a5	173	}
2c8086a5	174
7a2c5cb0	175	const struct clkops clk_pxa3xx_cken_ops = {
2a0d7187	176	.enable = clk_pxa3xx_cken_enable,
	177	.disable = clk_pxa3xx_cken_disable,
	178	};
	179
2c8086a5	180	static const struct clkops clk_pxa3xx_hsio_ops = {
	181	.enable = clk_pxa3xx_cken_enable,
	182	.disable = clk_pxa3xx_cken_disable,
	183	.getrate = clk_pxa3xx_hsio_getrate,
	184	};
	185
60bfe7fa MB	186	static const struct clkops clk_pxa3xx_ac97_ops = {
	187	.enable = clk_pxa3xx_cken_enable,
	188	.disable = clk_pxa3xx_cken_disable,
	189	.getrate = clk_pxa3xx_ac97_getrate,
	190	};
	191
dcc88a17 MB	192	static void clk_pout_enable(struct clk *clk)
	193	{
	194	OSCC \|= OSCC_PEN;
	195	}
	196
	197	static void clk_pout_disable(struct clk *clk)
	198	{
	199	OSCC &= ~OSCC_PEN;
	200	}
	201
	202	static const struct clkops clk_pout_ops = {
	203	.enable = clk_pout_enable,
	204	.disable = clk_pout_disable,
	205	};
	206
9ba63c4f MR	207	static void clk_dummy_enable(struct clk *clk)
	208	{
	209	}
	210
	211	static void clk_dummy_disable(struct clk *clk)
	212	{
	213	}
	214
	215	static const struct clkops clk_dummy_ops = {
	216	.enable = clk_dummy_enable,
	217	.disable = clk_dummy_disable,
	218	};
	219
2c8086a5	220	static struct clk pxa3xx_clks[] = {
dcc88a17 MB	221	{
	222	.name = "CLK_POUT",
	223	.ops = &clk_pout_ops,
	224	.rate = 13000000,
	225	.delay = 70,
	226	},
	227
9ba63c4f MR	228	/* Power I2C clock is always on */
	229	{
	230	.name = "I2CCLK",
	231	.ops = &clk_dummy_ops,
	232	.dev = &pxa3xx_device_i2c_power.dev,
	233	},
	234
60bfe7fa MB	235	PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
	236	PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL),
	237	PXA3xx_CK("AC97CLK", AC97, &clk_pxa3xx_ac97_ops, NULL),
2c8086a5	238
2a0d7187	239	PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
	240	PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
	241	PXA3xx_CKEN("UARTCLK", STUART, 14857000, 1, NULL),
2c8086a5	242
2a0d7187	243	PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev),
7a857620	244	PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5, &pxa27x_device_udc.dev),
f92a629c	245	PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev),
37320980	246	PXA3xx_CKEN("KBDCLK", KEYPAD, 32768, 0, &pxa27x_device_keypad.dev),
d8e0db11	247
	248	PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
	249	PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
	250	PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
	251	PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev),
75540c1a	252	PXA3xx_CKEN("PWMCLK", PWM0, 13000000, 0, &pxa27x_device_pwm0.dev),
75540c1a	253	PXA3xx_CKEN("PWMCLK", PWM1, 13000000, 0, &pxa27x_device_pwm1.dev),
fafc9d3f BW	254
fafc9d3f BW	255	PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev),
8d33b055	256	PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev),
2c8086a5	257	};
2c8086a5	258
7b5dea12	259	#ifdef CONFIG_PM
7b5dea12 RK	260
	261	#define ISRAM_START 0x5c000000
	262	#define ISRAM_SIZE SZ_256K
	263
	264	static void __iomem *sram;
	265	static unsigned long wakeup_src;
	266
c4d1fb62	267	#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
c4d1fb62	268	#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
7b5dea12	269
649de51b	270	enum { SLEEP_SAVE_CKENA,
c4d1fb62	271	SLEEP_SAVE_CKENB,
c4d1fb62	272	SLEEP_SAVE_ACCR,
7b5dea12	273
649de51b	274	SLEEP_SAVE_COUNT,
c4d1fb62	275	};
	276
	277	static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
	278	{
	279	SAVE(CKENA);
	280	SAVE(CKENB);
	281	SAVE(ACCR);
7b5dea12 RK	282	}
	283
	284	static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
	285	{
c4d1fb62	286	RESTORE(ACCR);
	287	RESTORE(CKENA);
	288	RESTORE(CKENB);
7b5dea12 RK	289	}
	290
	291	/*
	292	* Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
	293	* memory controller has to be reinitialised, so we place some code
	294	* in the SRAM to perform this function.
	295	*
	296	* We disable FIQs across the standby - otherwise, we might receive a
	297	* FIQ while the SDRAM is unavailable.
	298	*/
	299	static void pxa3xx_cpu_standby(unsigned int pwrmode)
	300	{
	301	extern const char pm_enter_standby_start[], pm_enter_standby_end[];
	302	void (fn)(unsigned int) = (void __force )(sram + 0x8000);
	303
	304	memcpy_toio(sram + 0x8000, pm_enter_standby_start,
	305	pm_enter_standby_end - pm_enter_standby_start);
	306
	307	AD2D0SR = ~0;
	308	AD2D1SR = ~0;
	309	AD2D0ER = wakeup_src;
	310	AD2D1ER = 0;
	311	ASCR = ASCR;
	312	ARSR = ARSR;
	313
	314	local_fiq_disable();
	315	fn(pwrmode);
	316	local_fiq_enable();
	317
	318	AD2D0ER = 0;
	319	AD2D1ER = 0;
7b5dea12 RK	320	}
7b5dea12 RK	321
c4d1fb62	322	/*
	323	* NOTE: currently, the OBM (OEM Boot Module) binary comes along with
	324	* PXA3xx development kits assumes that the resuming process continues
	325	* with the address stored within the first 4 bytes of SDRAM. The PSPR
	326	* register is used privately by BootROM and OBM, and _must_ be set to
	327	* 0x5c014000 for the moment.
	328	*/
	329	static void pxa3xx_cpu_pm_suspend(void)
	330	{
	331	volatile unsigned long p = (volatile void )0xc0000000;
	332	unsigned long saved_data = *p;
	333
	334	extern void pxa3xx_cpu_suspend(void);
	335	extern void pxa3xx_cpu_resume(void);
	336
	337	/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
	338	CKENA \|= (1 << CKEN_BOOT) \| (1 << CKEN_TPM);
	339	CKENB \|= 1 << (CKEN_HSIO2 & 0x1f);
	340
	341	/* clear and setup wakeup source */
	342	AD3SR = ~0;
	343	AD3ER = wakeup_src;
	344	ASCR = ASCR;
	345	ARSR = ARSR;
	346
	347	PCFR \|= (1u << 13); /* L1_DIS */
	348	PCFR &= ~((1u << 12) \| (1u << 1)); /* L0_EN \| SL_ROD */
	349
	350	PSPR = 0x5c014000;
	351
	352	/* overwrite with the resume address */
	353	*p = virt_to_phys(pxa3xx_cpu_resume);
	354
	355	pxa3xx_cpu_suspend();
	356
	357	*p = saved_data;
	358
	359	AD3ER = 0;
	360	}
	361
7b5dea12 RK	362	static void pxa3xx_cpu_pm_enter(suspend_state_t state)
	363	{
	364	/*
	365	* Don't sleep if no wakeup sources are defined
	366	*/
b86a5da8 MB	367	if (wakeup_src == 0) {
b86a5da8 MB	368	printk(KERN_ERR "Not suspending: no wakeup sources\n");
7b5dea12	369	return;
b86a5da8	370	}
7b5dea12 RK	371
	372	switch (state) {
	373	case PM_SUSPEND_STANDBY:
	374	pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
	375	break;
	376
	377	case PM_SUSPEND_MEM:
c4d1fb62	378	pxa3xx_cpu_pm_suspend();
7b5dea12 RK	379	break;
	380	}
	381	}
	382
	383	static int pxa3xx_cpu_pm_valid(suspend_state_t state)
	384	{
	385	return state == PM_SUSPEND_MEM \|\| state == PM_SUSPEND_STANDBY;
	386	}
	387
	388	static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
649de51b	389	.save_count = SLEEP_SAVE_COUNT,
7b5dea12 RK	390	.save = pxa3xx_cpu_pm_save,
	391	.restore = pxa3xx_cpu_pm_restore,
	392	.valid = pxa3xx_cpu_pm_valid,
	393	.enter = pxa3xx_cpu_pm_enter,
2c8086a5	394	};
2c8086a5	395
7b5dea12 RK	396	static void __init pxa3xx_init_pm(void)
	397	{
	398	sram = ioremap(ISRAM_START, ISRAM_SIZE);
	399	if (!sram) {
	400	printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
	401	return;
	402	}
	403
	404	/*
	405	* Since we copy wakeup code into the SRAM, we need to ensure
	406	* that it is preserved over the low power modes. Note: bit 8
	407	* is undocumented in the developer manual, but must be set.
	408	*/
	409	AD1R \|= ADXR_L2 \| ADXR_R0;
	410	AD2R \|= ADXR_L2 \| ADXR_R0;
	411	AD3R \|= ADXR_L2 \| ADXR_R0;
	412
	413	/*
	414	* Clear the resume enable registers.
	415	*/
	416	AD1D0ER = 0;
	417	AD2D0ER = 0;
	418	AD2D1ER = 0;
	419	AD3ER = 0;
	420
	421	pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
	422	}
	423
	424	static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
	425	{
	426	unsigned long flags, mask = 0;
	427
	428	switch (irq) {
	429	case IRQ_SSP3:
	430	mask = ADXER_MFP_WSSP3;
	431	break;
	432	case IRQ_MSL:
	433	mask = ADXER_WMSL0;
	434	break;
	435	case IRQ_USBH2:
	436	case IRQ_USBH1:
	437	mask = ADXER_WUSBH;
	438	break;
	439	case IRQ_KEYPAD:
	440	mask = ADXER_WKP;
	441	break;
	442	case IRQ_AC97:
	443	mask = ADXER_MFP_WAC97;
	444	break;
	445	case IRQ_USIM:
	446	mask = ADXER_WUSIM0;
	447	break;
	448	case IRQ_SSP2:
	449	mask = ADXER_MFP_WSSP2;
	450	break;
	451	case IRQ_I2C:
	452	mask = ADXER_MFP_WI2C;
	453	break;
	454	case IRQ_STUART:
	455	mask = ADXER_MFP_WUART3;
	456	break;
	457	case IRQ_BTUART:
	458	mask = ADXER_MFP_WUART2;
	459	break;
460	case IRQ_FFUART:
461	mask = ADXER_MFP_WUART1;
462	break;
463	case IRQ_MMC:
464	mask = ADXER_MFP_WMMC1;
465	break;
466	case IRQ_SSP:
467	mask = ADXER_MFP_WSSP1;
468	break;
469	case IRQ_RTCAlrm:
470	mask = ADXER_WRTC;
471	break;
472	case IRQ_SSP4:
473	mask = ADXER_MFP_WSSP4;
474	break;
475	case IRQ_TSI:
476	mask = ADXER_WTSI;
477	break;
478	case IRQ_USIM2:
479	mask = ADXER_WUSIM1;
480	break;
481	case IRQ_MMC2:
482	mask = ADXER_MFP_WMMC2;
483	break;
484	case IRQ_NAND:
485	mask = ADXER_MFP_WFLASH;
486	break;
487	case IRQ_USB2:
488	mask = ADXER_WUSB2;
489	break;
490	case IRQ_WAKEUP0:
491	mask = ADXER_WEXTWAKE0;
492	break;
493	case IRQ_WAKEUP1:
494	mask = ADXER_WEXTWAKE1;
495	break;
496	case IRQ_MMC3:
497	mask = ADXER_MFP_GEN12;
498	break;
e1217707 MB	499	default:
e1217707 MB	500	return -EINVAL;
7b5dea12 RK	501	}
	502
	503	local_irq_save(flags);
	504	if (on)
	505	wakeup_src \|= mask;
	506	else
	507	wakeup_src &= ~mask;
	508	local_irq_restore(flags);
	509
	510	return 0;
	511	}
7b5dea12 RK	512	#else
7b5dea12 RK	513	static inline void pxa3xx_init_pm(void) {}
b9e25ace	514	#define pxa3xx_set_wake NULL
7b5dea12 RK	515	#endif
7b5dea12 RK	516
2c8086a5	517	void __init pxa3xx_init_irq(void)
	518	{
	519	/* enable CP6 access */
	520	u32 value;
	521	__asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
	522	value \|= (1 << 6);
	523	__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
	524
b9e25ace	525	pxa_init_irq(56, pxa3xx_set_wake);
b9e25ace	526	pxa_init_gpio(128, NULL);
2c8086a5	527	}
	528
	529	/*
	530	* device registration specific to PXA3xx.
	531	*/
	532
9ba63c4f MR	533	void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
9ba63c4f MR	534	{
14758220	535	pxa_register_device(&pxa3xx_device_i2c_power, info);
9ba63c4f MR	536	}
9ba63c4f MR	537
2c8086a5	538	static struct platform_device *devices[] __initdata = {
284d115e	539	/* &pxa_device_udc, The UDC driver is PXA25x only */
2c8086a5	540	&pxa_device_ffuart,
	541	&pxa_device_btuart,
	542	&pxa_device_stuart,
2c8086a5	543	&pxa_device_i2s,
2c8086a5	544	&pxa_device_rtc,
d8e0db11	545	&pxa27x_device_ssp1,
	546	&pxa27x_device_ssp2,
	547	&pxa27x_device_ssp3,
	548	&pxa3xx_device_ssp4,
75540c1a	549	&pxa27x_device_pwm0,
75540c1a	550	&pxa27x_device_pwm1,
2c8086a5	551	};
2c8086a5	552
c0165504	553	static struct sys_device pxa3xx_sysdev[] = {
c0165504	554	{
c0165504	555	.cls = &pxa_irq_sysclass,
4be35e23	556	}, {
4be35e23	557	.cls = &pxa3xx_mfp_sysclass,
16dfdbf0	558	}, {
16dfdbf0	559	.cls = &pxa_gpio_sysclass,
c0165504	560	},
	561	};
	562
2c8086a5	563	static int __init pxa3xx_init(void)
2c8086a5	564	{
c0165504	565	int i, ret = 0;
2c8086a5	566
2c8086a5	567	if (cpu_is_pxa3xx()) {
04fef228 EM	568
	569	reset_status = ARSR;
	570
86260f98 DK	571	/*
	572	* clear RDH bit every time after reset
	573	*
	574	* Note: the last 3 bits DxS are write-1-to-clear so carefully
	575	* preserve them here in case they will be referenced later
	576	*/
	577	ASCR &= ~(ASCR_RDH \| ASCR_D1S \| ASCR_D2S \| ASCR_D3S);
	578
2c8086a5	579	clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks));
	580
	581	if ((ret = pxa_init_dma(32)))
	582	return ret;
	583
7b5dea12 RK	584	pxa3xx_init_pm();
7b5dea12 RK	585
c0165504	586	for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) {
	587	ret = sysdev_register(&pxa3xx_sysdev[i]);
	588	if (ret)
	589	pr_err("failed to register sysdev[%d]\n", i);
	590	}
	591
	592	ret = platform_add_devices(devices, ARRAY_SIZE(devices));
2c8086a5	593	}
c0165504	594
c0165504	595	return ret;
2c8086a5	596	}
2c8086a5	597
1c104e0e	598	postcore_initcall(pxa3xx_init);