[deliverable/linux.git] / arch / arm / mach-pxa / pxa3xx.c

/*
 * linux/arch/arm/mach-pxa/pxa3xx.c
 *
 * code specific to pxa3xx aka Monahans
 *
 * Copyright (C) 2006 Marvell International Ltd.
 *
 * 2007-09-02: eric miao <eric.miao@marvell.com>
 *             initial version
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pm.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/sysdev.h>

#include <asm/mach/map.h>
#include <mach/hardware.h>
#include <mach/gpio.h>
#include <mach/pxa3xx-regs.h>
#include <mach/reset.h>
#include <mach/ohci.h>
#include <mach/pm.h>
#include <mach/dma.h>
#include <mach/regs-intc.h>
#include <mach/smemc.h>
#include <plat/i2c.h>

#include "generic.h"
#include "devices.h"
#include "clock.h"

#define PECR_IE(n)	((1 << ((n) * 2)) << 28)
#define PECR_IS(n)	((1 << ((n) * 2)) << 29)

static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);

static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops);
static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70);

static struct clk_lookup pxa3xx_clkregs[] = {
	INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
	/* Power I2C clock is always on */
	INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
	INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
	INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
	INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
	INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
	INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
	INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
	INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
	INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
};

#ifdef CONFIG_PM

#define ISRAM_START	0x5c000000
#define ISRAM_SIZE	SZ_256K

static void __iomem *sram;
static unsigned long wakeup_src;

/*
 * Enter a standby mode (S0D1C2 or S0D2C2).  Upon wakeup, the dynamic
 * memory controller has to be reinitialised, so we place some code
 * in the SRAM to perform this function.
 *
 * We disable FIQs across the standby - otherwise, we might receive a
 * FIQ while the SDRAM is unavailable.
 */
static void pxa3xx_cpu_standby(unsigned int pwrmode)
{
	extern const char pm_enter_standby_start[], pm_enter_standby_end[];
	void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);

	memcpy_toio(sram + 0x8000, pm_enter_standby_start,
		    pm_enter_standby_end - pm_enter_standby_start);

	AD2D0SR = ~0;
	AD2D1SR = ~0;
	AD2D0ER = wakeup_src;
	AD2D1ER = 0;
	ASCR = ASCR;
	ARSR = ARSR;

	local_fiq_disable();
	fn(pwrmode);
	local_fiq_enable();

	AD2D0ER = 0;
	AD2D1ER = 0;
}

/*
 * NOTE:  currently, the OBM (OEM Boot Module) binary comes along with
 * PXA3xx development kits assumes that the resuming process continues
 * with the address stored within the first 4 bytes of SDRAM. The PSPR
 * register is used privately by BootROM and OBM, and _must_ be set to
 * 0x5c014000 for the moment.
 */
static void pxa3xx_cpu_pm_suspend(void)
{
	volatile unsigned long *p = (volatile void *)0xc0000000;
	unsigned long saved_data = *p;

	extern void pxa3xx_cpu_suspend(void);
	extern void pxa3xx_cpu_resume(void);

	/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
	CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
	CKENB |= 1 << (CKEN_HSIO2 & 0x1f);

	/* clear and setup wakeup source */
	AD3SR = ~0;
	AD3ER = wakeup_src;
	ASCR = ASCR;
	ARSR = ARSR;

	PCFR |= (1u << 13);			/* L1_DIS */
	PCFR &= ~((1u << 12) | (1u << 1));	/* L0_EN | SL_ROD */

	PSPR = 0x5c014000;

	/* overwrite with the resume address */
	*p = virt_to_phys(pxa3xx_cpu_resume);

	pxa3xx_cpu_suspend();

	*p = saved_data;

	AD3ER = 0;
}

static void pxa3xx_cpu_pm_enter(suspend_state_t state)
{
	/*
	 * Don't sleep if no wakeup sources are defined
	 */
	if (wakeup_src == 0) {
		printk(KERN_ERR "Not suspending: no wakeup sources\n");
		return;
	}

	switch (state) {
	case PM_SUSPEND_STANDBY:
		pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
		break;

	case PM_SUSPEND_MEM:
		pxa3xx_cpu_pm_suspend();
		break;
	}
}

static int pxa3xx_cpu_pm_valid(suspend_state_t state)
{
	return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
}

static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
	.valid		= pxa3xx_cpu_pm_valid,
	.enter		= pxa3xx_cpu_pm_enter,
};

static void __init pxa3xx_init_pm(void)
{
	sram = ioremap(ISRAM_START, ISRAM_SIZE);
	if (!sram) {
		printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
		return;
	}

	/*
	 * Since we copy wakeup code into the SRAM, we need to ensure
	 * that it is preserved over the low power modes.  Note: bit 8
	 * is undocumented in the developer manual, but must be set.
	 */
	AD1R |= ADXR_L2 | ADXR_R0;
	AD2R |= ADXR_L2 | ADXR_R0;
	AD3R |= ADXR_L2 | ADXR_R0;

	/*
	 * Clear the resume enable registers.
	 */
	AD1D0ER = 0;
	AD2D0ER = 0;
	AD2D1ER = 0;
	AD3ER = 0;

	pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
}

static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
{
	unsigned long flags, mask = 0;

	switch (irq) {
	case IRQ_SSP3:
		mask = ADXER_MFP_WSSP3;
		break;
	case IRQ_MSL:
		mask = ADXER_WMSL0;
		break;
	case IRQ_USBH2:
	case IRQ_USBH1:
		mask = ADXER_WUSBH;
		break;
	case IRQ_KEYPAD:
		mask = ADXER_WKP;
		break;
	case IRQ_AC97:
		mask = ADXER_MFP_WAC97;
		break;
	case IRQ_USIM:
		mask = ADXER_WUSIM0;
		break;
	case IRQ_SSP2:
		mask = ADXER_MFP_WSSP2;
		break;
	case IRQ_I2C:
		mask = ADXER_MFP_WI2C;
		break;
	case IRQ_STUART:
		mask = ADXER_MFP_WUART3;
		break;
	case IRQ_BTUART:
		mask = ADXER_MFP_WUART2;
		break;
	case IRQ_FFUART:
		mask = ADXER_MFP_WUART1;
		break;
	case IRQ_MMC:
		mask = ADXER_MFP_WMMC1;
		break;
	case IRQ_SSP:
		mask = ADXER_MFP_WSSP1;
		break;
	case IRQ_RTCAlrm:
		mask = ADXER_WRTC;
		break;
	case IRQ_SSP4:
		mask = ADXER_MFP_WSSP4;
		break;
	case IRQ_TSI:
		mask = ADXER_WTSI;
		break;
	case IRQ_USIM2:
		mask = ADXER_WUSIM1;
		break;
	case IRQ_MMC2:
		mask = ADXER_MFP_WMMC2;
		break;
	case IRQ_NAND:
		mask = ADXER_MFP_WFLASH;
		break;
	case IRQ_USB2:
		mask = ADXER_WUSB2;
		break;
	case IRQ_WAKEUP0:
		mask = ADXER_WEXTWAKE0;
		break;
	case IRQ_WAKEUP1:
		mask = ADXER_WEXTWAKE1;
		break;
	case IRQ_MMC3:
		mask = ADXER_MFP_GEN12;
		break;
	default:
		return -EINVAL;
	}

	local_irq_save(flags);
	if (on)
		wakeup_src |= mask;
	else
		wakeup_src &= ~mask;
	local_irq_restore(flags);

	return 0;
}
#else
static inline void pxa3xx_init_pm(void) {}
#define pxa3xx_set_wake	NULL
#endif

static void pxa_ack_ext_wakeup(unsigned int irq)
{
	PECR |= PECR_IS(irq - IRQ_WAKEUP0);
}

static void pxa_mask_ext_wakeup(unsigned int irq)
{
	ICMR2 &= ~(1 << ((irq - PXA_IRQ(0)) & 0x1f));
	PECR &= ~PECR_IE(irq - IRQ_WAKEUP0);
}

static void pxa_unmask_ext_wakeup(unsigned int irq)
{
	ICMR2 |= 1 << ((irq - PXA_IRQ(0)) & 0x1f);
	PECR |= PECR_IE(irq - IRQ_WAKEUP0);
}

static int pxa_set_ext_wakeup_type(unsigned int irq, unsigned int flow_type)
{
	if (flow_type & IRQ_TYPE_EDGE_RISING)
		PWER |= 1 << (irq - IRQ_WAKEUP0);

	if (flow_type & IRQ_TYPE_EDGE_FALLING)
		PWER |= 1 << (irq - IRQ_WAKEUP0 + 2);

	return 0;
}

static struct irq_chip pxa_ext_wakeup_chip = {
	.name		= "WAKEUP",
	.ack		= pxa_ack_ext_wakeup,
	.mask		= pxa_mask_ext_wakeup,
	.unmask		= pxa_unmask_ext_wakeup,
	.set_type	= pxa_set_ext_wakeup_type,
};

static void __init pxa_init_ext_wakeup_irq(set_wake_t fn)
{
	int irq;

	for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
		set_irq_chip(irq, &pxa_ext_wakeup_chip);
		set_irq_handler(irq, handle_edge_irq);
		set_irq_flags(irq, IRQF_VALID);
	}

	pxa_ext_wakeup_chip.set_wake = fn;
}

void __init pxa3xx_init_irq(void)
{
	/* enable CP6 access */
	u32 value;
	__asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
	value |= (1 << 6);
	__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));

	pxa_init_irq(56, pxa3xx_set_wake);
	pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
	pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
}

static struct map_desc pxa3xx_io_desc[] __initdata = {
	{	/* Mem Ctl */
		.virtual	= SMEMC_VIRT,
		.pfn		= __phys_to_pfn(PXA3XX_SMEMC_BASE),
		.length		= 0x00200000,
		.type		= MT_DEVICE
	}
};

void __init pxa3xx_map_io(void)
{
	pxa_map_io();
	iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
	pxa3xx_get_clk_frequency_khz(1);
}

/*
 * device registration specific to PXA3xx.
 */

void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
{
	pxa_register_device(&pxa3xx_device_i2c_power, info);
}

static struct platform_device *devices[] __initdata = {
	&pxa27x_device_udc,
	&pxa_device_pmu,
	&pxa_device_i2s,
	&pxa_device_asoc_ssp1,
	&pxa_device_asoc_ssp2,
	&pxa_device_asoc_ssp3,
	&pxa_device_asoc_ssp4,
	&pxa_device_asoc_platform,
	&sa1100_device_rtc,
	&pxa_device_rtc,
	&pxa27x_device_ssp1,
	&pxa27x_device_ssp2,
	&pxa27x_device_ssp3,
	&pxa3xx_device_ssp4,
	&pxa27x_device_pwm0,
	&pxa27x_device_pwm1,
};

static struct sys_device pxa3xx_sysdev[] = {
	{
		.cls	= &pxa_irq_sysclass,
	}, {
		.cls	= &pxa3xx_mfp_sysclass,
	}, {
		.cls	= &pxa_gpio_sysclass,
	}, {
		.cls	= &pxa3xx_clock_sysclass,
	}
};

static int __init pxa3xx_init(void)
{
	int i, ret = 0;

	if (cpu_is_pxa3xx()) {

		reset_status = ARSR;

		/*
		 * clear RDH bit every time after reset
		 *
		 * Note: the last 3 bits DxS are write-1-to-clear so carefully
		 * preserve them here in case they will be referenced later
		 */
		ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);

		clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));

		if ((ret = pxa_init_dma(IRQ_DMA, 32)))
			return ret;

		pxa3xx_init_pm();

		for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) {
			ret = sysdev_register(&pxa3xx_sysdev[i]);
			if (ret)
				pr_err("failed to register sysdev[%d]\n", i);
		}

		ret = platform_add_devices(devices, ARRAY_SIZE(devices));
	}

	return ret;
}

postcore_initcall(pxa3xx_init);
Commit	Line	Data
2c8086a5	1	/*
	2	* linux/arch/arm/mach-pxa/pxa3xx.c
	3	*
	4	* code specific to pxa3xx aka Monahans
	5	*
	6	* Copyright (C) 2006 Marvell International Ltd.
	7	*
e9bba8ee	8	* 2007-09-02: eric miao <eric.miao@marvell.com>
2c8086a5	9	* initial version
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#include <linux/module.h>
	17	#include <linux/kernel.h>
	18	#include <linux/init.h>
	19	#include <linux/pm.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/irq.h>
7b5dea12	22	#include <linux/io.h>
c0165504	23	#include <linux/sysdev.h>
2c8086a5	24
851982c1	25	#include <asm/mach/map.h>
a09e64fb	26	#include <mach/hardware.h>
a58fbcd8	27	#include <mach/gpio.h>
a09e64fb	28	#include <mach/pxa3xx-regs.h>
afd2fc02	29	#include <mach/reset.h>
a09e64fb RK	30	#include <mach/ohci.h>
	31	#include <mach/pm.h>
	32	#include <mach/dma.h>
bf293aec	33	#include <mach/regs-intc.h>
ad68bb9f	34	#include <mach/smemc.h>
f0a83701	35	#include <plat/i2c.h>
2c8086a5	36
	37	#include "generic.h"
	38	#include "devices.h"
	39	#include "clock.h"
	40
bf293aec MR	41	#define PECR_IE(n) ((1 << ((n) * 2)) << 28)
	42	#define PECR_IS(n) ((1 << ((n) * 2)) << 29)
	43
8c3abc7d RK	44	static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
	45	static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
	46	static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
	47	static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
	48	static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
	49	static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
e68750ae	50	static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
8c3abc7d RK	51	static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
	52	static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
	53	static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
	54	static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
	55	static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
	56	static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
	57	static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
	58	static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
	59	static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
	60
2e8581e7	61	static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
c085052b	62	static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops);
2e8581e7 EM	63	static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
2e8581e7 EM	64	static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
4029813c	65	static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70);
2e8581e7	66
8c3abc7d RK	67	static struct clk_lookup pxa3xx_clkregs[] = {
	68	INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
	69	/* Power I2C clock is always on */
5c68b099	70	INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
8c3abc7d RK	71	INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
	72	INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
	73	INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
	74	INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
	75	INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
	76	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
	77	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
	78	INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
	79	INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
	80	INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
69f22be7	81	INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
8c3abc7d RK	82	INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
	83	INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
	84	INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
	85	INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
	86	INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
	87	INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
	88	INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
	89	INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
	90	INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
c085052b	91	INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
2c8086a5	92	};
2c8086a5	93
7b5dea12	94	#ifdef CONFIG_PM
7b5dea12 RK	95
	96	#define ISRAM_START 0x5c000000
	97	#define ISRAM_SIZE SZ_256K
	98
	99	static void __iomem *sram;
	100	static unsigned long wakeup_src;
	101
7b5dea12 RK	102	/*
	103	* Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
	104	* memory controller has to be reinitialised, so we place some code
	105	* in the SRAM to perform this function.
	106	*
	107	* We disable FIQs across the standby - otherwise, we might receive a
	108	* FIQ while the SDRAM is unavailable.
	109	*/
	110	static void pxa3xx_cpu_standby(unsigned int pwrmode)
	111	{
	112	extern const char pm_enter_standby_start[], pm_enter_standby_end[];
	113	void (fn)(unsigned int) = (void __force )(sram + 0x8000);
	114
	115	memcpy_toio(sram + 0x8000, pm_enter_standby_start,
	116	pm_enter_standby_end - pm_enter_standby_start);
	117
	118	AD2D0SR = ~0;
	119	AD2D1SR = ~0;
	120	AD2D0ER = wakeup_src;
	121	AD2D1ER = 0;
	122	ASCR = ASCR;
	123	ARSR = ARSR;
	124
	125	local_fiq_disable();
	126	fn(pwrmode);
	127	local_fiq_enable();
	128
	129	AD2D0ER = 0;
	130	AD2D1ER = 0;
7b5dea12 RK	131	}
7b5dea12 RK	132
c4d1fb62	133	/*
	134	* NOTE: currently, the OBM (OEM Boot Module) binary comes along with
	135	* PXA3xx development kits assumes that the resuming process continues
	136	* with the address stored within the first 4 bytes of SDRAM. The PSPR
	137	* register is used privately by BootROM and OBM, and _must_ be set to
	138	* 0x5c014000 for the moment.
	139	*/
	140	static void pxa3xx_cpu_pm_suspend(void)
	141	{
	142	volatile unsigned long p = (volatile void )0xc0000000;
	143	unsigned long saved_data = *p;
	144
	145	extern void pxa3xx_cpu_suspend(void);
	146	extern void pxa3xx_cpu_resume(void);
	147
	148	/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
	149	CKENA \|= (1 << CKEN_BOOT) \| (1 << CKEN_TPM);
	150	CKENB \|= 1 << (CKEN_HSIO2 & 0x1f);
	151
	152	/* clear and setup wakeup source */
	153	AD3SR = ~0;
	154	AD3ER = wakeup_src;
	155	ASCR = ASCR;
	156	ARSR = ARSR;
	157
	158	PCFR \|= (1u << 13); /* L1_DIS */
	159	PCFR &= ~((1u << 12) \| (1u << 1)); /* L0_EN \| SL_ROD */
	160
	161	PSPR = 0x5c014000;
	162
	163	/* overwrite with the resume address */
	164	*p = virt_to_phys(pxa3xx_cpu_resume);
	165
	166	pxa3xx_cpu_suspend();
	167
	168	*p = saved_data;
	169
	170	AD3ER = 0;
	171	}
	172
7b5dea12 RK	173	static void pxa3xx_cpu_pm_enter(suspend_state_t state)
	174	{
	175	/*
	176	* Don't sleep if no wakeup sources are defined
	177	*/
b86a5da8 MB	178	if (wakeup_src == 0) {
b86a5da8 MB	179	printk(KERN_ERR "Not suspending: no wakeup sources\n");
7b5dea12	180	return;
b86a5da8	181	}
7b5dea12 RK	182
	183	switch (state) {
	184	case PM_SUSPEND_STANDBY:
	185	pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
	186	break;
	187
	188	case PM_SUSPEND_MEM:
c4d1fb62	189	pxa3xx_cpu_pm_suspend();
7b5dea12 RK	190	break;
	191	}
	192	}
	193
	194	static int pxa3xx_cpu_pm_valid(suspend_state_t state)
	195	{
	196	return state == PM_SUSPEND_MEM \|\| state == PM_SUSPEND_STANDBY;
	197	}
	198
	199	static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
7b5dea12 RK	200	.valid = pxa3xx_cpu_pm_valid,
7b5dea12 RK	201	.enter = pxa3xx_cpu_pm_enter,
2c8086a5	202	};
2c8086a5	203
7b5dea12 RK	204	static void __init pxa3xx_init_pm(void)
	205	{
	206	sram = ioremap(ISRAM_START, ISRAM_SIZE);
	207	if (!sram) {
	208	printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
	209	return;
	210	}
	211
	212	/*
	213	* Since we copy wakeup code into the SRAM, we need to ensure
	214	* that it is preserved over the low power modes. Note: bit 8
	215	* is undocumented in the developer manual, but must be set.
	216	*/
	217	AD1R \|= ADXR_L2 \| ADXR_R0;
	218	AD2R \|= ADXR_L2 \| ADXR_R0;
	219	AD3R \|= ADXR_L2 \| ADXR_R0;
	220
	221	/*
	222	* Clear the resume enable registers.
	223	*/
	224	AD1D0ER = 0;
	225	AD2D0ER = 0;
	226	AD2D1ER = 0;
	227	AD3ER = 0;
	228
	229	pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
	230	}
	231
	232	static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
	233	{
	234	unsigned long flags, mask = 0;
	235
	236	switch (irq) {
	237	case IRQ_SSP3:
	238	mask = ADXER_MFP_WSSP3;
	239	break;
	240	case IRQ_MSL:
	241	mask = ADXER_WMSL0;
	242	break;
	243	case IRQ_USBH2:
	244	case IRQ_USBH1:
	245	mask = ADXER_WUSBH;
	246	break;
	247	case IRQ_KEYPAD:
	248	mask = ADXER_WKP;
	249	break;
	250	case IRQ_AC97:
	251	mask = ADXER_MFP_WAC97;
	252	break;
	253	case IRQ_USIM:
	254	mask = ADXER_WUSIM0;
	255	break;
	256	case IRQ_SSP2:
	257	mask = ADXER_MFP_WSSP2;
	258	break;
	259	case IRQ_I2C:
	260	mask = ADXER_MFP_WI2C;
	261	break;
	262	case IRQ_STUART:
	263	mask = ADXER_MFP_WUART3;
	264	break;
	265	case IRQ_BTUART:
	266	mask = ADXER_MFP_WUART2;
	267	break;
268	case IRQ_FFUART:
269	mask = ADXER_MFP_WUART1;
270	break;
271	case IRQ_MMC:
272	mask = ADXER_MFP_WMMC1;
273	break;
274	case IRQ_SSP:
275	mask = ADXER_MFP_WSSP1;
276	break;
277	case IRQ_RTCAlrm:
278	mask = ADXER_WRTC;
279	break;
280	case IRQ_SSP4:
281	mask = ADXER_MFP_WSSP4;
282	break;
283	case IRQ_TSI:
284	mask = ADXER_WTSI;
285	break;
286	case IRQ_USIM2:
287	mask = ADXER_WUSIM1;
288	break;
289	case IRQ_MMC2:
290	mask = ADXER_MFP_WMMC2;
291	break;
292	case IRQ_NAND:
293	mask = ADXER_MFP_WFLASH;
294	break;
295	case IRQ_USB2:
296	mask = ADXER_WUSB2;
297	break;
298	case IRQ_WAKEUP0:
299	mask = ADXER_WEXTWAKE0;
300	break;
301	case IRQ_WAKEUP1:
302	mask = ADXER_WEXTWAKE1;
303	break;
304	case IRQ_MMC3:
305	mask = ADXER_MFP_GEN12;
306	break;
e1217707 MB	307	default:
e1217707 MB	308	return -EINVAL;
7b5dea12 RK	309	}
	310
	311	local_irq_save(flags);
	312	if (on)
	313	wakeup_src \|= mask;
	314	else
	315	wakeup_src &= ~mask;
	316	local_irq_restore(flags);
	317
	318	return 0;
	319	}
7b5dea12 RK	320	#else
7b5dea12 RK	321	static inline void pxa3xx_init_pm(void) {}
b9e25ace	322	#define pxa3xx_set_wake NULL
7b5dea12 RK	323	#endif
7b5dea12 RK	324
bf293aec MR	325	static void pxa_ack_ext_wakeup(unsigned int irq)
	326	{
	327	PECR \|= PECR_IS(irq - IRQ_WAKEUP0);
	328	}
	329
	330	static void pxa_mask_ext_wakeup(unsigned int irq)
	331	{
	332	ICMR2 &= ~(1 << ((irq - PXA_IRQ(0)) & 0x1f));
	333	PECR &= ~PECR_IE(irq - IRQ_WAKEUP0);
	334	}
	335
	336	static void pxa_unmask_ext_wakeup(unsigned int irq)
	337	{
	338	ICMR2 \|= 1 << ((irq - PXA_IRQ(0)) & 0x1f);
	339	PECR \|= PECR_IE(irq - IRQ_WAKEUP0);
	340	}
	341
12882096 IG	342	static int pxa_set_ext_wakeup_type(unsigned int irq, unsigned int flow_type)
	343	{
	344	if (flow_type & IRQ_TYPE_EDGE_RISING)
	345	PWER \|= 1 << (irq - IRQ_WAKEUP0);
	346
	347	if (flow_type & IRQ_TYPE_EDGE_FALLING)
	348	PWER \|= 1 << (irq - IRQ_WAKEUP0 + 2);
	349
	350	return 0;
	351	}
	352
bf293aec MR	353	static struct irq_chip pxa_ext_wakeup_chip = {
	354	.name = "WAKEUP",
	355	.ack = pxa_ack_ext_wakeup,
	356	.mask = pxa_mask_ext_wakeup,
	357	.unmask = pxa_unmask_ext_wakeup,
12882096	358	.set_type = pxa_set_ext_wakeup_type,
bf293aec MR	359	};
	360
	361	static void __init pxa_init_ext_wakeup_irq(set_wake_t fn)
	362	{
	363	int irq;
	364
	365	for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
	366	set_irq_chip(irq, &pxa_ext_wakeup_chip);
	367	set_irq_handler(irq, handle_edge_irq);
	368	set_irq_flags(irq, IRQF_VALID);
	369	}
	370
	371	pxa_ext_wakeup_chip.set_wake = fn;
	372	}
	373
2c8086a5	374	void __init pxa3xx_init_irq(void)
	375	{
	376	/* enable CP6 access */
	377	u32 value;
	378	__asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
	379	value \|= (1 << 6);
	380	__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
	381
b9e25ace	382	pxa_init_irq(56, pxa3xx_set_wake);
bf293aec	383	pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
a58fbcd8	384	pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
2c8086a5	385	}
2c8086a5	386
851982c1 MV	387	static struct map_desc pxa3xx_io_desc[] __initdata = {
851982c1 MV	388	{ /* Mem Ctl */
ad68bb9f MV	389	.virtual = SMEMC_VIRT,
ad68bb9f MV	390	.pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE),
851982c1 MV	391	.length = 0x00200000,
	392	.type = MT_DEVICE
	393	}
	394	};
	395
	396	void __init pxa3xx_map_io(void)
	397	{
	398	pxa_map_io();
	399	iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
	400	pxa3xx_get_clk_frequency_khz(1);
	401	}
	402
2c8086a5	403	/*
	404	* device registration specific to PXA3xx.
	405	*/
	406
9ba63c4f MR	407	void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
9ba63c4f MR	408	{
14758220	409	pxa_register_device(&pxa3xx_device_i2c_power, info);
9ba63c4f MR	410	}
9ba63c4f MR	411
2c8086a5	412	static struct platform_device *devices[] __initdata = {
94c35a6b	413	&pxa27x_device_udc,
09a5358d	414	&pxa_device_pmu,
2c8086a5	415	&pxa_device_i2s,
f0fba2ad LG	416	&pxa_device_asoc_ssp1,
	417	&pxa_device_asoc_ssp2,
	418	&pxa_device_asoc_ssp3,
	419	&pxa_device_asoc_ssp4,
	420	&pxa_device_asoc_platform,
72493146	421	&sa1100_device_rtc,
2c8086a5	422	&pxa_device_rtc,
d8e0db11	423	&pxa27x_device_ssp1,
	424	&pxa27x_device_ssp2,
	425	&pxa27x_device_ssp3,
	426	&pxa3xx_device_ssp4,
75540c1a	427	&pxa27x_device_pwm0,
75540c1a	428	&pxa27x_device_pwm1,
2c8086a5	429	};
2c8086a5	430
c0165504	431	static struct sys_device pxa3xx_sysdev[] = {
c0165504	432	{
c0165504	433	.cls = &pxa_irq_sysclass,
4be35e23	434	}, {
4be35e23	435	.cls = &pxa3xx_mfp_sysclass,
16dfdbf0	436	}, {
16dfdbf0	437	.cls = &pxa_gpio_sysclass,
aae8224d EM	438	}, {
	439	.cls = &pxa3xx_clock_sysclass,
	440	}
c0165504	441	};
c0165504	442
2c8086a5	443	static int __init pxa3xx_init(void)
2c8086a5	444	{
c0165504	445	int i, ret = 0;
2c8086a5	446
2c8086a5	447	if (cpu_is_pxa3xx()) {
04fef228 EM	448
	449	reset_status = ARSR;
	450
86260f98 DK	451	/*
	452	* clear RDH bit every time after reset
	453	*
	454	* Note: the last 3 bits DxS are write-1-to-clear so carefully
	455	* preserve them here in case they will be referenced later
	456	*/
	457	ASCR &= ~(ASCR_RDH \| ASCR_D1S \| ASCR_D2S \| ASCR_D3S);
	458
0a0300dc	459	clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
2c8086a5	460
fef1f99a	461	if ((ret = pxa_init_dma(IRQ_DMA, 32)))
2c8086a5	462	return ret;
2c8086a5	463
7b5dea12 RK	464	pxa3xx_init_pm();
7b5dea12 RK	465
c0165504	466	for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) {
	467	ret = sysdev_register(&pxa3xx_sysdev[i]);
	468	if (ret)
	469	pr_err("failed to register sysdev[%d]\n", i);
	470	}
	471
	472	ret = platform_add_devices(devices, ARRAY_SIZE(devices));
2c8086a5	473	}
c0165504	474
c0165504	475	return ret;
2c8086a5	476	}
2c8086a5	477
1c104e0e	478	postcore_initcall(pxa3xx_init);