Commit | Line | Data |
---|---|---|
2c8086a5 | 1 | /* |
2 | * linux/arch/arm/mach-pxa/pxa3xx.c | |
3 | * | |
4 | * code specific to pxa3xx aka Monahans | |
5 | * | |
6 | * Copyright (C) 2006 Marvell International Ltd. | |
7 | * | |
e9bba8ee | 8 | * 2007-09-02: eric miao <eric.miao@marvell.com> |
2c8086a5 | 9 | * initial version |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
2c8086a5 | 15 | #include <linux/module.h> |
16 | #include <linux/kernel.h> | |
17 | #include <linux/init.h> | |
b8f649f1 | 18 | #include <linux/gpio-pxa.h> |
2c8086a5 | 19 | #include <linux/pm.h> |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/irq.h> | |
7b5dea12 | 22 | #include <linux/io.h> |
82ce44d1 | 23 | #include <linux/of.h> |
2eaa03b5 | 24 | #include <linux/syscore_ops.h> |
b459396e | 25 | #include <linux/i2c/pxa-i2c.h> |
2c8086a5 | 26 | |
851982c1 | 27 | #include <asm/mach/map.h> |
2c74a0ce | 28 | #include <asm/suspend.h> |
a09e64fb RK |
29 | #include <mach/hardware.h> |
30 | #include <mach/pxa3xx-regs.h> | |
afd2fc02 | 31 | #include <mach/reset.h> |
293b2da1 | 32 | #include <linux/platform_data/usb-ohci-pxa27x.h> |
a09e64fb RK |
33 | #include <mach/pm.h> |
34 | #include <mach/dma.h> | |
ad68bb9f | 35 | #include <mach/smemc.h> |
4e611091 | 36 | #include <mach/irqs.h> |
2c8086a5 | 37 | |
38 | #include "generic.h" | |
39 | #include "devices.h" | |
2c8086a5 | 40 | |
bf293aec MR |
41 | #define PECR_IE(n) ((1 << ((n) * 2)) << 28) |
42 | #define PECR_IS(n) ((1 << ((n) * 2)) << 29) | |
43 | ||
089d0362 | 44 | extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int)); |
7b5dea12 | 45 | #ifdef CONFIG_PM |
7b5dea12 RK |
46 | |
47 | #define ISRAM_START 0x5c000000 | |
48 | #define ISRAM_SIZE SZ_256K | |
49 | ||
50 | static void __iomem *sram; | |
51 | static unsigned long wakeup_src; | |
52 | ||
7b5dea12 RK |
53 | /* |
54 | * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic | |
55 | * memory controller has to be reinitialised, so we place some code | |
56 | * in the SRAM to perform this function. | |
57 | * | |
58 | * We disable FIQs across the standby - otherwise, we might receive a | |
59 | * FIQ while the SDRAM is unavailable. | |
60 | */ | |
61 | static void pxa3xx_cpu_standby(unsigned int pwrmode) | |
62 | { | |
63 | extern const char pm_enter_standby_start[], pm_enter_standby_end[]; | |
64 | void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); | |
65 | ||
66 | memcpy_toio(sram + 0x8000, pm_enter_standby_start, | |
67 | pm_enter_standby_end - pm_enter_standby_start); | |
68 | ||
69 | AD2D0SR = ~0; | |
70 | AD2D1SR = ~0; | |
71 | AD2D0ER = wakeup_src; | |
72 | AD2D1ER = 0; | |
73 | ASCR = ASCR; | |
74 | ARSR = ARSR; | |
75 | ||
76 | local_fiq_disable(); | |
77 | fn(pwrmode); | |
78 | local_fiq_enable(); | |
79 | ||
80 | AD2D0ER = 0; | |
81 | AD2D1ER = 0; | |
7b5dea12 RK |
82 | } |
83 | ||
c4d1fb62 | 84 | /* |
85 | * NOTE: currently, the OBM (OEM Boot Module) binary comes along with | |
86 | * PXA3xx development kits assumes that the resuming process continues | |
87 | * with the address stored within the first 4 bytes of SDRAM. The PSPR | |
88 | * register is used privately by BootROM and OBM, and _must_ be set to | |
89 | * 0x5c014000 for the moment. | |
90 | */ | |
91 | static void pxa3xx_cpu_pm_suspend(void) | |
92 | { | |
93 | volatile unsigned long *p = (volatile void *)0xc0000000; | |
94 | unsigned long saved_data = *p; | |
a9503d21 RK |
95 | #ifndef CONFIG_IWMMXT |
96 | u64 acc0; | |
c4d1fb62 | 97 | |
a9503d21 RK |
98 | asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0)); |
99 | #endif | |
100 | ||
29cb3cd2 | 101 | extern int pxa3xx_finish_suspend(unsigned long); |
c4d1fb62 | 102 | |
103 | /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ | |
104 | CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); | |
105 | CKENB |= 1 << (CKEN_HSIO2 & 0x1f); | |
106 | ||
107 | /* clear and setup wakeup source */ | |
108 | AD3SR = ~0; | |
109 | AD3ER = wakeup_src; | |
110 | ASCR = ASCR; | |
111 | ARSR = ARSR; | |
112 | ||
113 | PCFR |= (1u << 13); /* L1_DIS */ | |
114 | PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */ | |
115 | ||
116 | PSPR = 0x5c014000; | |
117 | ||
118 | /* overwrite with the resume address */ | |
4f5ad99b | 119 | *p = virt_to_phys(cpu_resume); |
c4d1fb62 | 120 | |
2c74a0ce | 121 | cpu_suspend(0, pxa3xx_finish_suspend); |
c4d1fb62 | 122 | |
123 | *p = saved_data; | |
124 | ||
125 | AD3ER = 0; | |
a9503d21 RK |
126 | |
127 | #ifndef CONFIG_IWMMXT | |
128 | asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0)); | |
129 | #endif | |
c4d1fb62 | 130 | } |
131 | ||
7b5dea12 RK |
132 | static void pxa3xx_cpu_pm_enter(suspend_state_t state) |
133 | { | |
134 | /* | |
135 | * Don't sleep if no wakeup sources are defined | |
136 | */ | |
b86a5da8 MB |
137 | if (wakeup_src == 0) { |
138 | printk(KERN_ERR "Not suspending: no wakeup sources\n"); | |
7b5dea12 | 139 | return; |
b86a5da8 | 140 | } |
7b5dea12 RK |
141 | |
142 | switch (state) { | |
143 | case PM_SUSPEND_STANDBY: | |
144 | pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2); | |
145 | break; | |
146 | ||
147 | case PM_SUSPEND_MEM: | |
c4d1fb62 | 148 | pxa3xx_cpu_pm_suspend(); |
7b5dea12 RK |
149 | break; |
150 | } | |
151 | } | |
152 | ||
153 | static int pxa3xx_cpu_pm_valid(suspend_state_t state) | |
154 | { | |
155 | return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; | |
156 | } | |
157 | ||
158 | static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { | |
7b5dea12 RK |
159 | .valid = pxa3xx_cpu_pm_valid, |
160 | .enter = pxa3xx_cpu_pm_enter, | |
2c8086a5 | 161 | }; |
162 | ||
7b5dea12 RK |
163 | static void __init pxa3xx_init_pm(void) |
164 | { | |
165 | sram = ioremap(ISRAM_START, ISRAM_SIZE); | |
166 | if (!sram) { | |
167 | printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n"); | |
168 | return; | |
169 | } | |
170 | ||
171 | /* | |
172 | * Since we copy wakeup code into the SRAM, we need to ensure | |
173 | * that it is preserved over the low power modes. Note: bit 8 | |
174 | * is undocumented in the developer manual, but must be set. | |
175 | */ | |
176 | AD1R |= ADXR_L2 | ADXR_R0; | |
177 | AD2R |= ADXR_L2 | ADXR_R0; | |
178 | AD3R |= ADXR_L2 | ADXR_R0; | |
179 | ||
180 | /* | |
181 | * Clear the resume enable registers. | |
182 | */ | |
183 | AD1D0ER = 0; | |
184 | AD2D0ER = 0; | |
185 | AD2D1ER = 0; | |
186 | AD3ER = 0; | |
187 | ||
188 | pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; | |
189 | } | |
190 | ||
a3f4c927 | 191 | static int pxa3xx_set_wake(struct irq_data *d, unsigned int on) |
7b5dea12 RK |
192 | { |
193 | unsigned long flags, mask = 0; | |
194 | ||
a3f4c927 | 195 | switch (d->irq) { |
7b5dea12 RK |
196 | case IRQ_SSP3: |
197 | mask = ADXER_MFP_WSSP3; | |
198 | break; | |
199 | case IRQ_MSL: | |
200 | mask = ADXER_WMSL0; | |
201 | break; | |
202 | case IRQ_USBH2: | |
203 | case IRQ_USBH1: | |
204 | mask = ADXER_WUSBH; | |
205 | break; | |
206 | case IRQ_KEYPAD: | |
207 | mask = ADXER_WKP; | |
208 | break; | |
209 | case IRQ_AC97: | |
210 | mask = ADXER_MFP_WAC97; | |
211 | break; | |
212 | case IRQ_USIM: | |
213 | mask = ADXER_WUSIM0; | |
214 | break; | |
215 | case IRQ_SSP2: | |
216 | mask = ADXER_MFP_WSSP2; | |
217 | break; | |
218 | case IRQ_I2C: | |
219 | mask = ADXER_MFP_WI2C; | |
220 | break; | |
221 | case IRQ_STUART: | |
222 | mask = ADXER_MFP_WUART3; | |
223 | break; | |
224 | case IRQ_BTUART: | |
225 | mask = ADXER_MFP_WUART2; | |
226 | break; | |
227 | case IRQ_FFUART: | |
228 | mask = ADXER_MFP_WUART1; | |
229 | break; | |
230 | case IRQ_MMC: | |
231 | mask = ADXER_MFP_WMMC1; | |
232 | break; | |
233 | case IRQ_SSP: | |
234 | mask = ADXER_MFP_WSSP1; | |
235 | break; | |
236 | case IRQ_RTCAlrm: | |
237 | mask = ADXER_WRTC; | |
238 | break; | |
239 | case IRQ_SSP4: | |
240 | mask = ADXER_MFP_WSSP4; | |
241 | break; | |
242 | case IRQ_TSI: | |
243 | mask = ADXER_WTSI; | |
244 | break; | |
245 | case IRQ_USIM2: | |
246 | mask = ADXER_WUSIM1; | |
247 | break; | |
248 | case IRQ_MMC2: | |
249 | mask = ADXER_MFP_WMMC2; | |
250 | break; | |
251 | case IRQ_NAND: | |
252 | mask = ADXER_MFP_WFLASH; | |
253 | break; | |
254 | case IRQ_USB2: | |
255 | mask = ADXER_WUSB2; | |
256 | break; | |
257 | case IRQ_WAKEUP0: | |
258 | mask = ADXER_WEXTWAKE0; | |
259 | break; | |
260 | case IRQ_WAKEUP1: | |
261 | mask = ADXER_WEXTWAKE1; | |
262 | break; | |
263 | case IRQ_MMC3: | |
264 | mask = ADXER_MFP_GEN12; | |
265 | break; | |
e1217707 MB |
266 | default: |
267 | return -EINVAL; | |
7b5dea12 RK |
268 | } |
269 | ||
270 | local_irq_save(flags); | |
271 | if (on) | |
272 | wakeup_src |= mask; | |
273 | else | |
274 | wakeup_src &= ~mask; | |
275 | local_irq_restore(flags); | |
276 | ||
277 | return 0; | |
278 | } | |
7b5dea12 RK |
279 | #else |
280 | static inline void pxa3xx_init_pm(void) {} | |
b9e25ace | 281 | #define pxa3xx_set_wake NULL |
7b5dea12 RK |
282 | #endif |
283 | ||
a3f4c927 | 284 | static void pxa_ack_ext_wakeup(struct irq_data *d) |
bf293aec | 285 | { |
a3f4c927 | 286 | PECR |= PECR_IS(d->irq - IRQ_WAKEUP0); |
bf293aec MR |
287 | } |
288 | ||
a3f4c927 | 289 | static void pxa_mask_ext_wakeup(struct irq_data *d) |
bf293aec | 290 | { |
5d284e35 | 291 | pxa_mask_irq(d); |
a3f4c927 | 292 | PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0); |
bf293aec MR |
293 | } |
294 | ||
a3f4c927 | 295 | static void pxa_unmask_ext_wakeup(struct irq_data *d) |
bf293aec | 296 | { |
5d284e35 | 297 | pxa_unmask_irq(d); |
a3f4c927 | 298 | PECR |= PECR_IE(d->irq - IRQ_WAKEUP0); |
bf293aec MR |
299 | } |
300 | ||
a3f4c927 | 301 | static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type) |
12882096 IG |
302 | { |
303 | if (flow_type & IRQ_TYPE_EDGE_RISING) | |
a3f4c927 | 304 | PWER |= 1 << (d->irq - IRQ_WAKEUP0); |
12882096 IG |
305 | |
306 | if (flow_type & IRQ_TYPE_EDGE_FALLING) | |
a3f4c927 | 307 | PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2); |
12882096 IG |
308 | |
309 | return 0; | |
310 | } | |
311 | ||
bf293aec MR |
312 | static struct irq_chip pxa_ext_wakeup_chip = { |
313 | .name = "WAKEUP", | |
a3f4c927 LB |
314 | .irq_ack = pxa_ack_ext_wakeup, |
315 | .irq_mask = pxa_mask_ext_wakeup, | |
316 | .irq_unmask = pxa_unmask_ext_wakeup, | |
317 | .irq_set_type = pxa_set_ext_wakeup_type, | |
bf293aec MR |
318 | }; |
319 | ||
157d2644 HZ |
320 | static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *, |
321 | unsigned int)) | |
bf293aec MR |
322 | { |
323 | int irq; | |
324 | ||
325 | for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { | |
f38c02f3 TG |
326 | irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip, |
327 | handle_edge_irq); | |
bf293aec MR |
328 | set_irq_flags(irq, IRQF_VALID); |
329 | } | |
330 | ||
a3f4c927 | 331 | pxa_ext_wakeup_chip.irq_set_wake = fn; |
bf293aec MR |
332 | } |
333 | ||
089d0362 | 334 | static void __init __pxa3xx_init_irq(void) |
2c8086a5 | 335 | { |
336 | /* enable CP6 access */ | |
337 | u32 value; | |
338 | __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); | |
339 | value |= (1 << 6); | |
340 | __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); | |
341 | ||
bf293aec | 342 | pxa_init_ext_wakeup_irq(pxa3xx_set_wake); |
2c8086a5 | 343 | } |
344 | ||
089d0362 DM |
345 | void __init pxa3xx_init_irq(void) |
346 | { | |
347 | __pxa3xx_init_irq(); | |
348 | pxa_init_irq(56, pxa3xx_set_wake); | |
349 | } | |
350 | ||
e6c509c8 | 351 | #ifdef CONFIG_OF |
089d0362 DM |
352 | void __init pxa3xx_dt_init_irq(void) |
353 | { | |
354 | __pxa3xx_init_irq(); | |
355 | pxa_dt_irq_init(pxa3xx_set_wake); | |
356 | } | |
e6c509c8 | 357 | #endif /* CONFIG_OF */ |
089d0362 | 358 | |
851982c1 MV |
359 | static struct map_desc pxa3xx_io_desc[] __initdata = { |
360 | { /* Mem Ctl */ | |
97b09da4 | 361 | .virtual = (unsigned long)SMEMC_VIRT, |
ad68bb9f | 362 | .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE), |
0e32986c | 363 | .length = SMEMC_SIZE, |
851982c1 MV |
364 | .type = MT_DEVICE |
365 | } | |
366 | }; | |
367 | ||
368 | void __init pxa3xx_map_io(void) | |
369 | { | |
370 | pxa_map_io(); | |
371 | iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc)); | |
372 | pxa3xx_get_clk_frequency_khz(1); | |
373 | } | |
374 | ||
2c8086a5 | 375 | /* |
376 | * device registration specific to PXA3xx. | |
377 | */ | |
378 | ||
9ba63c4f MR |
379 | void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) |
380 | { | |
14758220 | 381 | pxa_register_device(&pxa3xx_device_i2c_power, info); |
9ba63c4f MR |
382 | } |
383 | ||
b8f649f1 HZ |
384 | static struct pxa_gpio_platform_data pxa3xx_gpio_pdata = { |
385 | .irq_base = PXA_GPIO_TO_IRQ(0), | |
386 | }; | |
387 | ||
2c8086a5 | 388 | static struct platform_device *devices[] __initdata = { |
94c35a6b | 389 | &pxa27x_device_udc, |
09a5358d | 390 | &pxa_device_pmu, |
2c8086a5 | 391 | &pxa_device_i2s, |
f0fba2ad LG |
392 | &pxa_device_asoc_ssp1, |
393 | &pxa_device_asoc_ssp2, | |
394 | &pxa_device_asoc_ssp3, | |
395 | &pxa_device_asoc_ssp4, | |
396 | &pxa_device_asoc_platform, | |
72493146 | 397 | &sa1100_device_rtc, |
2c8086a5 | 398 | &pxa_device_rtc, |
0da0e227 DM |
399 | &pxa3xx_device_ssp1, |
400 | &pxa3xx_device_ssp2, | |
401 | &pxa3xx_device_ssp3, | |
d8e0db11 | 402 | &pxa3xx_device_ssp4, |
75540c1a | 403 | &pxa27x_device_pwm0, |
404 | &pxa27x_device_pwm1, | |
2c8086a5 | 405 | }; |
406 | ||
407 | static int __init pxa3xx_init(void) | |
408 | { | |
2eaa03b5 | 409 | int ret = 0; |
2c8086a5 | 410 | |
411 | if (cpu_is_pxa3xx()) { | |
04fef228 EM |
412 | |
413 | reset_status = ARSR; | |
414 | ||
86260f98 DK |
415 | /* |
416 | * clear RDH bit every time after reset | |
417 | * | |
418 | * Note: the last 3 bits DxS are write-1-to-clear so carefully | |
419 | * preserve them here in case they will be referenced later | |
420 | */ | |
421 | ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); | |
422 | ||
fef1f99a | 423 | if ((ret = pxa_init_dma(IRQ_DMA, 32))) |
2c8086a5 | 424 | return ret; |
425 | ||
7b5dea12 RK |
426 | pxa3xx_init_pm(); |
427 | ||
2eaa03b5 RW |
428 | register_syscore_ops(&pxa_irq_syscore_ops); |
429 | register_syscore_ops(&pxa3xx_mfp_syscore_ops); | |
c0165504 | 430 | |
2cab0292 HZ |
431 | if (of_have_populated_dt()) |
432 | return 0; | |
433 | ||
434 | ret = platform_add_devices(devices, ARRAY_SIZE(devices)); | |
435 | if (ret) | |
436 | return ret; | |
b8f649f1 HZ |
437 | if (cpu_is_pxa300() || cpu_is_pxa310() || cpu_is_pxa320()) { |
438 | platform_device_add_data(&pxa3xx_device_gpio, | |
439 | &pxa3xx_gpio_pdata, | |
440 | sizeof(pxa3xx_gpio_pdata)); | |
2cab0292 | 441 | ret = platform_device_register(&pxa3xx_device_gpio); |
b8f649f1 | 442 | } |
2c8086a5 | 443 | } |
c0165504 | 444 | |
445 | return ret; | |
2c8086a5 | 446 | } |
447 | ||
1c104e0e | 448 | postcore_initcall(pxa3xx_init); |