[deliverable/linux.git] / arch / arm / mach-pxa / pxa3xx.c

/*
 * linux/arch/arm/mach-pxa/pxa3xx.c
 *
 * code specific to pxa3xx aka Monahans
 *
 * Copyright (C) 2006 Marvell International Ltd.
 *
 * 2007-09-02: eric miao <eric.miao@marvell.com>
 *             initial version
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/gpio-pxa.h>
#include <linux/pm.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/syscore_ops.h>
#include <linux/i2c/pxa-i2c.h>

#include <asm/mach/map.h>
#include <asm/suspend.h>
#include <mach/hardware.h>
#include <mach/pxa3xx-regs.h>
#include <mach/reset.h>
#include <linux/platform_data/usb-ohci-pxa27x.h>
#include <mach/pm.h>
#include <mach/dma.h>
#include <mach/smemc.h>
#include <mach/irqs.h>

#include "generic.h"
#include "devices.h"
#include "clock.h"

#define PECR_IE(n)	((1 << ((n) * 2)) << 28)
#define PECR_IS(n)	((1 << ((n) * 2)) << 29)

extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int));

static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_gpio, GPIO, 13000000, 0);

static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops);
static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70);

static struct clk_lookup pxa3xx_clkregs[] = {
	INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
	/* Power I2C clock is always on */
	INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
	INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
	INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
	INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
	INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
	INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
	INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
	INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa3xx-ssp.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa3xx-ssp.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa3xx-ssp.2", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa3xx-ssp.3", NULL),
	INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
	INIT_CLKREG(&clk_pxa3xx_gpio, "pxa3xx-gpio", NULL),
	INIT_CLKREG(&clk_pxa3xx_gpio, "pxa93x-gpio", NULL),
	INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
};

#ifdef CONFIG_PM

#define ISRAM_START	0x5c000000
#define ISRAM_SIZE	SZ_256K

static void __iomem *sram;
static unsigned long wakeup_src;

/*
 * Enter a standby mode (S0D1C2 or S0D2C2).  Upon wakeup, the dynamic
 * memory controller has to be reinitialised, so we place some code
 * in the SRAM to perform this function.
 *
 * We disable FIQs across the standby - otherwise, we might receive a
 * FIQ while the SDRAM is unavailable.
 */
static void pxa3xx_cpu_standby(unsigned int pwrmode)
{
	extern const char pm_enter_standby_start[], pm_enter_standby_end[];
	void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);

	memcpy_toio(sram + 0x8000, pm_enter_standby_start,
		    pm_enter_standby_end - pm_enter_standby_start);

	AD2D0SR = ~0;
	AD2D1SR = ~0;
	AD2D0ER = wakeup_src;
	AD2D1ER = 0;
	ASCR = ASCR;
	ARSR = ARSR;

	local_fiq_disable();
	fn(pwrmode);
	local_fiq_enable();

	AD2D0ER = 0;
	AD2D1ER = 0;
}

/*
 * NOTE:  currently, the OBM (OEM Boot Module) binary comes along with
 * PXA3xx development kits assumes that the resuming process continues
 * with the address stored within the first 4 bytes of SDRAM. The PSPR
 * register is used privately by BootROM and OBM, and _must_ be set to
 * 0x5c014000 for the moment.
 */
static void pxa3xx_cpu_pm_suspend(void)
{
	volatile unsigned long *p = (volatile void *)0xc0000000;
	unsigned long saved_data = *p;
#ifndef CONFIG_IWMMXT
	u64 acc0;

	asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0));
#endif

	extern int pxa3xx_finish_suspend(unsigned long);

	/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
	CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
	CKENB |= 1 << (CKEN_HSIO2 & 0x1f);

	/* clear and setup wakeup source */
	AD3SR = ~0;
	AD3ER = wakeup_src;
	ASCR = ASCR;
	ARSR = ARSR;

	PCFR |= (1u << 13);			/* L1_DIS */
	PCFR &= ~((1u << 12) | (1u << 1));	/* L0_EN | SL_ROD */

	PSPR = 0x5c014000;

	/* overwrite with the resume address */
	*p = virt_to_phys(cpu_resume);

	cpu_suspend(0, pxa3xx_finish_suspend);

	*p = saved_data;

	AD3ER = 0;

#ifndef CONFIG_IWMMXT
	asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0));
#endif
}

static void pxa3xx_cpu_pm_enter(suspend_state_t state)
{
	/*
	 * Don't sleep if no wakeup sources are defined
	 */
	if (wakeup_src == 0) {
		printk(KERN_ERR "Not suspending: no wakeup sources\n");
		return;
	}

	switch (state) {
	case PM_SUSPEND_STANDBY:
		pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
		break;

	case PM_SUSPEND_MEM:
		pxa3xx_cpu_pm_suspend();
		break;
	}
}

static int pxa3xx_cpu_pm_valid(suspend_state_t state)
{
	return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
}

static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
	.valid		= pxa3xx_cpu_pm_valid,
	.enter		= pxa3xx_cpu_pm_enter,
};

static void __init pxa3xx_init_pm(void)
{
	sram = ioremap(ISRAM_START, ISRAM_SIZE);
	if (!sram) {
		printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
		return;
	}

	/*
	 * Since we copy wakeup code into the SRAM, we need to ensure
	 * that it is preserved over the low power modes.  Note: bit 8
	 * is undocumented in the developer manual, but must be set.
	 */
	AD1R |= ADXR_L2 | ADXR_R0;
	AD2R |= ADXR_L2 | ADXR_R0;
	AD3R |= ADXR_L2 | ADXR_R0;

	/*
	 * Clear the resume enable registers.
	 */
	AD1D0ER = 0;
	AD2D0ER = 0;
	AD2D1ER = 0;
	AD3ER = 0;

	pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
}

static int pxa3xx_set_wake(struct irq_data *d, unsigned int on)
{
	unsigned long flags, mask = 0;

	switch (d->irq) {
	case IRQ_SSP3:
		mask = ADXER_MFP_WSSP3;
		break;
	case IRQ_MSL:
		mask = ADXER_WMSL0;
		break;
	case IRQ_USBH2:
	case IRQ_USBH1:
		mask = ADXER_WUSBH;
		break;
	case IRQ_KEYPAD:
		mask = ADXER_WKP;
		break;
	case IRQ_AC97:
		mask = ADXER_MFP_WAC97;
		break;
	case IRQ_USIM:
		mask = ADXER_WUSIM0;
		break;
	case IRQ_SSP2:
		mask = ADXER_MFP_WSSP2;
		break;
	case IRQ_I2C:
		mask = ADXER_MFP_WI2C;
		break;
	case IRQ_STUART:
		mask = ADXER_MFP_WUART3;
		break;
	case IRQ_BTUART:
		mask = ADXER_MFP_WUART2;
		break;
	case IRQ_FFUART:
		mask = ADXER_MFP_WUART1;
		break;
	case IRQ_MMC:
		mask = ADXER_MFP_WMMC1;
		break;
	case IRQ_SSP:
		mask = ADXER_MFP_WSSP1;
		break;
	case IRQ_RTCAlrm:
		mask = ADXER_WRTC;
		break;
	case IRQ_SSP4:
		mask = ADXER_MFP_WSSP4;
		break;
	case IRQ_TSI:
		mask = ADXER_WTSI;
		break;
	case IRQ_USIM2:
		mask = ADXER_WUSIM1;
		break;
	case IRQ_MMC2:
		mask = ADXER_MFP_WMMC2;
		break;
	case IRQ_NAND:
		mask = ADXER_MFP_WFLASH;
		break;
	case IRQ_USB2:
		mask = ADXER_WUSB2;
		break;
	case IRQ_WAKEUP0:
		mask = ADXER_WEXTWAKE0;
		break;
	case IRQ_WAKEUP1:
		mask = ADXER_WEXTWAKE1;
		break;
	case IRQ_MMC3:
		mask = ADXER_MFP_GEN12;
		break;
	default:
		return -EINVAL;
	}

	local_irq_save(flags);
	if (on)
		wakeup_src |= mask;
	else
		wakeup_src &= ~mask;
	local_irq_restore(flags);

	return 0;
}
#else
static inline void pxa3xx_init_pm(void) {}
#define pxa3xx_set_wake	NULL
#endif

static void pxa_ack_ext_wakeup(struct irq_data *d)
{
	PECR |= PECR_IS(d->irq - IRQ_WAKEUP0);
}

static void pxa_mask_ext_wakeup(struct irq_data *d)
{
	pxa_mask_irq(d);
	PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0);
}

static void pxa_unmask_ext_wakeup(struct irq_data *d)
{
	pxa_unmask_irq(d);
	PECR |= PECR_IE(d->irq - IRQ_WAKEUP0);
}

static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type)
{
	if (flow_type & IRQ_TYPE_EDGE_RISING)
		PWER |= 1 << (d->irq - IRQ_WAKEUP0);

	if (flow_type & IRQ_TYPE_EDGE_FALLING)
		PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2);

	return 0;
}

static struct irq_chip pxa_ext_wakeup_chip = {
	.name		= "WAKEUP",
	.irq_ack	= pxa_ack_ext_wakeup,
	.irq_mask	= pxa_mask_ext_wakeup,
	.irq_unmask	= pxa_unmask_ext_wakeup,
	.irq_set_type	= pxa_set_ext_wakeup_type,
};

static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *,
					   unsigned int))
{
	int irq;

	for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
		irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip,
					 handle_edge_irq);
		set_irq_flags(irq, IRQF_VALID);
	}

	pxa_ext_wakeup_chip.irq_set_wake = fn;
}

static void __init __pxa3xx_init_irq(void)
{
	/* enable CP6 access */
	u32 value;
	__asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
	value |= (1 << 6);
	__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));

	pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
}

void __init pxa3xx_init_irq(void)
{
	__pxa3xx_init_irq();
	pxa_init_irq(56, pxa3xx_set_wake);
}

#ifdef CONFIG_OF
void __init pxa3xx_dt_init_irq(void)
{
	__pxa3xx_init_irq();
	pxa_dt_irq_init(pxa3xx_set_wake);
}
#endif	/* CONFIG_OF */

static struct map_desc pxa3xx_io_desc[] __initdata = {
	{	/* Mem Ctl */
		.virtual	= (unsigned long)SMEMC_VIRT,
		.pfn		= __phys_to_pfn(PXA3XX_SMEMC_BASE),
		.length		= SMEMC_SIZE,
		.type		= MT_DEVICE
	}
};

void __init pxa3xx_map_io(void)
{
	pxa_map_io();
	iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
	pxa3xx_get_clk_frequency_khz(1);
}

/*
 * device registration specific to PXA3xx.
 */

void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
{
	pxa_register_device(&pxa3xx_device_i2c_power, info);
}

static struct pxa_gpio_platform_data pxa3xx_gpio_pdata = {
	.irq_base	= PXA_GPIO_TO_IRQ(0),
};

static struct platform_device *devices[] __initdata = {
	&pxa27x_device_udc,
	&pxa_device_pmu,
	&pxa_device_i2s,
	&pxa_device_asoc_ssp1,
	&pxa_device_asoc_ssp2,
	&pxa_device_asoc_ssp3,
	&pxa_device_asoc_ssp4,
	&pxa_device_asoc_platform,
	&sa1100_device_rtc,
	&pxa_device_rtc,
	&pxa3xx_device_ssp1,
	&pxa3xx_device_ssp2,
	&pxa3xx_device_ssp3,
	&pxa3xx_device_ssp4,
	&pxa27x_device_pwm0,
	&pxa27x_device_pwm1,
};

static int __init pxa3xx_init(void)
{
	int ret = 0;

	if (cpu_is_pxa3xx()) {

		reset_status = ARSR;

		/*
		 * clear RDH bit every time after reset
		 *
		 * Note: the last 3 bits DxS are write-1-to-clear so carefully
		 * preserve them here in case they will be referenced later
		 */
		ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);

		clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));

		if ((ret = pxa_init_dma(IRQ_DMA, 32)))
			return ret;

		pxa3xx_init_pm();

		register_syscore_ops(&pxa_irq_syscore_ops);
		register_syscore_ops(&pxa3xx_mfp_syscore_ops);
		register_syscore_ops(&pxa3xx_clock_syscore_ops);

		if (of_have_populated_dt())
			return 0;

		ret = platform_add_devices(devices, ARRAY_SIZE(devices));
		if (ret)
			return ret;
		if (cpu_is_pxa300() || cpu_is_pxa310() || cpu_is_pxa320()) {
			platform_device_add_data(&pxa3xx_device_gpio,
						 &pxa3xx_gpio_pdata,
						 sizeof(pxa3xx_gpio_pdata));
			ret = platform_device_register(&pxa3xx_device_gpio);
		}
	}

	return ret;
}

postcore_initcall(pxa3xx_init);
Commit	Line	Data
2c8086a5	1	/*
	2	* linux/arch/arm/mach-pxa/pxa3xx.c
	3	*
	4	* code specific to pxa3xx aka Monahans
	5	*
	6	* Copyright (C) 2006 Marvell International Ltd.
	7	*
e9bba8ee	8	* 2007-09-02: eric miao <eric.miao@marvell.com>
2c8086a5	9	* initial version
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
2c8086a5	15	#include <linux/module.h>
	16	#include <linux/kernel.h>
	17	#include <linux/init.h>
b8f649f1	18	#include <linux/gpio-pxa.h>
2c8086a5	19	#include <linux/pm.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/irq.h>
7b5dea12	22	#include <linux/io.h>
82ce44d1	23	#include <linux/of.h>
2eaa03b5	24	#include <linux/syscore_ops.h>
b459396e	25	#include <linux/i2c/pxa-i2c.h>
2c8086a5	26
851982c1	27	#include <asm/mach/map.h>
2c74a0ce	28	#include <asm/suspend.h>
a09e64fb RK	29	#include <mach/hardware.h>
a09e64fb RK	30	#include <mach/pxa3xx-regs.h>
afd2fc02	31	#include <mach/reset.h>
293b2da1	32	#include <linux/platform_data/usb-ohci-pxa27x.h>
a09e64fb RK	33	#include <mach/pm.h>
a09e64fb RK	34	#include <mach/dma.h>
ad68bb9f	35	#include <mach/smemc.h>
4e611091	36	#include <mach/irqs.h>
2c8086a5	37
	38	#include "generic.h"
	39	#include "devices.h"
	40	#include "clock.h"
	41
bf293aec MR	42	#define PECR_IE(n) ((1 << ((n) * 2)) << 28)
	43	#define PECR_IS(n) ((1 << ((n) * 2)) << 29)
	44
089d0362 DM	45	extern void __init pxa_dt_irq_init(int (fn)(struct irq_data , unsigned int));
089d0362 DM	46
8c3abc7d RK	47	static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
	48	static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
	49	static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
	50	static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
	51	static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
	52	static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
e68750ae	53	static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
8c3abc7d RK	54	static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
	55	static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
	56	static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
	57	static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
	58	static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
	59	static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
	60	static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
	61	static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
	62	static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
389eda15	63	static DEFINE_PXA3_CKEN(pxa3xx_gpio, GPIO, 13000000, 0);
8c3abc7d	64
2e8581e7	65	static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
c085052b	66	static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops);
2e8581e7 EM	67	static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
2e8581e7 EM	68	static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
4029813c	69	static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70);
2e8581e7	70
8c3abc7d RK	71	static struct clk_lookup pxa3xx_clkregs[] = {
	72	INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
	73	/* Power I2C clock is always on */
5c68b099	74	INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
8c3abc7d RK	75	INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
	76	INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
	77	INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
	78	INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
	79	INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
	80	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
	81	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
	82	INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
	83	INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
	84	INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
69f22be7	85	INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
8c3abc7d	86	INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
0da0e227 DM	87	INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa3xx-ssp.0", NULL),
	88	INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa3xx-ssp.1", NULL),
	89	INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa3xx-ssp.2", NULL),
	90	INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa3xx-ssp.3", NULL),
8c3abc7d RK	91	INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
	92	INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
	93	INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
	94	INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
c085052b	95	INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
2cab0292 HZ	96	INIT_CLKREG(&clk_pxa3xx_gpio, "pxa3xx-gpio", NULL),
2cab0292 HZ	97	INIT_CLKREG(&clk_pxa3xx_gpio, "pxa93x-gpio", NULL),
3e12ec77	98	INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
2c8086a5	99	};
2c8086a5	100
7b5dea12	101	#ifdef CONFIG_PM
7b5dea12 RK	102
	103	#define ISRAM_START 0x5c000000
	104	#define ISRAM_SIZE SZ_256K
	105
	106	static void __iomem *sram;
	107	static unsigned long wakeup_src;
	108
7b5dea12 RK	109	/*
	110	* Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
	111	* memory controller has to be reinitialised, so we place some code
	112	* in the SRAM to perform this function.
	113	*
	114	* We disable FIQs across the standby - otherwise, we might receive a
	115	* FIQ while the SDRAM is unavailable.
	116	*/
	117	static void pxa3xx_cpu_standby(unsigned int pwrmode)
	118	{
	119	extern const char pm_enter_standby_start[], pm_enter_standby_end[];
	120	void (fn)(unsigned int) = (void __force )(sram + 0x8000);
	121
	122	memcpy_toio(sram + 0x8000, pm_enter_standby_start,
	123	pm_enter_standby_end - pm_enter_standby_start);
	124
	125	AD2D0SR = ~0;
	126	AD2D1SR = ~0;
	127	AD2D0ER = wakeup_src;
	128	AD2D1ER = 0;
	129	ASCR = ASCR;
	130	ARSR = ARSR;
	131
	132	local_fiq_disable();
	133	fn(pwrmode);
	134	local_fiq_enable();
	135
	136	AD2D0ER = 0;
	137	AD2D1ER = 0;
7b5dea12 RK	138	}
7b5dea12 RK	139
c4d1fb62	140	/*
	141	* NOTE: currently, the OBM (OEM Boot Module) binary comes along with
	142	* PXA3xx development kits assumes that the resuming process continues
	143	* with the address stored within the first 4 bytes of SDRAM. The PSPR
	144	* register is used privately by BootROM and OBM, and _must_ be set to
	145	* 0x5c014000 for the moment.
	146	*/
	147	static void pxa3xx_cpu_pm_suspend(void)
	148	{
	149	volatile unsigned long p = (volatile void )0xc0000000;
	150	unsigned long saved_data = *p;
a9503d21 RK	151	#ifndef CONFIG_IWMMXT
a9503d21 RK	152	u64 acc0;
c4d1fb62	153
a9503d21 RK	154	asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0));
	155	#endif
	156
29cb3cd2	157	extern int pxa3xx_finish_suspend(unsigned long);
c4d1fb62	158
	159	/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
	160	CKENA \|= (1 << CKEN_BOOT) \| (1 << CKEN_TPM);
	161	CKENB \|= 1 << (CKEN_HSIO2 & 0x1f);
	162
	163	/* clear and setup wakeup source */
	164	AD3SR = ~0;
	165	AD3ER = wakeup_src;
	166	ASCR = ASCR;
	167	ARSR = ARSR;
	168
	169	PCFR \|= (1u << 13); /* L1_DIS */
	170	PCFR &= ~((1u << 12) \| (1u << 1)); /* L0_EN \| SL_ROD */
	171
	172	PSPR = 0x5c014000;
	173
	174	/* overwrite with the resume address */
4f5ad99b	175	*p = virt_to_phys(cpu_resume);
c4d1fb62	176
2c74a0ce	177	cpu_suspend(0, pxa3xx_finish_suspend);
c4d1fb62	178
	179	*p = saved_data;
	180
	181	AD3ER = 0;
a9503d21 RK	182
	183	#ifndef CONFIG_IWMMXT
	184	asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0));
	185	#endif
c4d1fb62	186	}
c4d1fb62	187
7b5dea12 RK	188	static void pxa3xx_cpu_pm_enter(suspend_state_t state)
	189	{
	190	/*
	191	* Don't sleep if no wakeup sources are defined
	192	*/
b86a5da8 MB	193	if (wakeup_src == 0) {
b86a5da8 MB	194	printk(KERN_ERR "Not suspending: no wakeup sources\n");
7b5dea12	195	return;
b86a5da8	196	}
7b5dea12 RK	197
	198	switch (state) {
	199	case PM_SUSPEND_STANDBY:
	200	pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
	201	break;
	202
	203	case PM_SUSPEND_MEM:
c4d1fb62	204	pxa3xx_cpu_pm_suspend();
7b5dea12 RK	205	break;
	206	}
	207	}
	208
	209	static int pxa3xx_cpu_pm_valid(suspend_state_t state)
	210	{
	211	return state == PM_SUSPEND_MEM \|\| state == PM_SUSPEND_STANDBY;
	212	}
	213
	214	static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
7b5dea12 RK	215	.valid = pxa3xx_cpu_pm_valid,
7b5dea12 RK	216	.enter = pxa3xx_cpu_pm_enter,
2c8086a5	217	};
2c8086a5	218
7b5dea12 RK	219	static void __init pxa3xx_init_pm(void)
	220	{
	221	sram = ioremap(ISRAM_START, ISRAM_SIZE);
	222	if (!sram) {
	223	printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
	224	return;
	225	}
	226
	227	/*
	228	* Since we copy wakeup code into the SRAM, we need to ensure
	229	* that it is preserved over the low power modes. Note: bit 8
	230	* is undocumented in the developer manual, but must be set.
	231	*/
	232	AD1R \|= ADXR_L2 \| ADXR_R0;
	233	AD2R \|= ADXR_L2 \| ADXR_R0;
	234	AD3R \|= ADXR_L2 \| ADXR_R0;
	235
	236	/*
	237	* Clear the resume enable registers.
	238	*/
	239	AD1D0ER = 0;
	240	AD2D0ER = 0;
	241	AD2D1ER = 0;
	242	AD3ER = 0;
	243
	244	pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
	245	}
	246
a3f4c927	247	static int pxa3xx_set_wake(struct irq_data *d, unsigned int on)
7b5dea12 RK	248	{
	249	unsigned long flags, mask = 0;
	250
a3f4c927	251	switch (d->irq) {
7b5dea12 RK	252	case IRQ_SSP3:
	253	mask = ADXER_MFP_WSSP3;
	254	break;
	255	case IRQ_MSL:
	256	mask = ADXER_WMSL0;
	257	break;
	258	case IRQ_USBH2:
	259	case IRQ_USBH1:
	260	mask = ADXER_WUSBH;
	261	break;
	262	case IRQ_KEYPAD:
	263	mask = ADXER_WKP;
	264	break;
	265	case IRQ_AC97:
	266	mask = ADXER_MFP_WAC97;
	267	break;
	268	case IRQ_USIM:
	269	mask = ADXER_WUSIM0;
	270	break;
	271	case IRQ_SSP2:
	272	mask = ADXER_MFP_WSSP2;
	273	break;
	274	case IRQ_I2C:
	275	mask = ADXER_MFP_WI2C;
	276	break;
	277	case IRQ_STUART:
	278	mask = ADXER_MFP_WUART3;
	279	break;
	280	case IRQ_BTUART:
	281	mask = ADXER_MFP_WUART2;
	282	break;
	283	case IRQ_FFUART:
	284	mask = ADXER_MFP_WUART1;
	285	break;
	286	case IRQ_MMC:
	287	mask = ADXER_MFP_WMMC1;
	288	break;
	289	case IRQ_SSP:
	290	mask = ADXER_MFP_WSSP1;
	291	break;
	292	case IRQ_RTCAlrm:
	293	mask = ADXER_WRTC;
	294	break;
	295	case IRQ_SSP4:
	296	mask = ADXER_MFP_WSSP4;
	297	break;
	298	case IRQ_TSI:
	299	mask = ADXER_WTSI;
	300	break;
	301	case IRQ_USIM2:
	302	mask = ADXER_WUSIM1;
	303	break;
	304	case IRQ_MMC2:
	305	mask = ADXER_MFP_WMMC2;
	306	break;
	307	case IRQ_NAND:
	308	mask = ADXER_MFP_WFLASH;
	309	break;
	310	case IRQ_USB2:
	311	mask = ADXER_WUSB2;
	312	break;
	313	case IRQ_WAKEUP0:
	314	mask = ADXER_WEXTWAKE0;
	315	break;
316	case IRQ_WAKEUP1:
317	mask = ADXER_WEXTWAKE1;
318	break;
319	case IRQ_MMC3:
320	mask = ADXER_MFP_GEN12;
321	break;
e1217707 MB	322	default:
e1217707 MB	323	return -EINVAL;
7b5dea12 RK	324	}
	325
	326	local_irq_save(flags);
	327	if (on)
	328	wakeup_src \|= mask;
	329	else
	330	wakeup_src &= ~mask;
	331	local_irq_restore(flags);
	332
	333	return 0;
	334	}
7b5dea12 RK	335	#else
7b5dea12 RK	336	static inline void pxa3xx_init_pm(void) {}
b9e25ace	337	#define pxa3xx_set_wake NULL
7b5dea12 RK	338	#endif
7b5dea12 RK	339
a3f4c927	340	static void pxa_ack_ext_wakeup(struct irq_data *d)
bf293aec	341	{
a3f4c927	342	PECR \|= PECR_IS(d->irq - IRQ_WAKEUP0);
bf293aec MR	343	}
bf293aec MR	344
a3f4c927	345	static void pxa_mask_ext_wakeup(struct irq_data *d)
bf293aec	346	{
5d284e35	347	pxa_mask_irq(d);
a3f4c927	348	PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0);
bf293aec MR	349	}
bf293aec MR	350
a3f4c927	351	static void pxa_unmask_ext_wakeup(struct irq_data *d)
bf293aec	352	{
5d284e35	353	pxa_unmask_irq(d);
a3f4c927	354	PECR \|= PECR_IE(d->irq - IRQ_WAKEUP0);
bf293aec MR	355	}
bf293aec MR	356
a3f4c927	357	static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type)
12882096 IG	358	{
12882096 IG	359	if (flow_type & IRQ_TYPE_EDGE_RISING)
a3f4c927	360	PWER \|= 1 << (d->irq - IRQ_WAKEUP0);
12882096 IG	361
12882096 IG	362	if (flow_type & IRQ_TYPE_EDGE_FALLING)
a3f4c927	363	PWER \|= 1 << (d->irq - IRQ_WAKEUP0 + 2);
12882096 IG	364
	365	return 0;
	366	}
	367
bf293aec MR	368	static struct irq_chip pxa_ext_wakeup_chip = {
bf293aec MR	369	.name = "WAKEUP",
a3f4c927 LB	370	.irq_ack = pxa_ack_ext_wakeup,
	371	.irq_mask = pxa_mask_ext_wakeup,
	372	.irq_unmask = pxa_unmask_ext_wakeup,
	373	.irq_set_type = pxa_set_ext_wakeup_type,
bf293aec MR	374	};
bf293aec MR	375
157d2644 HZ	376	static void __init pxa_init_ext_wakeup_irq(int (fn)(struct irq_data ,
157d2644 HZ	377	unsigned int))
bf293aec MR	378	{
	379	int irq;
	380
	381	for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
f38c02f3 TG	382	irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip,
f38c02f3 TG	383	handle_edge_irq);
bf293aec MR	384	set_irq_flags(irq, IRQF_VALID);
	385	}
	386
a3f4c927	387	pxa_ext_wakeup_chip.irq_set_wake = fn;
bf293aec MR	388	}
bf293aec MR	389
089d0362	390	static void __init __pxa3xx_init_irq(void)
2c8086a5	391	{
	392	/* enable CP6 access */
	393	u32 value;
	394	__asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
	395	value \|= (1 << 6);
	396	__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
	397
bf293aec	398	pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
2c8086a5	399	}
2c8086a5	400
089d0362 DM	401	void __init pxa3xx_init_irq(void)
	402	{
	403	__pxa3xx_init_irq();
	404	pxa_init_irq(56, pxa3xx_set_wake);
	405	}
	406
e6c509c8	407	#ifdef CONFIG_OF
089d0362 DM	408	void __init pxa3xx_dt_init_irq(void)
	409	{
	410	__pxa3xx_init_irq();
	411	pxa_dt_irq_init(pxa3xx_set_wake);
	412	}
e6c509c8	413	#endif /* CONFIG_OF */
089d0362	414
851982c1 MV	415	static struct map_desc pxa3xx_io_desc[] __initdata = {
851982c1 MV	416	{ /* Mem Ctl */
97b09da4	417	.virtual = (unsigned long)SMEMC_VIRT,
ad68bb9f	418	.pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE),
0e32986c	419	.length = SMEMC_SIZE,
851982c1 MV	420	.type = MT_DEVICE
	421	}
	422	};
	423
	424	void __init pxa3xx_map_io(void)
	425	{
	426	pxa_map_io();
	427	iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
	428	pxa3xx_get_clk_frequency_khz(1);
	429	}
	430
2c8086a5	431	/*
	432	* device registration specific to PXA3xx.
	433	*/
	434
9ba63c4f MR	435	void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
9ba63c4f MR	436	{
14758220	437	pxa_register_device(&pxa3xx_device_i2c_power, info);
9ba63c4f MR	438	}
9ba63c4f MR	439
b8f649f1 HZ	440	static struct pxa_gpio_platform_data pxa3xx_gpio_pdata = {
	441	.irq_base = PXA_GPIO_TO_IRQ(0),
	442	};
	443
2c8086a5	444	static struct platform_device *devices[] __initdata = {
94c35a6b	445	&pxa27x_device_udc,
09a5358d	446	&pxa_device_pmu,
2c8086a5	447	&pxa_device_i2s,
f0fba2ad LG	448	&pxa_device_asoc_ssp1,
	449	&pxa_device_asoc_ssp2,
	450	&pxa_device_asoc_ssp3,
	451	&pxa_device_asoc_ssp4,
	452	&pxa_device_asoc_platform,
72493146	453	&sa1100_device_rtc,
2c8086a5	454	&pxa_device_rtc,
0da0e227 DM	455	&pxa3xx_device_ssp1,
	456	&pxa3xx_device_ssp2,
	457	&pxa3xx_device_ssp3,
d8e0db11	458	&pxa3xx_device_ssp4,
75540c1a	459	&pxa27x_device_pwm0,
75540c1a	460	&pxa27x_device_pwm1,
2c8086a5	461	};
	462
	463	static int __init pxa3xx_init(void)
	464	{
2eaa03b5	465	int ret = 0;
2c8086a5	466
2c8086a5	467	if (cpu_is_pxa3xx()) {
04fef228 EM	468
	469	reset_status = ARSR;
	470
86260f98 DK	471	/*
	472	* clear RDH bit every time after reset
	473	*
	474	* Note: the last 3 bits DxS are write-1-to-clear so carefully
	475	* preserve them here in case they will be referenced later
	476	*/
	477	ASCR &= ~(ASCR_RDH \| ASCR_D1S \| ASCR_D2S \| ASCR_D3S);
	478
0a0300dc	479	clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
2c8086a5	480
fef1f99a	481	if ((ret = pxa_init_dma(IRQ_DMA, 32)))
2c8086a5	482	return ret;
2c8086a5	483
7b5dea12 RK	484	pxa3xx_init_pm();
7b5dea12 RK	485
2eaa03b5 RW	486	register_syscore_ops(&pxa_irq_syscore_ops);
2eaa03b5 RW	487	register_syscore_ops(&pxa3xx_mfp_syscore_ops);
2eaa03b5	488	register_syscore_ops(&pxa3xx_clock_syscore_ops);
c0165504	489
2cab0292 HZ	490	if (of_have_populated_dt())
	491	return 0;
	492
	493	ret = platform_add_devices(devices, ARRAY_SIZE(devices));
	494	if (ret)
	495	return ret;
b8f649f1 HZ	496	if (cpu_is_pxa300() \|\| cpu_is_pxa310() \|\| cpu_is_pxa320()) {
	497	platform_device_add_data(&pxa3xx_device_gpio,
	498	&pxa3xx_gpio_pdata,
	499	sizeof(pxa3xx_gpio_pdata));
2cab0292	500	ret = platform_device_register(&pxa3xx_device_gpio);
b8f649f1	501	}
2c8086a5	502	}
c0165504	503
c0165504	504	return ret;
2c8086a5	505	}
2c8086a5	506
1c104e0e	507	postcore_initcall(pxa3xx_init);