[deliverable/linux.git] / arch / arm / mach-pxa / pxa3xx.c

/*
 * linux/arch/arm/mach-pxa/pxa3xx.c
 *
 * code specific to pxa3xx aka Monahans
 *
 * Copyright (C) 2006 Marvell International Ltd.
 *
 * 2007-09-02: eric miao <eric.miao@marvell.com>
 *             initial version
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pm.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/syscore_ops.h>
#include <linux/i2c/pxa-i2c.h>

#include <asm/mach/map.h>
#include <asm/suspend.h>
#include <mach/hardware.h>
#include <mach/gpio.h>
#include <mach/pxa3xx-regs.h>
#include <mach/reset.h>
#include <mach/ohci.h>
#include <mach/pm.h>
#include <mach/dma.h>
#include <mach/regs-intc.h>
#include <mach/smemc.h>

#include "generic.h"
#include "devices.h"
#include "clock.h"

#define PECR_IE(n)	((1 << ((n) * 2)) << 28)
#define PECR_IS(n)	((1 << ((n) * 2)) << 29)

static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);

static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops);
static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70);

static struct clk_lookup pxa3xx_clkregs[] = {
	INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
	/* Power I2C clock is always on */
	INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
	INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
	INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
	INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
	INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
	INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
	INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
	INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
	INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
};

#ifdef CONFIG_PM

#define ISRAM_START	0x5c000000
#define ISRAM_SIZE	SZ_256K

static void __iomem *sram;
static unsigned long wakeup_src;

/*
 * Enter a standby mode (S0D1C2 or S0D2C2).  Upon wakeup, the dynamic
 * memory controller has to be reinitialised, so we place some code
 * in the SRAM to perform this function.
 *
 * We disable FIQs across the standby - otherwise, we might receive a
 * FIQ while the SDRAM is unavailable.
 */
static void pxa3xx_cpu_standby(unsigned int pwrmode)
{
	extern const char pm_enter_standby_start[], pm_enter_standby_end[];
	void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);

	memcpy_toio(sram + 0x8000, pm_enter_standby_start,
		    pm_enter_standby_end - pm_enter_standby_start);

	AD2D0SR = ~0;
	AD2D1SR = ~0;
	AD2D0ER = wakeup_src;
	AD2D1ER = 0;
	ASCR = ASCR;
	ARSR = ARSR;

	local_fiq_disable();
	fn(pwrmode);
	local_fiq_enable();

	AD2D0ER = 0;
	AD2D1ER = 0;
}

/*
 * NOTE:  currently, the OBM (OEM Boot Module) binary comes along with
 * PXA3xx development kits assumes that the resuming process continues
 * with the address stored within the first 4 bytes of SDRAM. The PSPR
 * register is used privately by BootROM and OBM, and _must_ be set to
 * 0x5c014000 for the moment.
 */
static void pxa3xx_cpu_pm_suspend(void)
{
	volatile unsigned long *p = (volatile void *)0xc0000000;
	unsigned long saved_data = *p;
#ifndef CONFIG_IWMMXT
	u64 acc0;

	asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0));
#endif

	extern void pxa3xx_finish_suspend(unsigned long);

	/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
	CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
	CKENB |= 1 << (CKEN_HSIO2 & 0x1f);

	/* clear and setup wakeup source */
	AD3SR = ~0;
	AD3ER = wakeup_src;
	ASCR = ASCR;
	ARSR = ARSR;

	PCFR |= (1u << 13);			/* L1_DIS */
	PCFR &= ~((1u << 12) | (1u << 1));	/* L0_EN | SL_ROD */

	PSPR = 0x5c014000;

	/* overwrite with the resume address */
	*p = virt_to_phys(cpu_resume);

	cpu_suspend(0, pxa3xx_finish_suspend);

	*p = saved_data;

	AD3ER = 0;

#ifndef CONFIG_IWMMXT
	asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0));
#endif
}

static void pxa3xx_cpu_pm_enter(suspend_state_t state)
{
	/*
	 * Don't sleep if no wakeup sources are defined
	 */
	if (wakeup_src == 0) {
		printk(KERN_ERR "Not suspending: no wakeup sources\n");
		return;
	}

	switch (state) {
	case PM_SUSPEND_STANDBY:
		pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
		break;

	case PM_SUSPEND_MEM:
		pxa3xx_cpu_pm_suspend();
		break;
	}
}

static int pxa3xx_cpu_pm_valid(suspend_state_t state)
{
	return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
}

static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
	.valid		= pxa3xx_cpu_pm_valid,
	.enter		= pxa3xx_cpu_pm_enter,
};

static void __init pxa3xx_init_pm(void)
{
	sram = ioremap(ISRAM_START, ISRAM_SIZE);
	if (!sram) {
		printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
		return;
	}

	/*
	 * Since we copy wakeup code into the SRAM, we need to ensure
	 * that it is preserved over the low power modes.  Note: bit 8
	 * is undocumented in the developer manual, but must be set.
	 */
	AD1R |= ADXR_L2 | ADXR_R0;
	AD2R |= ADXR_L2 | ADXR_R0;
	AD3R |= ADXR_L2 | ADXR_R0;

	/*
	 * Clear the resume enable registers.
	 */
	AD1D0ER = 0;
	AD2D0ER = 0;
	AD2D1ER = 0;
	AD3ER = 0;

	pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
}

static int pxa3xx_set_wake(struct irq_data *d, unsigned int on)
{
	unsigned long flags, mask = 0;

	switch (d->irq) {
	case IRQ_SSP3:
		mask = ADXER_MFP_WSSP3;
		break;
	case IRQ_MSL:
		mask = ADXER_WMSL0;
		break;
	case IRQ_USBH2:
	case IRQ_USBH1:
		mask = ADXER_WUSBH;
		break;
	case IRQ_KEYPAD:
		mask = ADXER_WKP;
		break;
	case IRQ_AC97:
		mask = ADXER_MFP_WAC97;
		break;
	case IRQ_USIM:
		mask = ADXER_WUSIM0;
		break;
	case IRQ_SSP2:
		mask = ADXER_MFP_WSSP2;
		break;
	case IRQ_I2C:
		mask = ADXER_MFP_WI2C;
		break;
	case IRQ_STUART:
		mask = ADXER_MFP_WUART3;
		break;
	case IRQ_BTUART:
		mask = ADXER_MFP_WUART2;
		break;
	case IRQ_FFUART:
		mask = ADXER_MFP_WUART1;
		break;
	case IRQ_MMC:
		mask = ADXER_MFP_WMMC1;
		break;
	case IRQ_SSP:
		mask = ADXER_MFP_WSSP1;
		break;
	case IRQ_RTCAlrm:
		mask = ADXER_WRTC;
		break;
	case IRQ_SSP4:
		mask = ADXER_MFP_WSSP4;
		break;
	case IRQ_TSI:
		mask = ADXER_WTSI;
		break;
	case IRQ_USIM2:
		mask = ADXER_WUSIM1;
		break;
	case IRQ_MMC2:
		mask = ADXER_MFP_WMMC2;
		break;
	case IRQ_NAND:
		mask = ADXER_MFP_WFLASH;
		break;
	case IRQ_USB2:
		mask = ADXER_WUSB2;
		break;
	case IRQ_WAKEUP0:
		mask = ADXER_WEXTWAKE0;
		break;
	case IRQ_WAKEUP1:
		mask = ADXER_WEXTWAKE1;
		break;
	case IRQ_MMC3:
		mask = ADXER_MFP_GEN12;
		break;
	default:
		return -EINVAL;
	}

	local_irq_save(flags);
	if (on)
		wakeup_src |= mask;
	else
		wakeup_src &= ~mask;
	local_irq_restore(flags);

	return 0;
}
#else
static inline void pxa3xx_init_pm(void) {}
#define pxa3xx_set_wake	NULL
#endif

static void pxa_ack_ext_wakeup(struct irq_data *d)
{
	PECR |= PECR_IS(d->irq - IRQ_WAKEUP0);
}

static void pxa_mask_ext_wakeup(struct irq_data *d)
{
	ICMR2 &= ~(1 << ((d->irq - PXA_IRQ(0)) & 0x1f));
	PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0);
}

static void pxa_unmask_ext_wakeup(struct irq_data *d)
{
	ICMR2 |= 1 << ((d->irq - PXA_IRQ(0)) & 0x1f);
	PECR |= PECR_IE(d->irq - IRQ_WAKEUP0);
}

static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type)
{
	if (flow_type & IRQ_TYPE_EDGE_RISING)
		PWER |= 1 << (d->irq - IRQ_WAKEUP0);

	if (flow_type & IRQ_TYPE_EDGE_FALLING)
		PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2);

	return 0;
}

static struct irq_chip pxa_ext_wakeup_chip = {
	.name		= "WAKEUP",
	.irq_ack	= pxa_ack_ext_wakeup,
	.irq_mask	= pxa_mask_ext_wakeup,
	.irq_unmask	= pxa_unmask_ext_wakeup,
	.irq_set_type	= pxa_set_ext_wakeup_type,
};

static void __init pxa_init_ext_wakeup_irq(set_wake_t fn)
{
	int irq;

	for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
		irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip,
					 handle_edge_irq);
		set_irq_flags(irq, IRQF_VALID);
	}

	pxa_ext_wakeup_chip.irq_set_wake = fn;
}

void __init pxa3xx_init_irq(void)
{
	/* enable CP6 access */
	u32 value;
	__asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
	value |= (1 << 6);
	__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));

	pxa_init_irq(56, pxa3xx_set_wake);
	pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
	pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
}

static struct map_desc pxa3xx_io_desc[] __initdata = {
	{	/* Mem Ctl */
		.virtual	= SMEMC_VIRT,
		.pfn		= __phys_to_pfn(PXA3XX_SMEMC_BASE),
		.length		= 0x00200000,
		.type		= MT_DEVICE
	}
};

void __init pxa3xx_map_io(void)
{
	pxa_map_io();
	iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
	pxa3xx_get_clk_frequency_khz(1);
}

/*
 * device registration specific to PXA3xx.
 */

void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
{
	pxa_register_device(&pxa3xx_device_i2c_power, info);
}

static struct platform_device *devices[] __initdata = {
	&pxa27x_device_udc,
	&pxa_device_pmu,
	&pxa_device_i2s,
	&pxa_device_asoc_ssp1,
	&pxa_device_asoc_ssp2,
	&pxa_device_asoc_ssp3,
	&pxa_device_asoc_ssp4,
	&pxa_device_asoc_platform,
	&sa1100_device_rtc,
	&pxa_device_rtc,
	&pxa27x_device_ssp1,
	&pxa27x_device_ssp2,
	&pxa27x_device_ssp3,
	&pxa3xx_device_ssp4,
	&pxa27x_device_pwm0,
	&pxa27x_device_pwm1,
};

static int __init pxa3xx_init(void)
{
	int ret = 0;

	if (cpu_is_pxa3xx()) {

		reset_status = ARSR;

		/*
		 * clear RDH bit every time after reset
		 *
		 * Note: the last 3 bits DxS are write-1-to-clear so carefully
		 * preserve them here in case they will be referenced later
		 */
		ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);

		clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));

		if ((ret = pxa_init_dma(IRQ_DMA, 32)))
			return ret;

		pxa3xx_init_pm();

		register_syscore_ops(&pxa_irq_syscore_ops);
		register_syscore_ops(&pxa3xx_mfp_syscore_ops);
		register_syscore_ops(&pxa_gpio_syscore_ops);
		register_syscore_ops(&pxa3xx_clock_syscore_ops);

		ret = platform_add_devices(devices, ARRAY_SIZE(devices));
	}

	return ret;
}

postcore_initcall(pxa3xx_init);
Commit	Line	Data
2c8086a5	1	/*
	2	* linux/arch/arm/mach-pxa/pxa3xx.c
	3	*
	4	* code specific to pxa3xx aka Monahans
	5	*
	6	* Copyright (C) 2006 Marvell International Ltd.
	7	*
e9bba8ee	8	* 2007-09-02: eric miao <eric.miao@marvell.com>
2c8086a5	9	* initial version
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#include <linux/module.h>
	17	#include <linux/kernel.h>
	18	#include <linux/init.h>
	19	#include <linux/pm.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/irq.h>
7b5dea12	22	#include <linux/io.h>
2eaa03b5	23	#include <linux/syscore_ops.h>
b459396e	24	#include <linux/i2c/pxa-i2c.h>
2c8086a5	25
851982c1	26	#include <asm/mach/map.h>
2c74a0ce	27	#include <asm/suspend.h>
a09e64fb	28	#include <mach/hardware.h>
a58fbcd8	29	#include <mach/gpio.h>
a09e64fb	30	#include <mach/pxa3xx-regs.h>
afd2fc02	31	#include <mach/reset.h>
a09e64fb RK	32	#include <mach/ohci.h>
	33	#include <mach/pm.h>
	34	#include <mach/dma.h>
bf293aec	35	#include <mach/regs-intc.h>
ad68bb9f	36	#include <mach/smemc.h>
2c8086a5	37
	38	#include "generic.h"
	39	#include "devices.h"
	40	#include "clock.h"
	41
bf293aec MR	42	#define PECR_IE(n) ((1 << ((n) * 2)) << 28)
	43	#define PECR_IS(n) ((1 << ((n) * 2)) << 29)
	44
8c3abc7d RK	45	static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
	46	static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
	47	static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
	48	static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
	49	static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
	50	static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
e68750ae	51	static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
8c3abc7d RK	52	static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
	53	static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
	54	static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
	55	static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
	56	static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
	57	static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
	58	static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
	59	static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
	60	static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
	61
2e8581e7	62	static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
c085052b	63	static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops);
2e8581e7 EM	64	static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
2e8581e7 EM	65	static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
4029813c	66	static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70);
2e8581e7	67
8c3abc7d RK	68	static struct clk_lookup pxa3xx_clkregs[] = {
	69	INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
	70	/* Power I2C clock is always on */
5c68b099	71	INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
8c3abc7d RK	72	INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
	73	INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
	74	INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
	75	INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
	76	INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
	77	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
	78	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
	79	INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
	80	INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
	81	INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
69f22be7	82	INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
8c3abc7d RK	83	INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
	84	INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
	85	INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
	86	INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
	87	INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
	88	INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
	89	INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
	90	INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
	91	INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
c085052b	92	INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
2c8086a5	93	};
2c8086a5	94
7b5dea12	95	#ifdef CONFIG_PM
7b5dea12 RK	96
	97	#define ISRAM_START 0x5c000000
	98	#define ISRAM_SIZE SZ_256K
	99
	100	static void __iomem *sram;
	101	static unsigned long wakeup_src;
	102
7b5dea12 RK	103	/*
	104	* Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
	105	* memory controller has to be reinitialised, so we place some code
	106	* in the SRAM to perform this function.
	107	*
	108	* We disable FIQs across the standby - otherwise, we might receive a
	109	* FIQ while the SDRAM is unavailable.
	110	*/
	111	static void pxa3xx_cpu_standby(unsigned int pwrmode)
	112	{
	113	extern const char pm_enter_standby_start[], pm_enter_standby_end[];
	114	void (fn)(unsigned int) = (void __force )(sram + 0x8000);
	115
	116	memcpy_toio(sram + 0x8000, pm_enter_standby_start,
	117	pm_enter_standby_end - pm_enter_standby_start);
	118
	119	AD2D0SR = ~0;
	120	AD2D1SR = ~0;
	121	AD2D0ER = wakeup_src;
	122	AD2D1ER = 0;
	123	ASCR = ASCR;
	124	ARSR = ARSR;
	125
	126	local_fiq_disable();
	127	fn(pwrmode);
	128	local_fiq_enable();
	129
	130	AD2D0ER = 0;
	131	AD2D1ER = 0;
7b5dea12 RK	132	}
7b5dea12 RK	133
c4d1fb62	134	/*
	135	* NOTE: currently, the OBM (OEM Boot Module) binary comes along with
	136	* PXA3xx development kits assumes that the resuming process continues
	137	* with the address stored within the first 4 bytes of SDRAM. The PSPR
	138	* register is used privately by BootROM and OBM, and _must_ be set to
	139	* 0x5c014000 for the moment.
	140	*/
	141	static void pxa3xx_cpu_pm_suspend(void)
	142	{
	143	volatile unsigned long p = (volatile void )0xc0000000;
	144	unsigned long saved_data = *p;
a9503d21 RK	145	#ifndef CONFIG_IWMMXT
a9503d21 RK	146	u64 acc0;
c4d1fb62	147
a9503d21 RK	148	asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0));
	149	#endif
	150
	151	extern void pxa3xx_finish_suspend(unsigned long);
c4d1fb62	152
	153	/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
	154	CKENA \|= (1 << CKEN_BOOT) \| (1 << CKEN_TPM);
	155	CKENB \|= 1 << (CKEN_HSIO2 & 0x1f);
	156
	157	/* clear and setup wakeup source */
	158	AD3SR = ~0;
	159	AD3ER = wakeup_src;
	160	ASCR = ASCR;
	161	ARSR = ARSR;
	162
	163	PCFR \|= (1u << 13); /* L1_DIS */
	164	PCFR &= ~((1u << 12) \| (1u << 1)); /* L0_EN \| SL_ROD */
	165
	166	PSPR = 0x5c014000;
	167
	168	/* overwrite with the resume address */
4f5ad99b	169	*p = virt_to_phys(cpu_resume);
c4d1fb62	170
2c74a0ce	171	cpu_suspend(0, pxa3xx_finish_suspend);
c4d1fb62	172
	173	*p = saved_data;
	174
	175	AD3ER = 0;
a9503d21 RK	176
	177	#ifndef CONFIG_IWMMXT
	178	asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0));
	179	#endif
c4d1fb62	180	}
c4d1fb62	181
7b5dea12 RK	182	static void pxa3xx_cpu_pm_enter(suspend_state_t state)
	183	{
	184	/*
	185	* Don't sleep if no wakeup sources are defined
	186	*/
b86a5da8 MB	187	if (wakeup_src == 0) {
b86a5da8 MB	188	printk(KERN_ERR "Not suspending: no wakeup sources\n");
7b5dea12	189	return;
b86a5da8	190	}
7b5dea12 RK	191
	192	switch (state) {
	193	case PM_SUSPEND_STANDBY:
	194	pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
	195	break;
	196
	197	case PM_SUSPEND_MEM:
c4d1fb62	198	pxa3xx_cpu_pm_suspend();
7b5dea12 RK	199	break;
	200	}
	201	}
	202
	203	static int pxa3xx_cpu_pm_valid(suspend_state_t state)
	204	{
	205	return state == PM_SUSPEND_MEM \|\| state == PM_SUSPEND_STANDBY;
	206	}
	207
	208	static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
7b5dea12 RK	209	.valid = pxa3xx_cpu_pm_valid,
7b5dea12 RK	210	.enter = pxa3xx_cpu_pm_enter,
2c8086a5	211	};
2c8086a5	212
7b5dea12 RK	213	static void __init pxa3xx_init_pm(void)
	214	{
	215	sram = ioremap(ISRAM_START, ISRAM_SIZE);
	216	if (!sram) {
	217	printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
	218	return;
	219	}
	220
	221	/*
	222	* Since we copy wakeup code into the SRAM, we need to ensure
	223	* that it is preserved over the low power modes. Note: bit 8
	224	* is undocumented in the developer manual, but must be set.
	225	*/
	226	AD1R \|= ADXR_L2 \| ADXR_R0;
	227	AD2R \|= ADXR_L2 \| ADXR_R0;
	228	AD3R \|= ADXR_L2 \| ADXR_R0;
	229
	230	/*
	231	* Clear the resume enable registers.
	232	*/
	233	AD1D0ER = 0;
	234	AD2D0ER = 0;
	235	AD2D1ER = 0;
	236	AD3ER = 0;
	237
	238	pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
	239	}
	240
a3f4c927	241	static int pxa3xx_set_wake(struct irq_data *d, unsigned int on)
7b5dea12 RK	242	{
	243	unsigned long flags, mask = 0;
	244
a3f4c927	245	switch (d->irq) {
7b5dea12 RK	246	case IRQ_SSP3:
	247	mask = ADXER_MFP_WSSP3;
	248	break;
	249	case IRQ_MSL:
	250	mask = ADXER_WMSL0;
	251	break;
	252	case IRQ_USBH2:
	253	case IRQ_USBH1:
	254	mask = ADXER_WUSBH;
	255	break;
	256	case IRQ_KEYPAD:
	257	mask = ADXER_WKP;
	258	break;
	259	case IRQ_AC97:
	260	mask = ADXER_MFP_WAC97;
	261	break;
	262	case IRQ_USIM:
	263	mask = ADXER_WUSIM0;
	264	break;
	265	case IRQ_SSP2:
	266	mask = ADXER_MFP_WSSP2;
	267	break;
	268	case IRQ_I2C:
	269	mask = ADXER_MFP_WI2C;
	270	break;
	271	case IRQ_STUART:
	272	mask = ADXER_MFP_WUART3;
	273	break;
	274	case IRQ_BTUART:
	275	mask = ADXER_MFP_WUART2;
	276	break;
	277	case IRQ_FFUART:
	278	mask = ADXER_MFP_WUART1;
	279	break;
	280	case IRQ_MMC:
	281	mask = ADXER_MFP_WMMC1;
	282	break;
	283	case IRQ_SSP:
	284	mask = ADXER_MFP_WSSP1;
	285	break;
	286	case IRQ_RTCAlrm:
	287	mask = ADXER_WRTC;
	288	break;
	289	case IRQ_SSP4:
	290	mask = ADXER_MFP_WSSP4;
	291	break;
	292	case IRQ_TSI:
	293	mask = ADXER_WTSI;
	294	break;
	295	case IRQ_USIM2:
	296	mask = ADXER_WUSIM1;
	297	break;
	298	case IRQ_MMC2:
	299	mask = ADXER_MFP_WMMC2;
	300	break;
	301	case IRQ_NAND:
	302	mask = ADXER_MFP_WFLASH;
	303	break;
	304	case IRQ_USB2:
	305	mask = ADXER_WUSB2;
	306	break;
	307	case IRQ_WAKEUP0:
	308	mask = ADXER_WEXTWAKE0;
	309	break;
310	case IRQ_WAKEUP1:
311	mask = ADXER_WEXTWAKE1;
312	break;
313	case IRQ_MMC3:
314	mask = ADXER_MFP_GEN12;
315	break;
e1217707 MB	316	default:
e1217707 MB	317	return -EINVAL;
7b5dea12 RK	318	}
	319
	320	local_irq_save(flags);
	321	if (on)
	322	wakeup_src \|= mask;
	323	else
	324	wakeup_src &= ~mask;
	325	local_irq_restore(flags);
	326
	327	return 0;
	328	}
7b5dea12 RK	329	#else
7b5dea12 RK	330	static inline void pxa3xx_init_pm(void) {}
b9e25ace	331	#define pxa3xx_set_wake NULL
7b5dea12 RK	332	#endif
7b5dea12 RK	333
a3f4c927	334	static void pxa_ack_ext_wakeup(struct irq_data *d)
bf293aec	335	{
a3f4c927	336	PECR \|= PECR_IS(d->irq - IRQ_WAKEUP0);
bf293aec MR	337	}
bf293aec MR	338
a3f4c927	339	static void pxa_mask_ext_wakeup(struct irq_data *d)
bf293aec	340	{
a3f4c927 LB	341	ICMR2 &= ~(1 << ((d->irq - PXA_IRQ(0)) & 0x1f));
a3f4c927 LB	342	PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0);
bf293aec MR	343	}
bf293aec MR	344
a3f4c927	345	static void pxa_unmask_ext_wakeup(struct irq_data *d)
bf293aec	346	{
a3f4c927 LB	347	ICMR2 \|= 1 << ((d->irq - PXA_IRQ(0)) & 0x1f);
a3f4c927 LB	348	PECR \|= PECR_IE(d->irq - IRQ_WAKEUP0);
bf293aec MR	349	}
bf293aec MR	350
a3f4c927	351	static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type)
12882096 IG	352	{
12882096 IG	353	if (flow_type & IRQ_TYPE_EDGE_RISING)
a3f4c927	354	PWER \|= 1 << (d->irq - IRQ_WAKEUP0);
12882096 IG	355
12882096 IG	356	if (flow_type & IRQ_TYPE_EDGE_FALLING)
a3f4c927	357	PWER \|= 1 << (d->irq - IRQ_WAKEUP0 + 2);
12882096 IG	358
	359	return 0;
	360	}
	361
bf293aec MR	362	static struct irq_chip pxa_ext_wakeup_chip = {
bf293aec MR	363	.name = "WAKEUP",
a3f4c927 LB	364	.irq_ack = pxa_ack_ext_wakeup,
	365	.irq_mask = pxa_mask_ext_wakeup,
	366	.irq_unmask = pxa_unmask_ext_wakeup,
	367	.irq_set_type = pxa_set_ext_wakeup_type,
bf293aec MR	368	};
	369
	370	static void __init pxa_init_ext_wakeup_irq(set_wake_t fn)
	371	{
	372	int irq;
	373
	374	for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
f38c02f3 TG	375	irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip,
f38c02f3 TG	376	handle_edge_irq);
bf293aec MR	377	set_irq_flags(irq, IRQF_VALID);
	378	}
	379
a3f4c927	380	pxa_ext_wakeup_chip.irq_set_wake = fn;
bf293aec MR	381	}
bf293aec MR	382
2c8086a5	383	void __init pxa3xx_init_irq(void)
	384	{
	385	/* enable CP6 access */
	386	u32 value;
	387	__asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
	388	value \|= (1 << 6);
	389	__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
	390
b9e25ace	391	pxa_init_irq(56, pxa3xx_set_wake);
bf293aec	392	pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
a58fbcd8	393	pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
2c8086a5	394	}
2c8086a5	395
851982c1 MV	396	static struct map_desc pxa3xx_io_desc[] __initdata = {
851982c1 MV	397	{ /* Mem Ctl */
ad68bb9f MV	398	.virtual = SMEMC_VIRT,
ad68bb9f MV	399	.pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE),
851982c1 MV	400	.length = 0x00200000,
	401	.type = MT_DEVICE
	402	}
	403	};
	404
	405	void __init pxa3xx_map_io(void)
	406	{
	407	pxa_map_io();
	408	iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
	409	pxa3xx_get_clk_frequency_khz(1);
	410	}
	411
2c8086a5	412	/*
	413	* device registration specific to PXA3xx.
	414	*/
	415
9ba63c4f MR	416	void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
9ba63c4f MR	417	{
14758220	418	pxa_register_device(&pxa3xx_device_i2c_power, info);
9ba63c4f MR	419	}
9ba63c4f MR	420
2c8086a5	421	static struct platform_device *devices[] __initdata = {
94c35a6b	422	&pxa27x_device_udc,
09a5358d	423	&pxa_device_pmu,
2c8086a5	424	&pxa_device_i2s,
f0fba2ad LG	425	&pxa_device_asoc_ssp1,
	426	&pxa_device_asoc_ssp2,
	427	&pxa_device_asoc_ssp3,
	428	&pxa_device_asoc_ssp4,
	429	&pxa_device_asoc_platform,
72493146	430	&sa1100_device_rtc,
2c8086a5	431	&pxa_device_rtc,
d8e0db11	432	&pxa27x_device_ssp1,
	433	&pxa27x_device_ssp2,
	434	&pxa27x_device_ssp3,
	435	&pxa3xx_device_ssp4,
75540c1a	436	&pxa27x_device_pwm0,
75540c1a	437	&pxa27x_device_pwm1,
2c8086a5	438	};
	439
	440	static int __init pxa3xx_init(void)
	441	{
2eaa03b5	442	int ret = 0;
2c8086a5	443
2c8086a5	444	if (cpu_is_pxa3xx()) {
04fef228 EM	445
	446	reset_status = ARSR;
	447
86260f98 DK	448	/*
	449	* clear RDH bit every time after reset
	450	*
	451	* Note: the last 3 bits DxS are write-1-to-clear so carefully
	452	* preserve them here in case they will be referenced later
	453	*/
	454	ASCR &= ~(ASCR_RDH \| ASCR_D1S \| ASCR_D2S \| ASCR_D3S);
	455
0a0300dc	456	clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
2c8086a5	457
fef1f99a	458	if ((ret = pxa_init_dma(IRQ_DMA, 32)))
2c8086a5	459	return ret;
2c8086a5	460
7b5dea12 RK	461	pxa3xx_init_pm();
7b5dea12 RK	462
2eaa03b5 RW	463	register_syscore_ops(&pxa_irq_syscore_ops);
	464	register_syscore_ops(&pxa3xx_mfp_syscore_ops);
	465	register_syscore_ops(&pxa_gpio_syscore_ops);
	466	register_syscore_ops(&pxa3xx_clock_syscore_ops);
c0165504	467
c0165504	468	ret = platform_add_devices(devices, ARRAY_SIZE(devices));
2c8086a5	469	}
c0165504	470
c0165504	471	return ret;
2c8086a5	472	}
2c8086a5	473
1c104e0e	474	postcore_initcall(pxa3xx_init);