[deliverable/linux.git] / arch / arm / mach-pxa / standby.S

/*
 * PXA27x standby mode
 *
 * Author: David Burrage
 *
 * 2005 (c) MontaVista Software, Inc. This file is licensed under
 * the terms of the GNU General Public License version 2. This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */

#include <linux/linkage.h>
#include <asm/assembler.h>
#include <mach/hardware.h>

#include <mach/pxa2xx-regs.h>

		.text

#ifdef CONFIG_PXA27x
ENTRY(pxa_cpu_standby)
	ldr	r0, =PSSR
	mov	r1, #(PSSR_PH | PSSR_STS)
	mov	r2, #PWRMODE_STANDBY
	mov	r3, #UNCACHED_PHYS_0	@ Read mem context in.
	ldr	ip, [r3]
	b	1f

	.align	5
1:	mcr	p14, 0, r2, c7, c0, 0	@ put the system into Standby
	str	r1, [r0]		@ make sure PSSR_PH/STS are clear
	mov	pc, lr

#endif

#ifdef CONFIG_PXA3xx

#define PXA3_MDCNFG		0x0000
#define PXA3_MDCNFG_DMCEN	(1 << 30)
#define PXA3_DDR_HCAL		0x0060
#define PXA3_DDR_HCAL_HCRNG	0x1f
#define PXA3_DDR_HCAL_HCPROG	(1 << 28)
#define PXA3_DDR_HCAL_HCEN	(1 << 31)
#define PXA3_DMCIER		0x0070
#define PXA3_DMCIER_EDLP	(1 << 29)
#define PXA3_DMCISR		0x0078
#define PXA3_RCOMP		0x0100
#define PXA3_RCOMP_SWEVAL	(1 << 31)

ENTRY(pm_enter_standby_start)
	mov	r1, #0xf6000000			@ DMEMC_REG_BASE (PXA3_MDCNFG)
	add	r1, r1, #0x00100000

	/*
	 * Preload the TLB entry for accessing the dynamic memory
	 * controller registers.  Note that page table lookups will
	 * fail until the dynamic memory controller has been
	 * reinitialised - and that includes MMU page table walks.
	 * This also means that only the dynamic memory controller
	 * can be reliably accessed in the code following standby.
	 */
	ldr	r2, [r1]			@ Dummy read PXA3_MDCNFG

	mcr	p14, 0, r0, c7, c0, 0
	.rept	8
	nop
	.endr

	ldr	r0, [r1, #PXA3_DDR_HCAL]	@ Clear (and wait for) HCEN
	bic	r0, r0, #PXA3_DDR_HCAL_HCEN
	str	r0, [r1, #PXA3_DDR_HCAL]
1:	ldr	r0, [r1, #PXA3_DDR_HCAL]
	tst	r0, #PXA3_DDR_HCAL_HCEN
	bne	1b

	ldr	r0, [r1, #PXA3_RCOMP]		@ Initiate RCOMP
	orr	r0, r0, #PXA3_RCOMP_SWEVAL
	str	r0, [r1, #PXA3_RCOMP]

	mov	r0, #~0				@ Clear interrupts
	str	r0, [r1, #PXA3_DMCISR]

	ldr	r0, [r1, #PXA3_DMCIER]		@ set DMIER[EDLP]
	orr	r0, r0, #PXA3_DMCIER_EDLP
	str	r0, [r1, #PXA3_DMCIER]

	ldr	r0, [r1, #PXA3_DDR_HCAL]	@ clear HCRNG, set HCPROG, HCEN
	bic	r0, r0, #PXA3_DDR_HCAL_HCRNG
	orr	r0, r0, #PXA3_DDR_HCAL_HCEN | PXA3_DDR_HCAL_HCPROG
	str	r0, [r1, #PXA3_DDR_HCAL]

1:	ldr	r0, [r1, #PXA3_DMCISR]
	tst	r0, #PXA3_DMCIER_EDLP
	beq	1b

	ldr	r0, [r1, #PXA3_MDCNFG]		@ set PXA3_MDCNFG[DMCEN]
	orr	r0, r0, #PXA3_MDCNFG_DMCEN
	str	r0, [r1, #PXA3_MDCNFG]
1:	ldr	r0, [r1, #PXA3_MDCNFG]
	tst	r0, #PXA3_MDCNFG_DMCEN
	beq	1b

	ldr	r0, [r1, #PXA3_DDR_HCAL]	@ set PXA3_DDR_HCAL[HCRNG]
	orr	r0, r0, #2 @ HCRNG
	str	r0, [r1, #PXA3_DDR_HCAL]

	ldr	r0, [r1, #PXA3_DMCIER]		@ Clear the interrupt
	bic	r0, r0, #0x20000000
	str	r0, [r1, #PXA3_DMCIER]

	mov	pc, lr
ENTRY(pm_enter_standby_end)

#endif
Commit	Line	Data
26705ca4 TP	1	/*
	2	* PXA27x standby mode
	3	*
	4	* Author: David Burrage
	5	*
	6	* 2005 (c) MontaVista Software, Inc. This file is licensed under
	7	* the terms of the GNU General Public License version 2. This program
	8	* is licensed "as is" without any warranty of any kind, whether express
	9	* or implied.
	10	*/
	11
26705ca4 TP	12	#include <linux/linkage.h>
26705ca4 TP	13	#include <asm/assembler.h>
a09e64fb	14	#include <mach/hardware.h>
26705ca4	15
a09e64fb	16	#include <mach/pxa2xx-regs.h>
26705ca4 TP	17
	18	.text
	19
533462fb	20	#ifdef CONFIG_PXA27x
26705ca4 TP	21	ENTRY(pxa_cpu_standby)
	22	ldr r0, =PSSR
	23	mov r1, #(PSSR_PH \| PSSR_STS)
80a18573	24	mov r2, #PWRMODE_STANDBY
26705ca4 TP	25	mov r3, #UNCACHED_PHYS_0 @ Read mem context in.
	26	ldr ip, [r3]
	27	b 1f
	28
	29	.align 5
	30	1: mcr p14, 0, r2, c7, c0, 0 @ put the system into Standby
	31	str r1, [r0] @ make sure PSSR_PH/STS are clear
	32	mov pc, lr
533462fb RK	33
533462fb RK	34	#endif
7b5dea12 RK	35
	36	#ifdef CONFIG_PXA3xx
	37
ffdf7862 RK	38	#define PXA3_MDCNFG 0x0000
	39	#define PXA3_MDCNFG_DMCEN (1 << 30)
	40	#define PXA3_DDR_HCAL 0x0060
	41	#define PXA3_DDR_HCAL_HCRNG 0x1f
	42	#define PXA3_DDR_HCAL_HCPROG (1 << 28)
	43	#define PXA3_DDR_HCAL_HCEN (1 << 31)
	44	#define PXA3_DMCIER 0x0070
	45	#define PXA3_DMCIER_EDLP (1 << 29)
	46	#define PXA3_DMCISR 0x0078
	47	#define PXA3_RCOMP 0x0100
	48	#define PXA3_RCOMP_SWEVAL (1 << 31)
7b5dea12 RK	49
7b5dea12 RK	50	ENTRY(pm_enter_standby_start)
ffdf7862	51	mov r1, #0xf6000000 @ DMEMC_REG_BASE (PXA3_MDCNFG)
7b5dea12 RK	52	add r1, r1, #0x00100000
	53
	54	/*
	55	* Preload the TLB entry for accessing the dynamic memory
	56	* controller registers. Note that page table lookups will
	57	* fail until the dynamic memory controller has been
	58	* reinitialised - and that includes MMU page table walks.
	59	* This also means that only the dynamic memory controller
	60	* can be reliably accessed in the code following standby.
	61	*/
ffdf7862	62	ldr r2, [r1] @ Dummy read PXA3_MDCNFG
7b5dea12 RK	63
	64	mcr p14, 0, r0, c7, c0, 0
	65	.rept 8
	66	nop
	67	.endr
	68
ffdf7862 RK	69	ldr r0, [r1, #PXA3_DDR_HCAL] @ Clear (and wait for) HCEN
	70	bic r0, r0, #PXA3_DDR_HCAL_HCEN
	71	str r0, [r1, #PXA3_DDR_HCAL]
	72	1: ldr r0, [r1, #PXA3_DDR_HCAL]
	73	tst r0, #PXA3_DDR_HCAL_HCEN
7b5dea12 RK	74	bne 1b
7b5dea12 RK	75
ffdf7862 RK	76	ldr r0, [r1, #PXA3_RCOMP] @ Initiate RCOMP
	77	orr r0, r0, #PXA3_RCOMP_SWEVAL
	78	str r0, [r1, #PXA3_RCOMP]
7b5dea12	79
ffdf7862 RK	80	mov r0, #~0 @ Clear interrupts
ffdf7862 RK	81	str r0, [r1, #PXA3_DMCISR]
7b5dea12	82
ffdf7862 RK	83	ldr r0, [r1, #PXA3_DMCIER] @ set DMIER[EDLP]
	84	orr r0, r0, #PXA3_DMCIER_EDLP
	85	str r0, [r1, #PXA3_DMCIER]
7b5dea12	86
ffdf7862 RK	87	ldr r0, [r1, #PXA3_DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN
	88	bic r0, r0, #PXA3_DDR_HCAL_HCRNG
	89	orr r0, r0, #PXA3_DDR_HCAL_HCEN \| PXA3_DDR_HCAL_HCPROG
	90	str r0, [r1, #PXA3_DDR_HCAL]
7b5dea12	91
ffdf7862 RK	92	1: ldr r0, [r1, #PXA3_DMCISR]
ffdf7862 RK	93	tst r0, #PXA3_DMCIER_EDLP
7b5dea12 RK	94	beq 1b
7b5dea12 RK	95
ffdf7862 RK	96	ldr r0, [r1, #PXA3_MDCNFG] @ set PXA3_MDCNFG[DMCEN]
	97	orr r0, r0, #PXA3_MDCNFG_DMCEN
	98	str r0, [r1, #PXA3_MDCNFG]
	99	1: ldr r0, [r1, #PXA3_MDCNFG]
	100	tst r0, #PXA3_MDCNFG_DMCEN
7b5dea12 RK	101	beq 1b
7b5dea12 RK	102
ffdf7862	103	ldr r0, [r1, #PXA3_DDR_HCAL] @ set PXA3_DDR_HCAL[HCRNG]
7b5dea12	104	orr r0, r0, #2 @ HCRNG
ffdf7862	105	str r0, [r1, #PXA3_DDR_HCAL]
7b5dea12	106
ffdf7862	107	ldr r0, [r1, #PXA3_DMCIER] @ Clear the interrupt
7b5dea12	108	bic r0, r0, #0x20000000
ffdf7862	109	str r0, [r1, #PXA3_DMCIER]
7b5dea12 RK	110
	111	mov pc, lr
	112	ENTRY(pm_enter_standby_end)
	113
	114	#endif