[deliverable/linux.git] / arch / arm / mach-pxa / time.c

/*
 * arch/arm/mach-pxa/time.c
 *
 * PXA clocksource, clockevents, and OST interrupt handlers.
 * Copyright (c) 2007 by Bill Gatliff <bgat@billgatliff.com>.
 *
 * Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001
 * by MontaVista Software, Inc.  (Nico, your code rocks!)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/clockchips.h>
#include <linux/sched.h>

#include <asm/div64.h>
#include <asm/cnt32_to_63.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
#include <asm/arch/pxa-regs.h>

/*
 * This is PXA's sched_clock implementation. This has a resolution
 * of at least 308 ns and a maximum value of 208 days.
 *
 * The return value is guaranteed to be monotonic in that range as
 * long as there is always less than 582 seconds between successive
 * calls to sched_clock() which should always be the case in practice.
 */

#define OSCR2NS_SCALE_FACTOR 10

static unsigned long oscr2ns_scale;

static void __init set_oscr2ns_scale(unsigned long oscr_rate)
{
	unsigned long long v = 1000000000ULL << OSCR2NS_SCALE_FACTOR;
	do_div(v, oscr_rate);
	oscr2ns_scale = v;
	/*
	 * We want an even value to automatically clear the top bit
	 * returned by cnt32_to_63() without an additional run time
	 * instruction. So if the LSB is 1 then round it up.
	 */
	if (oscr2ns_scale & 1)
		oscr2ns_scale++;
}

unsigned long long sched_clock(void)
{
	unsigned long long v = cnt32_to_63(OSCR);
	return (v * oscr2ns_scale) >> OSCR2NS_SCALE_FACTOR;
}


static irqreturn_t
pxa_ost0_interrupt(int irq, void *dev_id)
{
	int next_match;
	struct clock_event_device *c = dev_id;

	if (c->mode == CLOCK_EVT_MODE_ONESHOT) {
		/* Disarm the compare/match, signal the event. */
		OIER &= ~OIER_E0;
		c->event_handler(c);
	} else if (c->mode == CLOCK_EVT_MODE_PERIODIC) {
		/* Call the event handler as many times as necessary
		 * to recover missed events, if any (if we update
		 * OSMR0 and OSCR0 is still ahead of us, we've missed
		 * the event).  As we're dealing with that, re-arm the
		 * compare/match for the next event.
		 *
		 * HACK ALERT:
		 *
		 * There's a latency between the instruction that
		 * writes to OSMR0 and the actual commit to the
		 * physical hardware, because the CPU doesn't (have
		 * to) run at bus speed, there's a write buffer
		 * between the CPU and the bus, etc. etc.  So if the
		 * target OSCR0 is "very close", to the OSMR0 load
		 * value, the update to OSMR0 might not get to the
		 * hardware in time and we'll miss that interrupt.
		 *
		 * To be safe, if the new OSMR0 is "very close" to the
		 * target OSCR0 value, we call the event_handler as
		 * though the event actually happened.  According to
		 * Nico's comment in the previous version of this
		 * code, experience has shown that 6 OSCR ticks is
		 * "very close" but he went with 8.  We will use 16,
		 * based on the results of testing on PXA270.
		 *
		 * To be doubly sure, we also tell clkevt via
		 * clockevents_register_device() not to ask for
		 * anything that might put us "very close".
	 */
#define MIN_OSCR_DELTA 16
	do {
			OSSR = OSSR_M0;
		next_match = (OSMR0 += LATCH);
			c->event_handler(c);
		} while (((signed long)(next_match - OSCR) <= MIN_OSCR_DELTA)
			 && (c->mode == CLOCK_EVT_MODE_PERIODIC));
	}

	return IRQ_HANDLED;
}

static int
pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
{
	unsigned long irqflags;

	raw_local_irq_save(irqflags);
	OSMR0 = OSCR + delta;
	OSSR = OSSR_M0;
	OIER |= OIER_E0;
	raw_local_irq_restore(irqflags);
	return 0;
}

static void
pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
{
	unsigned long irqflags;

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		raw_local_irq_save(irqflags);
		OSMR0 = OSCR + LATCH;
		OSSR = OSSR_M0;
		OIER |= OIER_E0;
		raw_local_irq_restore(irqflags);
		break;

	case CLOCK_EVT_MODE_ONESHOT:
		raw_local_irq_save(irqflags);
		OIER &= ~OIER_E0;
		raw_local_irq_restore(irqflags);
		break;

	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		/* initializing, released, or preparing for suspend */
		raw_local_irq_save(irqflags);
		OIER &= ~OIER_E0;
		raw_local_irq_restore(irqflags);
		break;
	}
}

static struct clock_event_device ckevt_pxa_osmr0 = {
	.name		= "osmr0",
	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.shift		= 32,
	.rating		= 200,
	.cpumask	= CPU_MASK_CPU0,
	.set_next_event	= pxa_osmr0_set_next_event,
	.set_mode	= pxa_osmr0_set_mode,
};

static cycle_t pxa_read_oscr(void)
{
	return OSCR;
}

static struct clocksource cksrc_pxa_oscr0 = {
	.name           = "oscr0",
	.rating         = 200,
	.read           = pxa_read_oscr,
	.mask           = CLOCKSOURCE_MASK(32),
	.shift          = 20,
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

static struct irqaction pxa_ost0_irq = {
	.name		= "ost0",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= pxa_ost0_interrupt,
	.dev_id		= &ckevt_pxa_osmr0,
};

static void __init pxa_timer_init(void)
{
	OIER = 0;
	OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;

	set_oscr2ns_scale(CLOCK_TICK_RATE);

	ckevt_pxa_osmr0.mult =
		div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt_pxa_osmr0.shift);
	ckevt_pxa_osmr0.max_delta_ns =
		clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
	ckevt_pxa_osmr0.min_delta_ns =
		clockevent_delta2ns(MIN_OSCR_DELTA, &ckevt_pxa_osmr0) + 1;

	cksrc_pxa_oscr0.mult =
		clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_pxa_oscr0.shift);

	setup_irq(IRQ_OST0, &pxa_ost0_irq);

	clocksource_register(&cksrc_pxa_oscr0);
	clockevents_register_device(&ckevt_pxa_osmr0);
}

#ifdef CONFIG_PM
static unsigned long osmr[4], oier;

static void pxa_timer_suspend(void)
{
	osmr[0] = OSMR0;
	osmr[1] = OSMR1;
	osmr[2] = OSMR2;
	osmr[3] = OSMR3;
	oier = OIER;
}

static void pxa_timer_resume(void)
{
	OSMR0 = osmr[0];
	OSMR1 = osmr[1];
	OSMR2 = osmr[2];
	OSMR3 = osmr[3];
	OIER = oier;

	/*
	 * OSCR0 is the system timer, which has to increase
	 * monotonically until it rolls over in hardware.  The value
	 * (OSMR0 - LATCH) is OSCR0 at the most recent system tick,
	 * which is a handy value to restore to OSCR0.
	 */
	OSCR = OSMR0 - LATCH;
}
#else
#define pxa_timer_suspend NULL
#define pxa_timer_resume NULL
#endif

struct sys_timer pxa_timer = {
	.init		= pxa_timer_init,
	.suspend	= pxa_timer_suspend,
	.resume		= pxa_timer_resume,
};
Commit	Line	Data
1da177e4 LT	1	/*
	2	* arch/arm/mach-pxa/time.c
	3	*
7bbb18c9 BG	4	* PXA clocksource, clockevents, and OST interrupt handlers.
	5	* Copyright (c) 2007 by Bill Gatliff <bgat@billgatliff.com>.
	6	*
	7	* Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001
	8	* by MontaVista Software, Inc. (Nico, your code rocks!)
1da177e4 LT	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
1da177e4 LT	15	#include <linux/kernel.h>
1da177e4 LT	16	#include <linux/init.h>
1da177e4	17	#include <linux/interrupt.h>
7bbb18c9	18	#include <linux/clockchips.h>
6c3a1583	19	#include <linux/sched.h>
7bbb18c9	20
6c3a1583 NP	21	#include <asm/div64.h>
6c3a1583 NP	22	#include <asm/cnt32_to_63.h>
1da177e4 LT	23	#include <asm/mach/irq.h>
	24	#include <asm/mach/time.h>
	25	#include <asm/arch/pxa-regs.h>
	26
6c3a1583 NP	27	/*
	28	* This is PXA's sched_clock implementation. This has a resolution
	29	* of at least 308 ns and a maximum value of 208 days.
	30	*
	31	* The return value is guaranteed to be monotonic in that range as
	32	* long as there is always less than 582 seconds between successive
	33	* calls to sched_clock() which should always be the case in practice.
	34	*/
	35
	36	#define OSCR2NS_SCALE_FACTOR 10
	37
	38	static unsigned long oscr2ns_scale;
	39
	40	static void __init set_oscr2ns_scale(unsigned long oscr_rate)
	41	{
	42	unsigned long long v = 1000000000ULL << OSCR2NS_SCALE_FACTOR;
	43	do_div(v, oscr_rate);
	44	oscr2ns_scale = v;
	45	/*
	46	* We want an even value to automatically clear the top bit
	47	* returned by cnt32_to_63() without an additional run time
	48	* instruction. So if the LSB is 1 then round it up.
	49	*/
	50	if (oscr2ns_scale & 1)
	51	oscr2ns_scale++;
	52	}
	53
	54	unsigned long long sched_clock(void)
	55	{
	56	unsigned long long v = cnt32_to_63(OSCR);
	57	return (v * oscr2ns_scale) >> OSCR2NS_SCALE_FACTOR;
	58	}
	59
	60
1da177e4	61	static irqreturn_t
7bbb18c9	62	pxa_ost0_interrupt(int irq, void *dev_id)
1da177e4 LT	63	{
1da177e4 LT	64	int next_match;
7bbb18c9 BG	65	struct clock_event_device *c = dev_id;
	66
	67	if (c->mode == CLOCK_EVT_MODE_ONESHOT) {
	68	/* Disarm the compare/match, signal the event. */
	69	OIER &= ~OIER_E0;
	70	c->event_handler(c);
	71	} else if (c->mode == CLOCK_EVT_MODE_PERIODIC) {
	72	/* Call the event handler as many times as necessary
	73	* to recover missed events, if any (if we update
	74	* OSMR0 and OSCR0 is still ahead of us, we've missed
	75	* the event). As we're dealing with that, re-arm the
	76	* compare/match for the next event.
	77	*
	78	* HACK ALERT:
	79	*
	80	* There's a latency between the instruction that
	81	* writes to OSMR0 and the actual commit to the
	82	* physical hardware, because the CPU doesn't (have
	83	* to) run at bus speed, there's a write buffer
	84	* between the CPU and the bus, etc. etc. So if the
	85	* target OSCR0 is "very close", to the OSMR0 load
	86	* value, the update to OSMR0 might not get to the
	87	* hardware in time and we'll miss that interrupt.
	88	*
	89	* To be safe, if the new OSMR0 is "very close" to the
	90	* target OSCR0 value, we call the event_handler as
	91	* though the event actually happened. According to
	92	* Nico's comment in the previous version of this
	93	* code, experience has shown that 6 OSCR ticks is
	94	* "very close" but he went with 8. We will use 16,
	95	* based on the results of testing on PXA270.
	96	*
	97	* To be doubly sure, we also tell clkevt via
	98	* clockevents_register_device() not to ask for
	99	* anything that might put us "very close".
1da177e4	100	*/
7bbb18c9	101	#define MIN_OSCR_DELTA 16
1da177e4	102	do {
7bbb18c9	103	OSSR = OSSR_M0;
1da177e4	104	next_match = (OSMR0 += LATCH);
7bbb18c9 BG	105	c->event_handler(c);
	106	} while (((signed long)(next_match - OSCR) <= MIN_OSCR_DELTA)
	107	&& (c->mode == CLOCK_EVT_MODE_PERIODIC));
	108	}
1da177e4 LT	109
	110	return IRQ_HANDLED;
	111	}
	112
7bbb18c9 BG	113	static int
	114	pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
	115	{
	116	unsigned long irqflags;
	117
	118	raw_local_irq_save(irqflags);
	119	OSMR0 = OSCR + delta;
	120	OSSR = OSSR_M0;
	121	OIER \|= OIER_E0;
	122	raw_local_irq_restore(irqflags);
	123	return 0;
	124	}
	125
	126	static void
	127	pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
	128	{
	129	unsigned long irqflags;
	130
	131	switch (mode) {
	132	case CLOCK_EVT_MODE_PERIODIC:
	133	raw_local_irq_save(irqflags);
	134	OSMR0 = OSCR + LATCH;
	135	OSSR = OSSR_M0;
	136	OIER \|= OIER_E0;
	137	raw_local_irq_restore(irqflags);
	138	break;
	139
	140	case CLOCK_EVT_MODE_ONESHOT:
	141	raw_local_irq_save(irqflags);
	142	OIER &= ~OIER_E0;
	143	raw_local_irq_restore(irqflags);
	144	break;
	145
	146	case CLOCK_EVT_MODE_UNUSED:
	147	case CLOCK_EVT_MODE_SHUTDOWN:
	148	/* initializing, released, or preparing for suspend */
	149	raw_local_irq_save(irqflags);
	150	OIER &= ~OIER_E0;
	151	raw_local_irq_restore(irqflags);
	152	break;
	153	}
	154	}
	155
	156	static struct clock_event_device ckevt_pxa_osmr0 = {
	157	.name = "osmr0",
	158	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	159	.shift = 32,
	160	.rating = 200,
	161	.cpumask = CPU_MASK_CPU0,
	162	.set_next_event = pxa_osmr0_set_next_event,
	163	.set_mode = pxa_osmr0_set_mode,
1da177e4 LT	164	};
1da177e4 LT	165
7bbb18c9	166	static cycle_t pxa_read_oscr(void)
c80204e5 SH	167	{
	168	return OSCR;
	169	}
	170
7bbb18c9 BG	171	static struct clocksource cksrc_pxa_oscr0 = {
7bbb18c9 BG	172	.name = "oscr0",
c80204e5	173	.rating = 200,
7bbb18c9	174	.read = pxa_read_oscr,
c80204e5 SH	175	.mask = CLOCKSOURCE_MASK(32),
c80204e5 SH	176	.shift = 20,
c66699a7	177	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
c80204e5 SH	178	};
c80204e5 SH	179
7bbb18c9 BG	180	static struct irqaction pxa_ost0_irq = {
	181	.name = "ost0",
	182	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
	183	.handler = pxa_ost0_interrupt,
	184	.dev_id = &ckevt_pxa_osmr0,
	185	};
	186
1da177e4 LT	187	static void __init pxa_timer_init(void)
1da177e4 LT	188	{
7bbb18c9 BG	189	OIER = 0;
7bbb18c9 BG	190	OSSR = OSSR_M0 \| OSSR_M1 \| OSSR_M2 \| OSSR_M3;
1da177e4	191
6c3a1583 NP	192	set_oscr2ns_scale(CLOCK_TICK_RATE);
6c3a1583 NP	193
7bbb18c9 BG	194	ckevt_pxa_osmr0.mult =
	195	div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt_pxa_osmr0.shift);
	196	ckevt_pxa_osmr0.max_delta_ns =
	197	clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
	198	ckevt_pxa_osmr0.min_delta_ns =
	199	clockevent_delta2ns(MIN_OSCR_DELTA, &ckevt_pxa_osmr0) + 1;
1da177e4	200
7bbb18c9 BG	201	cksrc_pxa_oscr0.mult =
7bbb18c9 BG	202	clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_pxa_oscr0.shift);
5c53ff08	203
7bbb18c9	204	setup_irq(IRQ_OST0, &pxa_ost0_irq);
5c53ff08	205
7bbb18c9 BG	206	clocksource_register(&cksrc_pxa_oscr0);
7bbb18c9 BG	207	clockevents_register_device(&ckevt_pxa_osmr0);
5c53ff08 NP	208	}
5c53ff08 NP	209
1da177e4 LT	210	#ifdef CONFIG_PM
	211	static unsigned long osmr[4], oier;
	212
	213	static void pxa_timer_suspend(void)
	214	{
	215	osmr[0] = OSMR0;
	216	osmr[1] = OSMR1;
	217	osmr[2] = OSMR2;
	218	osmr[3] = OSMR3;
	219	oier = OIER;
	220	}
	221
	222	static void pxa_timer_resume(void)
	223	{
	224	OSMR0 = osmr[0];
	225	OSMR1 = osmr[1];
	226	OSMR2 = osmr[2];
	227	OSMR3 = osmr[3];
	228	OIER = oier;
	229
	230	/*
7bbb18c9 BG	231	* OSCR0 is the system timer, which has to increase
	232	* monotonically until it rolls over in hardware. The value
	233	* (OSMR0 - LATCH) is OSCR0 at the most recent system tick,
	234	* which is a handy value to restore to OSCR0.
1da177e4 LT	235	*/
	236	OSCR = OSMR0 - LATCH;
	237	}
	238	#else
	239	#define pxa_timer_suspend NULL
	240	#define pxa_timer_resume NULL
	241	#endif
	242
	243	struct sys_timer pxa_timer = {
	244	.init = pxa_timer_init,
	245	.suspend = pxa_timer_suspend,
	246	.resume = pxa_timer_resume,
1da177e4	247	};