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e491a11c MZ |
1 | /* |
2 | * Support for the Arcom ZEUS. | |
3 | * | |
4 | * Copyright (C) 2006 Arcom Control Systems Ltd. | |
5 | * | |
6 | * Loosely based on Arcom's 2.6.16.28. | |
7 | * Maintained by Marc Zyngier <maz@misterjones.org> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/cpufreq.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/irq.h> | |
17 | #include <linux/pm.h> | |
18 | #include <linux/gpio.h> | |
19 | #include <linux/serial_8250.h> | |
20 | #include <linux/dm9000.h> | |
21 | #include <linux/mmc/host.h> | |
22 | #include <linux/spi/spi.h> | |
23 | #include <linux/mtd/mtd.h> | |
24 | #include <linux/mtd/partitions.h> | |
25 | #include <linux/mtd/physmap.h> | |
26 | #include <linux/i2c.h> | |
27 | #include <linux/i2c/pca953x.h> | |
a1916eb0 | 28 | #include <linux/apm-emulation.h> |
e491a11c MZ |
29 | |
30 | #include <asm/mach-types.h> | |
31 | #include <asm/mach/arch.h> | |
32 | #include <asm/mach/map.h> | |
33 | ||
34 | #include <plat/i2c.h> | |
35 | ||
36 | #include <mach/pxa2xx-regs.h> | |
37 | #include <mach/regs-uart.h> | |
38 | #include <mach/ohci.h> | |
39 | #include <mach/mmc.h> | |
40 | #include <mach/pxa27x-udc.h> | |
41 | #include <mach/udc.h> | |
42 | #include <mach/pxafb.h> | |
43 | #include <mach/pxa2xx_spi.h> | |
44 | #include <mach/mfp-pxa27x.h> | |
45 | #include <mach/pm.h> | |
46 | #include <mach/audio.h> | |
c2de1c38 | 47 | #include <mach/arcom-pcmcia.h> |
e491a11c MZ |
48 | #include <mach/zeus.h> |
49 | ||
50 | #include "generic.h" | |
51 | ||
52 | /* | |
53 | * Interrupt handling | |
54 | */ | |
55 | ||
56 | static unsigned long zeus_irq_enabled_mask; | |
57 | static const int zeus_isa_irqs[] = { 3, 4, 5, 6, 7, 10, 11, 12, }; | |
58 | static const int zeus_isa_irq_map[] = { | |
59 | 0, /* ISA irq #0, invalid */ | |
60 | 0, /* ISA irq #1, invalid */ | |
61 | 0, /* ISA irq #2, invalid */ | |
62 | 1 << 0, /* ISA irq #3 */ | |
63 | 1 << 1, /* ISA irq #4 */ | |
64 | 1 << 2, /* ISA irq #5 */ | |
65 | 1 << 3, /* ISA irq #6 */ | |
66 | 1 << 4, /* ISA irq #7 */ | |
67 | 0, /* ISA irq #8, invalid */ | |
68 | 0, /* ISA irq #9, invalid */ | |
69 | 1 << 5, /* ISA irq #10 */ | |
70 | 1 << 6, /* ISA irq #11 */ | |
71 | 1 << 7, /* ISA irq #12 */ | |
72 | }; | |
73 | ||
74 | static inline int zeus_irq_to_bitmask(unsigned int irq) | |
75 | { | |
76 | return zeus_isa_irq_map[irq - PXA_ISA_IRQ(0)]; | |
77 | } | |
78 | ||
79 | static inline int zeus_bit_to_irq(int bit) | |
80 | { | |
81 | return zeus_isa_irqs[bit] + PXA_ISA_IRQ(0); | |
82 | } | |
83 | ||
84 | static void zeus_ack_irq(unsigned int irq) | |
85 | { | |
86 | __raw_writew(zeus_irq_to_bitmask(irq), ZEUS_CPLD_ISA_IRQ); | |
87 | } | |
88 | ||
89 | static void zeus_mask_irq(unsigned int irq) | |
90 | { | |
91 | zeus_irq_enabled_mask &= ~(zeus_irq_to_bitmask(irq)); | |
92 | } | |
93 | ||
94 | static void zeus_unmask_irq(unsigned int irq) | |
95 | { | |
96 | zeus_irq_enabled_mask |= zeus_irq_to_bitmask(irq); | |
97 | } | |
98 | ||
99 | static inline unsigned long zeus_irq_pending(void) | |
100 | { | |
101 | return __raw_readw(ZEUS_CPLD_ISA_IRQ) & zeus_irq_enabled_mask; | |
102 | } | |
103 | ||
104 | static void zeus_irq_handler(unsigned int irq, struct irq_desc *desc) | |
105 | { | |
106 | unsigned long pending; | |
107 | ||
108 | pending = zeus_irq_pending(); | |
109 | do { | |
110 | /* we're in a chained irq handler, | |
111 | * so ack the interrupt by hand */ | |
112 | desc->chip->ack(gpio_to_irq(ZEUS_ISA_GPIO)); | |
113 | ||
114 | if (likely(pending)) { | |
115 | irq = zeus_bit_to_irq(__ffs(pending)); | |
116 | generic_handle_irq(irq); | |
117 | } | |
118 | pending = zeus_irq_pending(); | |
119 | } while (pending); | |
120 | } | |
121 | ||
122 | static struct irq_chip zeus_irq_chip = { | |
123 | .name = "ISA", | |
124 | .ack = zeus_ack_irq, | |
125 | .mask = zeus_mask_irq, | |
126 | .unmask = zeus_unmask_irq, | |
127 | }; | |
128 | ||
129 | static void __init zeus_init_irq(void) | |
130 | { | |
131 | int level; | |
132 | int isa_irq; | |
133 | ||
134 | pxa27x_init_irq(); | |
135 | ||
136 | /* Peripheral IRQs. It would be nice to move those inside driver | |
137 | configuration, but it is not supported at the moment. */ | |
138 | set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING); | |
139 | set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING); | |
140 | set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING); | |
141 | set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO), IRQ_TYPE_EDGE_FALLING); | |
142 | set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING); | |
143 | ||
144 | /* Setup ISA IRQs */ | |
145 | for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) { | |
146 | isa_irq = zeus_bit_to_irq(level); | |
147 | set_irq_chip(isa_irq, &zeus_irq_chip); | |
148 | set_irq_handler(isa_irq, handle_edge_irq); | |
149 | set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE); | |
150 | } | |
151 | ||
152 | set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING); | |
153 | set_irq_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler); | |
154 | } | |
155 | ||
156 | ||
157 | /* | |
158 | * Platform devices | |
159 | */ | |
160 | ||
161 | /* Flash */ | |
162 | static struct resource zeus_mtd_resources[] = { | |
163 | [0] = { /* NOR Flash (up to 64MB) */ | |
164 | .start = ZEUS_FLASH_PHYS, | |
165 | .end = ZEUS_FLASH_PHYS + SZ_64M - 1, | |
166 | .flags = IORESOURCE_MEM, | |
167 | }, | |
168 | [1] = { /* SRAM */ | |
169 | .start = ZEUS_SRAM_PHYS, | |
170 | .end = ZEUS_SRAM_PHYS + SZ_512K - 1, | |
171 | .flags = IORESOURCE_MEM, | |
172 | }, | |
173 | }; | |
174 | ||
175 | static struct physmap_flash_data zeus_flash_data[] = { | |
176 | [0] = { | |
177 | .width = 2, | |
178 | .parts = NULL, | |
179 | .nr_parts = 0, | |
180 | }, | |
181 | }; | |
182 | ||
183 | static struct platform_device zeus_mtd_devices[] = { | |
184 | [0] = { | |
185 | .name = "physmap-flash", | |
186 | .id = 0, | |
187 | .dev = { | |
188 | .platform_data = &zeus_flash_data[0], | |
189 | }, | |
190 | .resource = &zeus_mtd_resources[0], | |
191 | .num_resources = 1, | |
192 | }, | |
193 | }; | |
194 | ||
195 | /* Serial */ | |
196 | static struct resource zeus_serial_resources[] = { | |
197 | { | |
198 | .start = 0x10000000, | |
199 | .end = 0x1000000f, | |
200 | .flags = IORESOURCE_MEM, | |
201 | }, | |
202 | { | |
203 | .start = 0x10800000, | |
204 | .end = 0x1080000f, | |
205 | .flags = IORESOURCE_MEM, | |
206 | }, | |
207 | { | |
208 | .start = 0x11000000, | |
209 | .end = 0x1100000f, | |
210 | .flags = IORESOURCE_MEM, | |
211 | }, | |
212 | { | |
213 | .start = 0x40100000, | |
214 | .end = 0x4010001f, | |
215 | .flags = IORESOURCE_MEM, | |
216 | }, | |
217 | { | |
218 | .start = 0x40200000, | |
219 | .end = 0x4020001f, | |
220 | .flags = IORESOURCE_MEM, | |
221 | }, | |
222 | { | |
223 | .start = 0x40700000, | |
224 | .end = 0x4070001f, | |
225 | .flags = IORESOURCE_MEM, | |
226 | }, | |
227 | }; | |
228 | ||
229 | static struct plat_serial8250_port serial_platform_data[] = { | |
230 | /* External UARTs */ | |
231 | /* FIXME: Shared IRQs on COM1-COM4 will not work properly on v1i1 hardware. */ | |
232 | { /* COM1 */ | |
233 | .mapbase = 0x10000000, | |
234 | .irq = gpio_to_irq(ZEUS_UARTA_GPIO), | |
235 | .irqflags = IRQF_TRIGGER_RISING, | |
236 | .uartclk = 14745600, | |
237 | .regshift = 1, | |
238 | .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, | |
239 | .iotype = UPIO_MEM, | |
240 | }, | |
241 | { /* COM2 */ | |
242 | .mapbase = 0x10800000, | |
243 | .irq = gpio_to_irq(ZEUS_UARTB_GPIO), | |
244 | .irqflags = IRQF_TRIGGER_RISING, | |
245 | .uartclk = 14745600, | |
246 | .regshift = 1, | |
247 | .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, | |
248 | .iotype = UPIO_MEM, | |
249 | }, | |
250 | { /* COM3 */ | |
251 | .mapbase = 0x11000000, | |
252 | .irq = gpio_to_irq(ZEUS_UARTC_GPIO), | |
253 | .irqflags = IRQF_TRIGGER_RISING, | |
254 | .uartclk = 14745600, | |
255 | .regshift = 1, | |
256 | .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, | |
257 | .iotype = UPIO_MEM, | |
258 | }, | |
259 | { /* COM4 */ | |
260 | .mapbase = 0x11800000, | |
261 | .irq = gpio_to_irq(ZEUS_UARTD_GPIO), | |
262 | .irqflags = IRQF_TRIGGER_RISING, | |
263 | .uartclk = 14745600, | |
264 | .regshift = 1, | |
265 | .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, | |
266 | .iotype = UPIO_MEM, | |
267 | }, | |
268 | /* Internal UARTs */ | |
269 | { /* FFUART */ | |
270 | .membase = (void *)&FFUART, | |
271 | .mapbase = __PREG(FFUART), | |
272 | .irq = IRQ_FFUART, | |
273 | .uartclk = 921600 * 16, | |
274 | .regshift = 2, | |
275 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, | |
276 | .iotype = UPIO_MEM, | |
277 | }, | |
278 | { /* BTUART */ | |
279 | .membase = (void *)&BTUART, | |
280 | .mapbase = __PREG(BTUART), | |
281 | .irq = IRQ_BTUART, | |
282 | .uartclk = 921600 * 16, | |
283 | .regshift = 2, | |
284 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, | |
285 | .iotype = UPIO_MEM, | |
286 | }, | |
287 | { /* STUART */ | |
288 | .membase = (void *)&STUART, | |
289 | .mapbase = __PREG(STUART), | |
290 | .irq = IRQ_STUART, | |
291 | .uartclk = 921600 * 16, | |
292 | .regshift = 2, | |
293 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, | |
294 | .iotype = UPIO_MEM, | |
295 | }, | |
296 | { }, | |
297 | }; | |
298 | ||
299 | static struct platform_device zeus_serial_device = { | |
300 | .name = "serial8250", | |
301 | .id = PLAT8250_DEV_PLATFORM, | |
302 | .dev = { | |
303 | .platform_data = serial_platform_data, | |
304 | }, | |
305 | .num_resources = ARRAY_SIZE(zeus_serial_resources), | |
306 | .resource = zeus_serial_resources, | |
307 | }; | |
308 | ||
309 | /* Ethernet */ | |
310 | static struct resource zeus_dm9k0_resource[] = { | |
311 | [0] = { | |
312 | .start = ZEUS_ETH0_PHYS, | |
313 | .end = ZEUS_ETH0_PHYS + 1, | |
314 | .flags = IORESOURCE_MEM | |
315 | }, | |
316 | [1] = { | |
317 | .start = ZEUS_ETH0_PHYS + 2, | |
318 | .end = ZEUS_ETH0_PHYS + 3, | |
319 | .flags = IORESOURCE_MEM | |
320 | }, | |
321 | [2] = { | |
322 | .start = gpio_to_irq(ZEUS_ETH0_GPIO), | |
323 | .end = gpio_to_irq(ZEUS_ETH0_GPIO), | |
324 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, | |
325 | }, | |
326 | }; | |
327 | ||
328 | static struct resource zeus_dm9k1_resource[] = { | |
329 | [0] = { | |
330 | .start = ZEUS_ETH1_PHYS, | |
331 | .end = ZEUS_ETH1_PHYS + 1, | |
332 | .flags = IORESOURCE_MEM | |
333 | }, | |
334 | [1] = { | |
335 | .start = ZEUS_ETH1_PHYS + 2, | |
336 | .end = ZEUS_ETH1_PHYS + 3, | |
337 | .flags = IORESOURCE_MEM, | |
338 | }, | |
339 | [2] = { | |
340 | .start = gpio_to_irq(ZEUS_ETH1_GPIO), | |
341 | .end = gpio_to_irq(ZEUS_ETH1_GPIO), | |
342 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, | |
343 | }, | |
344 | }; | |
345 | ||
346 | static struct dm9000_plat_data zeus_dm9k_platdata = { | |
347 | .flags = DM9000_PLATF_16BITONLY, | |
348 | }; | |
349 | ||
350 | static struct platform_device zeus_dm9k0_device = { | |
351 | .name = "dm9000", | |
352 | .id = 0, | |
353 | .num_resources = ARRAY_SIZE(zeus_dm9k0_resource), | |
354 | .resource = zeus_dm9k0_resource, | |
355 | .dev = { | |
356 | .platform_data = &zeus_dm9k_platdata, | |
357 | } | |
358 | }; | |
359 | ||
360 | static struct platform_device zeus_dm9k1_device = { | |
361 | .name = "dm9000", | |
362 | .id = 1, | |
363 | .num_resources = ARRAY_SIZE(zeus_dm9k1_resource), | |
364 | .resource = zeus_dm9k1_resource, | |
365 | .dev = { | |
366 | .platform_data = &zeus_dm9k_platdata, | |
367 | } | |
368 | }; | |
369 | ||
370 | /* External SRAM */ | |
371 | static struct resource zeus_sram_resource = { | |
372 | .start = ZEUS_SRAM_PHYS, | |
373 | .end = ZEUS_SRAM_PHYS + ZEUS_SRAM_SIZE * 2 - 1, | |
374 | .flags = IORESOURCE_MEM, | |
375 | }; | |
376 | ||
377 | static struct platform_device zeus_sram_device = { | |
378 | .name = "pxa2xx-8bit-sram", | |
379 | .id = 0, | |
380 | .num_resources = 1, | |
381 | .resource = &zeus_sram_resource, | |
382 | }; | |
383 | ||
384 | /* SPI interface on SSP3 */ | |
385 | static struct pxa2xx_spi_master pxa2xx_spi_ssp3_master_info = { | |
386 | .num_chipselect = 1, | |
387 | .enable_dma = 1, | |
388 | }; | |
389 | ||
390 | static struct platform_device pxa2xx_spi_ssp3_device = { | |
391 | .name = "pxa2xx-spi", | |
392 | .id = 3, | |
393 | .dev = { | |
394 | .platform_data = &pxa2xx_spi_ssp3_master_info, | |
395 | }, | |
396 | }; | |
397 | ||
398 | /* Leds */ | |
399 | static struct gpio_led zeus_leds[] = { | |
400 | [0] = { | |
401 | .name = "zeus:yellow:1", | |
402 | .default_trigger = "heartbeat", | |
403 | .gpio = ZEUS_EXT0_GPIO(3), | |
404 | .active_low = 1, | |
405 | }, | |
406 | [1] = { | |
407 | .name = "zeus:yellow:2", | |
408 | .default_trigger = "default-on", | |
409 | .gpio = ZEUS_EXT0_GPIO(4), | |
410 | .active_low = 1, | |
411 | }, | |
412 | [2] = { | |
413 | .name = "zeus:yellow:3", | |
414 | .default_trigger = "default-on", | |
415 | .gpio = ZEUS_EXT0_GPIO(5), | |
416 | .active_low = 1, | |
417 | }, | |
418 | }; | |
419 | ||
420 | static struct gpio_led_platform_data zeus_leds_info = { | |
421 | .leds = zeus_leds, | |
422 | .num_leds = ARRAY_SIZE(zeus_leds), | |
423 | }; | |
424 | ||
425 | static struct platform_device zeus_leds_device = { | |
426 | .name = "leds-gpio", | |
427 | .id = -1, | |
428 | .dev = { | |
429 | .platform_data = &zeus_leds_info, | |
430 | }, | |
431 | }; | |
432 | ||
c2de1c38 MZ |
433 | static void zeus_cf_reset(int state) |
434 | { | |
435 | u16 cpld_state = __raw_readw(ZEUS_CPLD_CONTROL); | |
436 | ||
437 | if (state) | |
438 | cpld_state |= ZEUS_CPLD_CONTROL_CF_RST; | |
439 | else | |
440 | cpld_state &= ~ZEUS_CPLD_CONTROL_CF_RST; | |
441 | ||
442 | __raw_writew(cpld_state, ZEUS_CPLD_CONTROL); | |
443 | } | |
444 | ||
445 | static struct arcom_pcmcia_pdata zeus_pcmcia_info = { | |
446 | .cd_gpio = ZEUS_CF_CD_GPIO, | |
447 | .rdy_gpio = ZEUS_CF_RDY_GPIO, | |
448 | .pwr_gpio = ZEUS_CF_PWEN_GPIO, | |
449 | .reset = zeus_cf_reset, | |
450 | }; | |
451 | ||
452 | static struct platform_device zeus_pcmcia_device = { | |
453 | .name = "zeus-pcmcia", | |
454 | .id = -1, | |
455 | .dev = { | |
456 | .platform_data = &zeus_pcmcia_info, | |
457 | }, | |
458 | }; | |
459 | ||
fcfdc67f MZ |
460 | static struct resource zeus_max6369_resource = { |
461 | .start = ZEUS_CPLD_EXTWDOG_PHYS, | |
462 | .end = ZEUS_CPLD_EXTWDOG_PHYS, | |
463 | .flags = IORESOURCE_MEM, | |
464 | }; | |
465 | ||
466 | struct platform_device zeus_max6369_device = { | |
467 | .name = "max6369_wdt", | |
468 | .id = -1, | |
469 | .resource = &zeus_max6369_resource, | |
470 | .num_resources = 1, | |
471 | }; | |
472 | ||
e491a11c MZ |
473 | static struct platform_device *zeus_devices[] __initdata = { |
474 | &zeus_serial_device, | |
475 | &zeus_mtd_devices[0], | |
476 | &zeus_dm9k0_device, | |
477 | &zeus_dm9k1_device, | |
478 | &zeus_sram_device, | |
479 | &pxa2xx_spi_ssp3_device, | |
480 | &zeus_leds_device, | |
c2de1c38 | 481 | &zeus_pcmcia_device, |
fcfdc67f | 482 | &zeus_max6369_device, |
e491a11c MZ |
483 | }; |
484 | ||
485 | /* AC'97 */ | |
486 | static pxa2xx_audio_ops_t zeus_ac97_info = { | |
487 | .reset_gpio = 95, | |
488 | }; | |
489 | ||
490 | ||
491 | /* | |
492 | * USB host | |
493 | */ | |
494 | ||
495 | static int zeus_ohci_init(struct device *dev) | |
496 | { | |
497 | int err; | |
498 | ||
499 | /* Switch on port 2. */ | |
500 | if ((err = gpio_request(ZEUS_USB2_PWREN_GPIO, "USB2_PWREN"))) { | |
501 | dev_err(dev, "Can't request USB2_PWREN\n"); | |
502 | return err; | |
503 | } | |
504 | ||
505 | if ((err = gpio_direction_output(ZEUS_USB2_PWREN_GPIO, 1))) { | |
506 | gpio_free(ZEUS_USB2_PWREN_GPIO); | |
507 | dev_err(dev, "Can't enable USB2_PWREN\n"); | |
508 | return err; | |
509 | } | |
510 | ||
511 | /* Port 2 is shared between host and client interface. */ | |
512 | UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE; | |
513 | ||
514 | return 0; | |
515 | } | |
516 | ||
517 | static void zeus_ohci_exit(struct device *dev) | |
518 | { | |
519 | /* Power-off port 2 */ | |
520 | gpio_direction_output(ZEUS_USB2_PWREN_GPIO, 0); | |
521 | gpio_free(ZEUS_USB2_PWREN_GPIO); | |
522 | } | |
523 | ||
524 | static struct pxaohci_platform_data zeus_ohci_platform_data = { | |
525 | .port_mode = PMM_NPS_MODE, | |
7ff27dfa MZ |
526 | /* Clear Power Control Polarity Low and set Power Sense |
527 | * Polarity Low. Supply power to USB ports. */ | |
528 | .flags = ENABLE_PORT_ALL | POWER_SENSE_LOW, | |
e491a11c MZ |
529 | .init = zeus_ohci_init, |
530 | .exit = zeus_ohci_exit, | |
531 | }; | |
532 | ||
533 | /* | |
534 | * Flat Panel | |
535 | */ | |
536 | ||
537 | static void zeus_lcd_power(int on, struct fb_var_screeninfo *si) | |
538 | { | |
539 | gpio_set_value(ZEUS_LCD_EN_GPIO, on); | |
540 | } | |
541 | ||
542 | static void zeus_backlight_power(int on) | |
543 | { | |
544 | gpio_set_value(ZEUS_BKLEN_GPIO, on); | |
545 | } | |
546 | ||
547 | static int zeus_setup_fb_gpios(void) | |
548 | { | |
549 | int err; | |
550 | ||
551 | if ((err = gpio_request(ZEUS_LCD_EN_GPIO, "LCD_EN"))) | |
552 | goto out_err; | |
553 | ||
554 | if ((err = gpio_direction_output(ZEUS_LCD_EN_GPIO, 0))) | |
555 | goto out_err_lcd; | |
556 | ||
557 | if ((err = gpio_request(ZEUS_BKLEN_GPIO, "BKLEN"))) | |
558 | goto out_err_lcd; | |
559 | ||
560 | if ((err = gpio_direction_output(ZEUS_BKLEN_GPIO, 0))) | |
561 | goto out_err_bkl; | |
562 | ||
563 | return 0; | |
564 | ||
565 | out_err_bkl: | |
566 | gpio_free(ZEUS_BKLEN_GPIO); | |
567 | out_err_lcd: | |
568 | gpio_free(ZEUS_LCD_EN_GPIO); | |
569 | out_err: | |
570 | return err; | |
571 | } | |
572 | ||
573 | static struct pxafb_mode_info zeus_fb_mode_info[] = { | |
574 | { | |
575 | .pixclock = 39722, | |
576 | ||
577 | .xres = 640, | |
578 | .yres = 480, | |
579 | ||
580 | .bpp = 16, | |
581 | ||
582 | .hsync_len = 63, | |
583 | .left_margin = 16, | |
584 | .right_margin = 81, | |
585 | ||
586 | .vsync_len = 2, | |
587 | .upper_margin = 12, | |
588 | .lower_margin = 31, | |
589 | ||
590 | .sync = 0, | |
591 | }, | |
592 | }; | |
593 | ||
594 | static struct pxafb_mach_info zeus_fb_info = { | |
595 | .modes = zeus_fb_mode_info, | |
596 | .num_modes = 1, | |
597 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, | |
598 | .pxafb_lcd_power = zeus_lcd_power, | |
599 | .pxafb_backlight_power = zeus_backlight_power, | |
600 | }; | |
601 | ||
602 | /* | |
603 | * MMC/SD Device | |
604 | * | |
605 | * The card detect interrupt isn't debounced so we delay it by 250ms | |
606 | * to give the card a chance to fully insert/eject. | |
607 | */ | |
608 | ||
609 | static struct pxamci_platform_data zeus_mci_platform_data = { | |
610 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, | |
611 | .detect_delay = HZ/4, | |
612 | .gpio_card_detect = ZEUS_MMC_CD_GPIO, | |
613 | .gpio_card_ro = ZEUS_MMC_WP_GPIO, | |
614 | .gpio_card_ro_invert = 1, | |
615 | .gpio_power = -1 | |
616 | }; | |
617 | ||
618 | /* | |
619 | * USB Device Controller | |
620 | */ | |
621 | static void zeus_udc_command(int cmd) | |
622 | { | |
623 | switch (cmd) { | |
624 | case PXA2XX_UDC_CMD_DISCONNECT: | |
625 | pr_info("zeus: disconnecting USB client\n"); | |
626 | UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE; | |
627 | break; | |
628 | ||
629 | case PXA2XX_UDC_CMD_CONNECT: | |
630 | pr_info("zeus: connecting USB client\n"); | |
631 | UP2OCR = UP2OCR_HXOE | UP2OCR_DPPUE; | |
632 | break; | |
633 | } | |
634 | } | |
635 | ||
636 | static struct pxa2xx_udc_mach_info zeus_udc_info = { | |
637 | .udc_command = zeus_udc_command, | |
638 | }; | |
639 | ||
98acdbe4 | 640 | #ifdef CONFIG_PM |
e491a11c MZ |
641 | static void zeus_power_off(void) |
642 | { | |
643 | local_irq_disable(); | |
644 | pxa27x_cpu_suspend(PWRMODE_DEEPSLEEP); | |
645 | } | |
98acdbe4 SS |
646 | #else |
647 | #define zeus_power_off NULL | |
648 | #endif | |
e491a11c | 649 | |
a1916eb0 MZ |
650 | #ifdef CONFIG_APM_EMULATION |
651 | static void zeus_get_power_status(struct apm_power_info *info) | |
652 | { | |
653 | /* Power supply is always present */ | |
654 | info->ac_line_status = APM_AC_ONLINE; | |
655 | info->battery_status = APM_BATTERY_STATUS_NOT_PRESENT; | |
656 | info->battery_flag = APM_BATTERY_FLAG_NOT_PRESENT; | |
657 | } | |
658 | ||
659 | static inline void zeus_setup_apm(void) | |
660 | { | |
661 | apm_get_power_status = zeus_get_power_status; | |
662 | } | |
663 | #else | |
664 | static inline void zeus_setup_apm(void) | |
665 | { | |
666 | } | |
667 | #endif | |
668 | ||
100627b4 MZ |
669 | static int zeus_get_pcb_info(struct i2c_client *client, unsigned gpio, |
670 | unsigned ngpio, void *context) | |
e491a11c MZ |
671 | { |
672 | int i; | |
673 | u8 pcb_info = 0; | |
674 | ||
675 | for (i = 0; i < 8; i++) { | |
676 | int pcb_bit = gpio + i + 8; | |
677 | ||
678 | if (gpio_request(pcb_bit, "pcb info")) { | |
679 | dev_err(&client->dev, "Can't request pcb info %d\n", i); | |
680 | continue; | |
681 | } | |
682 | ||
683 | if (gpio_direction_input(pcb_bit)) { | |
684 | dev_err(&client->dev, "Can't read pcb info %d\n", i); | |
685 | gpio_free(pcb_bit); | |
686 | continue; | |
687 | } | |
688 | ||
689 | pcb_info |= !!gpio_get_value(pcb_bit) << i; | |
690 | ||
691 | gpio_free(pcb_bit); | |
692 | } | |
693 | ||
694 | dev_info(&client->dev, "Zeus PCB version %d issue %d\n", | |
695 | pcb_info >> 4, pcb_info & 0xf); | |
696 | ||
697 | return 0; | |
698 | } | |
699 | ||
700 | static struct pca953x_platform_data zeus_pca953x_pdata[] = { | |
701 | [0] = { .gpio_base = ZEUS_EXT0_GPIO_BASE, }, | |
702 | [1] = { | |
703 | .gpio_base = ZEUS_EXT1_GPIO_BASE, | |
704 | .setup = zeus_get_pcb_info, | |
705 | }, | |
706 | [2] = { .gpio_base = ZEUS_USER_GPIO_BASE, }, | |
707 | }; | |
708 | ||
709 | static struct i2c_board_info __initdata zeus_i2c_devices[] = { | |
710 | { | |
711 | I2C_BOARD_INFO("pca9535", 0x21), | |
712 | .platform_data = &zeus_pca953x_pdata[0], | |
713 | }, | |
714 | { | |
715 | I2C_BOARD_INFO("pca9535", 0x22), | |
716 | .platform_data = &zeus_pca953x_pdata[1], | |
717 | }, | |
718 | { | |
719 | I2C_BOARD_INFO("pca9535", 0x20), | |
720 | .platform_data = &zeus_pca953x_pdata[2], | |
721 | .irq = gpio_to_irq(ZEUS_EXTGPIO_GPIO), | |
722 | }, | |
723 | { I2C_BOARD_INFO("lm75a", 0x48) }, | |
724 | { I2C_BOARD_INFO("24c01", 0x50) }, | |
725 | { I2C_BOARD_INFO("isl1208", 0x6f) }, | |
726 | }; | |
727 | ||
728 | static mfp_cfg_t zeus_pin_config[] __initdata = { | |
c11b6a42 EM |
729 | /* AC97 */ |
730 | GPIO28_AC97_BITCLK, | |
731 | GPIO29_AC97_SDATA_IN_0, | |
732 | GPIO30_AC97_SDATA_OUT, | |
733 | GPIO31_AC97_SYNC, | |
734 | ||
e491a11c MZ |
735 | GPIO15_nCS_1, |
736 | GPIO78_nCS_2, | |
737 | GPIO80_nCS_4, | |
738 | GPIO33_nCS_5, | |
739 | ||
740 | GPIO22_GPIO, | |
741 | GPIO32_MMC_CLK, | |
742 | GPIO92_MMC_DAT_0, | |
743 | GPIO109_MMC_DAT_1, | |
744 | GPIO110_MMC_DAT_2, | |
745 | GPIO111_MMC_DAT_3, | |
746 | GPIO112_MMC_CMD, | |
747 | ||
748 | GPIO88_USBH1_PWR, | |
749 | GPIO89_USBH1_PEN, | |
750 | GPIO119_USBH2_PWR, | |
751 | GPIO120_USBH2_PEN, | |
752 | ||
753 | GPIO86_LCD_LDD_16, | |
754 | GPIO87_LCD_LDD_17, | |
755 | ||
756 | GPIO102_GPIO, | |
757 | GPIO104_CIF_DD_2, | |
758 | GPIO105_CIF_DD_1, | |
759 | ||
760 | GPIO48_nPOE, | |
761 | GPIO49_nPWE, | |
762 | GPIO50_nPIOR, | |
763 | GPIO51_nPIOW, | |
764 | GPIO85_nPCE_1, | |
765 | GPIO54_nPCE_2, | |
766 | GPIO79_PSKTSEL, | |
767 | GPIO55_nPREG, | |
768 | GPIO56_nPWAIT, | |
769 | GPIO57_nIOIS16, | |
770 | GPIO36_GPIO, /* CF CD */ | |
771 | GPIO97_GPIO, /* CF PWREN */ | |
772 | GPIO99_GPIO, /* CF RDY */ | |
773 | }; | |
774 | ||
5f86ceba MZ |
775 | /* |
776 | * DM9k MSCx settings: SRAM, 16 bits | |
777 | * 17 cycles delay first access | |
778 | * 5 cycles delay next access | |
779 | * 13 cycles recovery time | |
780 | * faster device | |
781 | */ | |
782 | #define DM9K_MSC_VALUE 0xe4c9 | |
783 | ||
e491a11c MZ |
784 | static void __init zeus_init(void) |
785 | { | |
5f86ceba | 786 | u16 dm9000_msc = DM9K_MSC_VALUE; |
e491a11c MZ |
787 | |
788 | system_rev = __raw_readw(ZEUS_CPLD_VERSION); | |
789 | pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f)); | |
790 | ||
791 | /* Fix timings for dm9000s (CS1/CS2)*/ | |
792 | MSC0 = (MSC0 & 0xffff) | (dm9000_msc << 16); | |
793 | MSC1 = (MSC1 & 0xffff0000) | dm9000_msc; | |
794 | ||
795 | pm_power_off = zeus_power_off; | |
a1916eb0 | 796 | zeus_setup_apm(); |
e491a11c MZ |
797 | |
798 | pxa2xx_mfp_config(ARRAY_AND_SIZE(zeus_pin_config)); | |
799 | ||
800 | platform_add_devices(zeus_devices, ARRAY_SIZE(zeus_devices)); | |
801 | ||
802 | pxa_set_ohci_info(&zeus_ohci_platform_data); | |
803 | ||
804 | if (zeus_setup_fb_gpios()) | |
805 | pr_err("Failed to setup fb gpios\n"); | |
806 | else | |
807 | set_pxa_fb_info(&zeus_fb_info); | |
808 | ||
809 | pxa_set_mci_info(&zeus_mci_platform_data); | |
810 | pxa_set_udc_info(&zeus_udc_info); | |
811 | pxa_set_ac97_info(&zeus_ac97_info); | |
812 | pxa_set_i2c_info(NULL); | |
813 | i2c_register_board_info(0, ARRAY_AND_SIZE(zeus_i2c_devices)); | |
814 | } | |
815 | ||
816 | static struct map_desc zeus_io_desc[] __initdata = { | |
817 | { | |
818 | .virtual = ZEUS_CPLD_VERSION, | |
819 | .pfn = __phys_to_pfn(ZEUS_CPLD_VERSION_PHYS), | |
820 | .length = 0x1000, | |
821 | .type = MT_DEVICE, | |
822 | }, | |
823 | { | |
824 | .virtual = ZEUS_CPLD_ISA_IRQ, | |
825 | .pfn = __phys_to_pfn(ZEUS_CPLD_ISA_IRQ_PHYS), | |
826 | .length = 0x1000, | |
827 | .type = MT_DEVICE, | |
828 | }, | |
829 | { | |
830 | .virtual = ZEUS_CPLD_CONTROL, | |
831 | .pfn = __phys_to_pfn(ZEUS_CPLD_CONTROL_PHYS), | |
832 | .length = 0x1000, | |
833 | .type = MT_DEVICE, | |
834 | }, | |
e491a11c MZ |
835 | { |
836 | .virtual = ZEUS_PC104IO, | |
837 | .pfn = __phys_to_pfn(ZEUS_PC104IO_PHYS), | |
838 | .length = 0x00800000, | |
839 | .type = MT_DEVICE, | |
840 | }, | |
841 | }; | |
842 | ||
843 | static void __init zeus_map_io(void) | |
844 | { | |
845 | pxa_map_io(); | |
846 | ||
847 | iotable_init(zeus_io_desc, ARRAY_SIZE(zeus_io_desc)); | |
848 | ||
849 | /* Clear PSPR to ensure a full restart on wake-up. */ | |
850 | PMCR = PSPR = 0; | |
851 | ||
852 | /* enable internal 32.768Khz oscillator (ignore OSCC_OOK) */ | |
853 | OSCC |= OSCC_OON; | |
854 | ||
855 | /* Some clock cycles later (from OSCC_ON), programme PCFR (OPDE...). | |
856 | * float chip selects and PCMCIA */ | |
857 | PCFR = PCFR_OPDE | PCFR_DC_EN | PCFR_FS | PCFR_FP; | |
858 | } | |
859 | ||
90ac0dfd | 860 | MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS") |
e491a11c MZ |
861 | /* Maintainer: Marc Zyngier <maz@misterjones.org> */ |
862 | .phys_io = 0x40000000, | |
863 | .io_pg_offst = ((io_p2v(0x40000000) >> 18) & 0xfffc), | |
864 | .boot_params = 0xa0000100, | |
865 | .map_io = zeus_map_io, | |
866 | .init_irq = zeus_init_irq, | |
867 | .timer = &pxa_timer, | |
868 | .init_machine = zeus_init, | |
869 | MACHINE_END | |
870 |