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e7c70825 | 1 | /* |
e7c70825 BB |
2 | * Copyright (C) 2008 ARM Limited |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program; if not, write to the Free Software | |
15 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
16 | * MA 02110-1301, USA. | |
17 | */ | |
18 | ||
19 | #ifndef __ASM_ARCH_BOARD_PBA8_H | |
20 | #define __ASM_ARCH_BOARD_PBA8_H | |
21 | ||
6d407a6e | 22 | #include "platform.h" |
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23 | |
24 | /* | |
25 | * Peripheral addresses | |
26 | */ | |
27 | #define REALVIEW_PBA8_UART0_BASE 0x10009000 /* UART 0 */ | |
28 | #define REALVIEW_PBA8_UART1_BASE 0x1000A000 /* UART 1 */ | |
29 | #define REALVIEW_PBA8_UART2_BASE 0x1000B000 /* UART 2 */ | |
30 | #define REALVIEW_PBA8_UART3_BASE 0x1000C000 /* UART 3 */ | |
31 | #define REALVIEW_PBA8_SSP_BASE 0x1000D000 /* Synchronous Serial Port */ | |
32 | #define REALVIEW_PBA8_WATCHDOG0_BASE 0x1000F000 /* Watchdog 0 */ | |
33 | #define REALVIEW_PBA8_WATCHDOG_BASE 0x10010000 /* watchdog interface */ | |
34 | #define REALVIEW_PBA8_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */ | |
35 | #define REALVIEW_PBA8_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */ | |
36 | #define REALVIEW_PBA8_GPIO0_BASE 0x10013000 /* GPIO port 0 */ | |
37 | #define REALVIEW_PBA8_RTC_BASE 0x10017000 /* Real Time Clock */ | |
38 | #define REALVIEW_PBA8_TIMER4_5_BASE 0x10018000 /* Timer 4/5 */ | |
39 | #define REALVIEW_PBA8_TIMER6_7_BASE 0x10019000 /* Timer 6/7 */ | |
40 | #define REALVIEW_PBA8_SCTL_BASE 0x1001A000 /* System Controller */ | |
41 | #define REALVIEW_PBA8_CLCD_BASE 0x10020000 /* CLCD */ | |
42 | #define REALVIEW_PBA8_ONB_SRAM_BASE 0x10060000 /* On-board SRAM */ | |
43 | #define REALVIEW_PBA8_DMC_BASE 0x100E0000 /* DMC configuration */ | |
44 | #define REALVIEW_PBA8_SMC_BASE 0x100E1000 /* SMC configuration */ | |
45 | #define REALVIEW_PBA8_CAN_BASE 0x100E2000 /* CAN bus */ | |
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46 | #define REALVIEW_PBA8_GIC_CPU_BASE 0x1E000000 /* Generic interrupt controller CPU interface */ |
47 | #define REALVIEW_PBA8_FLASH0_BASE 0x40000000 | |
48 | #define REALVIEW_PBA8_FLASH0_SIZE SZ_64M | |
49 | #define REALVIEW_PBA8_FLASH1_BASE 0x44000000 | |
50 | #define REALVIEW_PBA8_FLASH1_SIZE SZ_64M | |
51 | #define REALVIEW_PBA8_ETH_BASE 0x4E000000 /* Ethernet */ | |
52 | #define REALVIEW_PBA8_USB_BASE 0x4F000000 /* USB */ | |
53 | #define REALVIEW_PBA8_GIC_DIST_BASE 0x1E001000 /* Generic interrupt controller distributor */ | |
54 | #define REALVIEW_PBA8_LT_BASE 0xC0000000 /* Logic Tile expansion */ | |
55 | #define REALVIEW_PBA8_SDRAM6_BASE 0x70000000 /* SDRAM bank 6 256MB */ | |
56 | #define REALVIEW_PBA8_SDRAM7_BASE 0x80000000 /* SDRAM bank 7 256MB */ | |
57 | ||
58 | #define REALVIEW_PBA8_SYS_PLD_CTRL1 0x74 | |
59 | ||
60 | /* | |
61 | * PBA8 PCI regions | |
62 | */ | |
63 | #define REALVIEW_PBA8_PCI_BASE 0x90040000 /* PCI-X Unit base */ | |
64 | #define REALVIEW_PBA8_PCI_IO_BASE 0x90050000 /* IO Region on AHB */ | |
65 | #define REALVIEW_PBA8_PCI_MEM_BASE 0xA0000000 /* MEM Region on AHB */ | |
66 | ||
67 | #define REALVIEW_PBA8_PCI_BASE_SIZE 0x10000 /* 16 Kb */ | |
68 | #define REALVIEW_PBA8_PCI_IO_SIZE 0x1000 /* 4 Kb */ | |
69 | #define REALVIEW_PBA8_PCI_MEM_SIZE 0x20000000 /* 512 MB */ | |
70 | ||
e7c70825 | 71 | #endif /* __ASM_ARCH_BOARD_PBA8_H */ |