[deliverable/linux.git] / arch / arm / mach-realview / core.c

/*
 *  linux/arch/arm/mach-realview/core.c
 *
 *  Copyright (C) 1999 - 2003 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/sysdev.h>
#include <linux/interrupt.h>
#include <linux/amba/bus.h>
#include <linux/amba/clcd.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/io.h>

#include <asm/system.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/leds.h>
#include <asm/mach-types.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/icst307.h>

#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/mmc.h>

#include <asm/hardware/gic.h>

#include "core.h"
#include "clock.h"

#define REALVIEW_REFCOUNTER	(__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)

/* used by entry-macro.S and platsmp.c */
void __iomem *gic_cpu_base_addr;

/*
 * This is the RealView sched_clock implementation.  This has
 * a resolution of 41.7ns, and a maximum value of about 179s.
 */
unsigned long long sched_clock(void)
{
	unsigned long long v;

	v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
	do_div(v, 3);

	return v;
}


#define REALVIEW_FLASHCTRL    (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)

static int realview_flash_init(void)
{
	u32 val;

	val = __raw_readl(REALVIEW_FLASHCTRL);
	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	__raw_writel(val, REALVIEW_FLASHCTRL);

	return 0;
}

static void realview_flash_exit(void)
{
	u32 val;

	val = __raw_readl(REALVIEW_FLASHCTRL);
	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	__raw_writel(val, REALVIEW_FLASHCTRL);
}

static void realview_flash_set_vpp(int on)
{
	u32 val;

	val = __raw_readl(REALVIEW_FLASHCTRL);
	if (on)
		val |= REALVIEW_FLASHPROG_FLVPPEN;
	else
		val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	__raw_writel(val, REALVIEW_FLASHCTRL);
}

static struct flash_platform_data realview_flash_data = {
	.map_name		= "cfi_probe",
	.width			= 4,
	.init			= realview_flash_init,
	.exit			= realview_flash_exit,
	.set_vpp		= realview_flash_set_vpp,
};

struct platform_device realview_flash_device = {
	.name			= "armflash",
	.id			= 0,
	.dev			= {
		.platform_data	= &realview_flash_data,
	},
};

int realview_flash_register(struct resource *res, u32 num)
{
	realview_flash_device.resource = res;
	realview_flash_device.num_resources = num;
	return platform_device_register(&realview_flash_device);
}

static struct resource realview_i2c_resource = {
	.start		= REALVIEW_I2C_BASE,
	.end		= REALVIEW_I2C_BASE + SZ_4K - 1,
	.flags		= IORESOURCE_MEM,
};

struct platform_device realview_i2c_device = {
	.name		= "versatile-i2c",
	.id		= -1,
	.num_resources	= 1,
	.resource	= &realview_i2c_resource,
};

#define REALVIEW_SYSMCI	(__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)

static unsigned int realview_mmc_status(struct device *dev)
{
	struct amba_device *adev = container_of(dev, struct amba_device, dev);
	u32 mask;

	if (adev->res.start == REALVIEW_MMCI0_BASE)
		mask = 1;
	else
		mask = 2;

	return readl(REALVIEW_SYSMCI) & mask;
}

struct mmc_platform_data realview_mmc0_plat_data = {
	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
	.status		= realview_mmc_status,
};

struct mmc_platform_data realview_mmc1_plat_data = {
	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
	.status		= realview_mmc_status,
};

/*
 * Clock handling
 */
static const struct icst307_params realview_oscvco_params = {
	.ref		= 24000,
	.vco_max	= 200000,
	.vd_min		= 4 + 8,
	.vd_max		= 511 + 8,
	.rd_min		= 1 + 2,
	.rd_max		= 127 + 2,
};

static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
{
	void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
	void __iomem *sys_osc;
	u32 val;

	if (machine_is_realview_pb1176())
		sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
	else
		sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;

	val = readl(sys_osc) & ~0x7ffff;
	val |= vco.v | (vco.r << 9) | (vco.s << 16);

	writel(0xa05f, sys_lock);
	writel(val, sys_osc);
	writel(0, sys_lock);
}

struct clk realview_clcd_clk = {
	.name	= "CLCDCLK",
	.params	= &realview_oscvco_params,
	.setvco = realview_oscvco_set,
};

/*
 * CLCD support.
 */
#define SYS_CLCD_NLCDIOON	(1 << 2)
#define SYS_CLCD_VDDPOSSWITCH	(1 << 3)
#define SYS_CLCD_PWR3V5SWITCH	(1 << 4)
#define SYS_CLCD_ID_MASK	(0x1f << 8)
#define SYS_CLCD_ID_SANYO_3_8	(0x00 << 8)
#define SYS_CLCD_ID_UNKNOWN_8_4	(0x01 << 8)
#define SYS_CLCD_ID_EPSON_2_2	(0x02 << 8)
#define SYS_CLCD_ID_SANYO_2_5	(0x07 << 8)
#define SYS_CLCD_ID_VGA		(0x1f << 8)

static struct clcd_panel vga = {
	.mode		= {
		.name		= "VGA",
		.refresh	= 60,
		.xres		= 640,
		.yres		= 480,
		.pixclock	= 39721,
		.left_margin	= 40,
		.right_margin	= 24,
		.upper_margin	= 32,
		.lower_margin	= 11,
		.hsync_len	= 96,
		.vsync_len	= 2,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static struct clcd_panel xvga = {
	.mode		= {
		.name		= "XVGA",
		.refresh	= 60,
		.xres		= 1024,
		.yres		= 768,
		.pixclock	= 15748,
		.left_margin	= 152,
		.right_margin	= 48,
		.upper_margin	= 23,
		.lower_margin	= 3,
		.hsync_len	= 104,
		.vsync_len	= 4,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static struct clcd_panel sanyo_3_8_in = {
	.mode		= {
		.name		= "Sanyo QVGA",
		.refresh	= 116,
		.xres		= 320,
		.yres		= 240,
		.pixclock	= 100000,
		.left_margin	= 6,
		.right_margin	= 6,
		.upper_margin	= 5,
		.lower_margin	= 5,
		.hsync_len	= 6,
		.vsync_len	= 6,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static struct clcd_panel sanyo_2_5_in = {
	.mode		= {
		.name		= "Sanyo QVGA Portrait",
		.refresh	= 116,
		.xres		= 240,
		.yres		= 320,
		.pixclock	= 100000,
		.left_margin	= 20,
		.right_margin	= 10,
		.upper_margin	= 2,
		.lower_margin	= 2,
		.hsync_len	= 10,
		.vsync_len	= 2,
		.sync		= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_IVS | TIM2_IHS | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static struct clcd_panel epson_2_2_in = {
	.mode		= {
		.name		= "Epson QCIF",
		.refresh	= 390,
		.xres		= 176,
		.yres		= 220,
		.pixclock	= 62500,
		.left_margin	= 3,
		.right_margin	= 2,
		.upper_margin	= 1,
		.lower_margin	= 0,
		.hsync_len	= 3,
		.vsync_len	= 2,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

/*
 * Detect which LCD panel is connected, and return the appropriate
 * clcd_panel structure.  Note: we do not have any information on
 * the required timings for the 8.4in panel, so we presently assume
 * VGA timings.
 */
static struct clcd_panel *realview_clcd_panel(void)
{
	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	struct clcd_panel *vga_panel;
	struct clcd_panel *panel;
	u32 val;

	if (machine_is_realview_eb())
		vga_panel = &vga;
	else
		vga_panel = &xvga;

	val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
	if (val == SYS_CLCD_ID_SANYO_3_8)
		panel = &sanyo_3_8_in;
	else if (val == SYS_CLCD_ID_SANYO_2_5)
		panel = &sanyo_2_5_in;
	else if (val == SYS_CLCD_ID_EPSON_2_2)
		panel = &epson_2_2_in;
	else if (val == SYS_CLCD_ID_VGA)
		panel = vga_panel;
	else {
		printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
			val);
		panel = vga_panel;
	}

	return panel;
}

/*
 * Disable all display connectors on the interface module.
 */
static void realview_clcd_disable(struct clcd_fb *fb)
{
	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	u32 val;

	val = readl(sys_clcd);
	val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
	writel(val, sys_clcd);
}

/*
 * Enable the relevant connector on the interface module.
 */
static void realview_clcd_enable(struct clcd_fb *fb)
{
	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	u32 val;

	/*
	 * Enable the PSUs
	 */
	val = readl(sys_clcd);
	val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
	writel(val, sys_clcd);
}

static int realview_clcd_setup(struct clcd_fb *fb)
{
	unsigned long framesize;
	dma_addr_t dma;

	if (machine_is_realview_eb())
		/* VGA, 16bpp */
		framesize = 640 * 480 * 2;
	else
		/* XVGA, 16bpp */
		framesize = 1024 * 768 * 2;

	fb->panel		= realview_clcd_panel();

	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
						    &dma, GFP_KERNEL);
	if (!fb->fb.screen_base) {
		printk(KERN_ERR "CLCD: unable to map framebuffer\n");
		return -ENOMEM;
	}

	fb->fb.fix.smem_start	= dma;
	fb->fb.fix.smem_len	= framesize;

	return 0;
}

static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
{
	return dma_mmap_writecombine(&fb->dev->dev, vma,
				     fb->fb.screen_base,
				     fb->fb.fix.smem_start,
				     fb->fb.fix.smem_len);
}

static void realview_clcd_remove(struct clcd_fb *fb)
{
	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
			      fb->fb.screen_base, fb->fb.fix.smem_start);
}

struct clcd_board clcd_plat_data = {
	.name		= "RealView",
	.check		= clcdfb_check,
	.decode		= clcdfb_decode,
	.disable	= realview_clcd_disable,
	.enable		= realview_clcd_enable,
	.setup		= realview_clcd_setup,
	.mmap		= realview_clcd_mmap,
	.remove		= realview_clcd_remove,
};

#ifdef CONFIG_LEDS
#define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)

void realview_leds_event(led_event_t ledevt)
{
	unsigned long flags;
	u32 val;

	local_irq_save(flags);
	val = readl(VA_LEDS_BASE);

	switch (ledevt) {
	case led_idle_start:
		val = val & ~REALVIEW_SYS_LED0;
		break;

	case led_idle_end:
		val = val | REALVIEW_SYS_LED0;
		break;

	case led_timer:
		val = val ^ REALVIEW_SYS_LED1;
		break;

	case led_halted:
		val = 0;
		break;

	default:
		break;
	}

	writel(val, VA_LEDS_BASE);
	local_irq_restore(flags);
}
#endif	/* CONFIG_LEDS */

/*
 * Where is the timer (VA)?
 */
void __iomem *timer0_va_base;
void __iomem *timer1_va_base;
void __iomem *timer2_va_base;
void __iomem *timer3_va_base;

/*
 * How long is the timer interval?
 */
#define TIMER_INTERVAL	(TICKS_PER_uSEC * mSEC_10)
#if TIMER_INTERVAL >= 0x100000
#define TIMER_RELOAD	(TIMER_INTERVAL >> 8)
#define TIMER_DIVISOR	(TIMER_CTRL_DIV256)
#define TICKS2USECS(x)	(256 * (x) / TICKS_PER_uSEC)
#elif TIMER_INTERVAL >= 0x10000
#define TIMER_RELOAD	(TIMER_INTERVAL >> 4)		/* Divide by 16 */
#define TIMER_DIVISOR	(TIMER_CTRL_DIV16)
#define TICKS2USECS(x)	(16 * (x) / TICKS_PER_uSEC)
#else
#define TIMER_RELOAD	(TIMER_INTERVAL)
#define TIMER_DIVISOR	(TIMER_CTRL_DIV1)
#define TICKS2USECS(x)	((x) / TICKS_PER_uSEC)
#endif

static void timer_set_mode(enum clock_event_mode mode,
			   struct clock_event_device *clk)
{
	unsigned long ctrl;

	switch(mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD);

		ctrl = TIMER_CTRL_PERIODIC;
		ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		/* period set, and timer enabled in 'next_event' hook */
		ctrl = TIMER_CTRL_ONESHOT;
		ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	default:
		ctrl = 0;
	}

	writel(ctrl, timer0_va_base + TIMER_CTRL);
}

static int timer_set_next_event(unsigned long evt,
				struct clock_event_device *unused)
{
	unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL);

	writel(evt, timer0_va_base + TIMER_LOAD);
	writel(ctrl | TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL);

	return 0;
}

static struct clock_event_device timer0_clockevent =	 {
	.name		= "timer0",
	.shift		= 32,
	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_mode	= timer_set_mode,
	.set_next_event	= timer_set_next_event,
	.rating		= 300,
	.cpumask	= CPU_MASK_ALL,
};

static void __init realview_clockevents_init(unsigned int timer_irq)
{
	timer0_clockevent.irq = timer_irq;
	timer0_clockevent.mult =
		div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
	timer0_clockevent.max_delta_ns =
		clockevent_delta2ns(0xffffffff, &timer0_clockevent);
	timer0_clockevent.min_delta_ns =
		clockevent_delta2ns(0xf, &timer0_clockevent);

	clockevents_register_device(&timer0_clockevent);
}

/*
 * IRQ handler for the timer
 */
static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = &timer0_clockevent;

	/* clear the interrupt */
	writel(1, timer0_va_base + TIMER_INTCLR);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction realview_timer_irq = {
	.name		= "RealView Timer Tick",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= realview_timer_interrupt,
};

static cycle_t realview_get_cycles(void)
{
	return ~readl(timer3_va_base + TIMER_VALUE);
}

static struct clocksource clocksource_realview = {
	.name	= "timer3",
	.rating	= 200,
	.read	= realview_get_cycles,
	.mask	= CLOCKSOURCE_MASK(32),
	.shift	= 20,
	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
};

static void __init realview_clocksource_init(void)
{
	/* setup timer 0 as free-running clocksource */
	writel(0, timer3_va_base + TIMER_CTRL);
	writel(0xffffffff, timer3_va_base + TIMER_LOAD);
	writel(0xffffffff, timer3_va_base + TIMER_VALUE);
	writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
		timer3_va_base + TIMER_CTRL);

	clocksource_realview.mult =
		clocksource_khz2mult(1000, clocksource_realview.shift);
	clocksource_register(&clocksource_realview);
}

/*
 * Set up the clock source and clock events devices
 */
void __init realview_timer_init(unsigned int timer_irq)
{
	u32 val;

#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
	/*
	 * The dummy clock device has to be registered before the main device
	 * so that the latter will broadcast the clock events
	 */
	local_timer_setup();
#endif

	/* 
	 * set clock frequency: 
	 *	REALVIEW_REFCLK is 32KHz
	 *	REALVIEW_TIMCLK is 1MHz
	 */
	val = readl(__io_address(REALVIEW_SCTL_BASE));
	writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
	       (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) | 
	       (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
	       (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
	       __io_address(REALVIEW_SCTL_BASE));

	/*
	 * Initialise to a known state (all timers off)
	 */
	writel(0, timer0_va_base + TIMER_CTRL);
	writel(0, timer1_va_base + TIMER_CTRL);
	writel(0, timer2_va_base + TIMER_CTRL);
	writel(0, timer3_va_base + TIMER_CTRL);

	/* 
	 * Make irqs happen for the system timer
	 */
	setup_irq(timer_irq, &realview_timer_irq);

	realview_clocksource_init();
	realview_clockevents_init(timer_irq);
}
Commit	Line	Data
8ad68bbf CM	1	/*
	2	* linux/arch/arm/mach-realview/core.c
	3	*
	4	* Copyright (C) 1999 - 2003 ARM Limited
	5	* Copyright (C) 2000 Deep Blue Solutions Ltd
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
8ad68bbf	21	#include <linux/init.h>
1be7228d	22	#include <linux/platform_device.h>
8ad68bbf CM	23	#include <linux/dma-mapping.h>
	24	#include <linux/sysdev.h>
	25	#include <linux/interrupt.h>
a62c80e5 RK	26	#include <linux/amba/bus.h>
a62c80e5 RK	27	#include <linux/amba/clcd.h>
85802afe	28	#include <linux/clocksource.h>
ae30ceac	29	#include <linux/clockchips.h>
fced80c7	30	#include <linux/io.h>
8ad68bbf CM	31
8ad68bbf CM	32	#include <asm/system.h>
a09e64fb	33	#include <mach/hardware.h>
8ad68bbf CM	34	#include <asm/irq.h>
8ad68bbf CM	35	#include <asm/leds.h>
68c3d935	36	#include <asm/mach-types.h>
8ad68bbf CM	37	#include <asm/hardware/arm_timer.h>
	38	#include <asm/hardware/icst307.h>
	39
	40	#include <asm/mach/arch.h>
	41	#include <asm/mach/flash.h>
	42	#include <asm/mach/irq.h>
8ad68bbf CM	43	#include <asm/mach/map.h>
	44	#include <asm/mach/mmc.h>
	45
	46	#include <asm/hardware/gic.h>
	47
	48	#include "core.h"
	49	#include "clock.h"
	50
	51	#define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
	52
1bbdf637	53	/* used by entry-macro.S and platsmp.c */
c4057f52 CM	54	void __iomem *gic_cpu_base_addr;
c4057f52 CM	55
8ad68bbf CM	56	/*
	57	* This is the RealView sched_clock implementation. This has
	58	* a resolution of 41.7ns, and a maximum value of about 179s.
	59	*/
	60	unsigned long long sched_clock(void)
	61	{
	62	unsigned long long v;
	63
	64	v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
	65	do_div(v, 3);
	66
	67	return v;
	68	}
	69
	70
	71	#define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
	72
	73	static int realview_flash_init(void)
	74	{
	75	u32 val;
	76
	77	val = __raw_readl(REALVIEW_FLASHCTRL);
	78	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	79	__raw_writel(val, REALVIEW_FLASHCTRL);
	80
	81	return 0;
	82	}
	83
	84	static void realview_flash_exit(void)
	85	{
	86	u32 val;
	87
	88	val = __raw_readl(REALVIEW_FLASHCTRL);
	89	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	90	__raw_writel(val, REALVIEW_FLASHCTRL);
	91	}
	92
	93	static void realview_flash_set_vpp(int on)
	94	{
	95	u32 val;
	96
	97	val = __raw_readl(REALVIEW_FLASHCTRL);
	98	if (on)
	99	val \|= REALVIEW_FLASHPROG_FLVPPEN;
	100	else
	101	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	102	__raw_writel(val, REALVIEW_FLASHCTRL);
	103	}
	104
	105	static struct flash_platform_data realview_flash_data = {
	106	.map_name = "cfi_probe",
	107	.width = 4,
	108	.init = realview_flash_init,
	109	.exit = realview_flash_exit,
	110	.set_vpp = realview_flash_set_vpp,
	111	};
	112
8ad68bbf CM	113	struct platform_device realview_flash_device = {
	114	.name = "armflash",
	115	.id = 0,
	116	.dev = {
	117	.platform_data = &realview_flash_data,
	118	},
8ad68bbf CM	119	};
8ad68bbf CM	120
a44ddfd5 CM	121	int realview_flash_register(struct resource *res, u32 num)
	122	{
	123	realview_flash_device.resource = res;
	124	realview_flash_device.num_resources = num;
	125	return platform_device_register(&realview_flash_device);
	126	}
	127
6b65cd74 RK	128	static struct resource realview_i2c_resource = {
	129	.start = REALVIEW_I2C_BASE,
	130	.end = REALVIEW_I2C_BASE + SZ_4K - 1,
	131	.flags = IORESOURCE_MEM,
	132	};
	133
	134	struct platform_device realview_i2c_device = {
	135	.name = "versatile-i2c",
	136	.id = -1,
	137	.num_resources = 1,
	138	.resource = &realview_i2c_resource,
	139	};
	140
8ad68bbf CM	141	#define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
	142
	143	static unsigned int realview_mmc_status(struct device *dev)
	144	{
	145	struct amba_device *adev = container_of(dev, struct amba_device, dev);
	146	u32 mask;
	147
	148	if (adev->res.start == REALVIEW_MMCI0_BASE)
	149	mask = 1;
	150	else
	151	mask = 2;
	152
	153	return readl(REALVIEW_SYSMCI) & mask;
	154	}
	155
	156	struct mmc_platform_data realview_mmc0_plat_data = {
	157	.ocr_mask = MMC_VDD_32_33\|MMC_VDD_33_34,
	158	.status = realview_mmc_status,
	159	};
	160
	161	struct mmc_platform_data realview_mmc1_plat_data = {
	162	.ocr_mask = MMC_VDD_32_33\|MMC_VDD_33_34,
	163	.status = realview_mmc_status,
	164	};
	165
	166	/*
	167	* Clock handling
	168	*/
	169	static const struct icst307_params realview_oscvco_params = {
	170	.ref = 24000,
	171	.vco_max = 200000,
	172	.vd_min = 4 + 8,
	173	.vd_max = 511 + 8,
	174	.rd_min = 1 + 2,
	175	.rd_max = 127 + 2,
	176	};
	177
	178	static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
	179	{
	180	void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
68c3d935	181	void __iomem *sys_osc;
8ad68bbf CM	182	u32 val;
8ad68bbf CM	183
68c3d935 CT	184	if (machine_is_realview_pb1176())
	185	sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
	186	else
	187	sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
	188
8ad68bbf CM	189	val = readl(sys_osc) & ~0x7ffff;
	190	val \|= vco.v \| (vco.r << 9) \| (vco.s << 16);
	191
	192	writel(0xa05f, sys_lock);
	193	writel(val, sys_osc);
	194	writel(0, sys_lock);
	195	}
	196
	197	struct clk realview_clcd_clk = {
	198	.name = "CLCDCLK",
	199	.params = &realview_oscvco_params,
	200	.setvco = realview_oscvco_set,
	201	};
	202
	203	/*
	204	* CLCD support.
	205	*/
8ad68bbf CM	206	#define SYS_CLCD_NLCDIOON (1 << 2)
	207	#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
	208	#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
	209	#define SYS_CLCD_ID_MASK (0x1f << 8)
	210	#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
	211	#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
	212	#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
	213	#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
	214	#define SYS_CLCD_ID_VGA (0x1f << 8)
	215
	216	static struct clcd_panel vga = {
	217	.mode = {
	218	.name = "VGA",
	219	.refresh = 60,
	220	.xres = 640,
	221	.yres = 480,
	222	.pixclock = 39721,
	223	.left_margin = 40,
	224	.right_margin = 24,
	225	.upper_margin = 32,
	226	.lower_margin = 11,
	227	.hsync_len = 96,
	228	.vsync_len = 2,
	229	.sync = 0,
	230	.vmode = FB_VMODE_NONINTERLACED,
	231	},
	232	.width = -1,
	233	.height = -1,
	234	.tim2 = TIM2_BCD \| TIM2_IPC,
4eccca20	235	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
8ad68bbf CM	236	.bpp = 16,
	237	};
	238
c34a1025 CT	239	static struct clcd_panel xvga = {
	240	.mode = {
	241	.name = "XVGA",
	242	.refresh = 60,
	243	.xres = 1024,
	244	.yres = 768,
	245	.pixclock = 15748,
	246	.left_margin = 152,
	247	.right_margin = 48,
	248	.upper_margin = 23,
	249	.lower_margin = 3,
	250	.hsync_len = 104,
	251	.vsync_len = 4,
	252	.sync = 0,
	253	.vmode = FB_VMODE_NONINTERLACED,
	254	},
	255	.width = -1,
	256	.height = -1,
	257	.tim2 = TIM2_BCD \| TIM2_IPC,
4eccca20	258	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
c34a1025 CT	259	.bpp = 16,
	260	};
	261
8ad68bbf CM	262	static struct clcd_panel sanyo_3_8_in = {
	263	.mode = {
	264	.name = "Sanyo QVGA",
	265	.refresh = 116,
	266	.xres = 320,
	267	.yres = 240,
	268	.pixclock = 100000,
	269	.left_margin = 6,
	270	.right_margin = 6,
	271	.upper_margin = 5,
	272	.lower_margin = 5,
	273	.hsync_len = 6,
	274	.vsync_len = 6,
	275	.sync = 0,
	276	.vmode = FB_VMODE_NONINTERLACED,
	277	},
	278	.width = -1,
	279	.height = -1,
	280	.tim2 = TIM2_BCD,
4eccca20	281	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
8ad68bbf CM	282	.bpp = 16,
	283	};
	284
	285	static struct clcd_panel sanyo_2_5_in = {
	286	.mode = {
	287	.name = "Sanyo QVGA Portrait",
	288	.refresh = 116,
	289	.xres = 240,
	290	.yres = 320,
	291	.pixclock = 100000,
	292	.left_margin = 20,
	293	.right_margin = 10,
	294	.upper_margin = 2,
	295	.lower_margin = 2,
	296	.hsync_len = 10,
	297	.vsync_len = 2,
	298	.sync = FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	299	.vmode = FB_VMODE_NONINTERLACED,
	300	},
	301	.width = -1,
	302	.height = -1,
	303	.tim2 = TIM2_IVS \| TIM2_IHS \| TIM2_IPC,
4eccca20	304	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
8ad68bbf CM	305	.bpp = 16,
	306	};
	307
	308	static struct clcd_panel epson_2_2_in = {
	309	.mode = {
	310	.name = "Epson QCIF",
	311	.refresh = 390,
	312	.xres = 176,
	313	.yres = 220,
	314	.pixclock = 62500,
	315	.left_margin = 3,
	316	.right_margin = 2,
	317	.upper_margin = 1,
	318	.lower_margin = 0,
	319	.hsync_len = 3,
	320	.vsync_len = 2,
	321	.sync = 0,
	322	.vmode = FB_VMODE_NONINTERLACED,
	323	},
	324	.width = -1,
	325	.height = -1,
	326	.tim2 = TIM2_BCD \| TIM2_IPC,
4eccca20	327	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
8ad68bbf CM	328	.bpp = 16,
	329	};
	330
	331	/*
	332	* Detect which LCD panel is connected, and return the appropriate
	333	* clcd_panel structure. Note: we do not have any information on
	334	* the required timings for the 8.4in panel, so we presently assume
	335	* VGA timings.
	336	*/
	337	static struct clcd_panel *realview_clcd_panel(void)
	338	{
	339	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
c34a1025 CT	340	struct clcd_panel *vga_panel;
c34a1025 CT	341	struct clcd_panel *panel;
8ad68bbf CM	342	u32 val;
8ad68bbf CM	343
c34a1025 CT	344	if (machine_is_realview_eb())
	345	vga_panel = &vga;
	346	else
	347	vga_panel = &xvga;
	348
8ad68bbf CM	349	val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
	350	if (val == SYS_CLCD_ID_SANYO_3_8)
	351	panel = &sanyo_3_8_in;
	352	else if (val == SYS_CLCD_ID_SANYO_2_5)
	353	panel = &sanyo_2_5_in;
	354	else if (val == SYS_CLCD_ID_EPSON_2_2)
	355	panel = &epson_2_2_in;
	356	else if (val == SYS_CLCD_ID_VGA)
c34a1025	357	panel = vga_panel;
8ad68bbf CM	358	else {
	359	printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
	360	val);
c34a1025	361	panel = vga_panel;
8ad68bbf CM	362	}
	363
	364	return panel;
	365	}
	366
	367	/*
	368	* Disable all display connectors on the interface module.
	369	*/
	370	static void realview_clcd_disable(struct clcd_fb *fb)
	371	{
	372	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	373	u32 val;
	374
	375	val = readl(sys_clcd);
	376	val &= ~SYS_CLCD_NLCDIOON \| SYS_CLCD_PWR3V5SWITCH;
	377	writel(val, sys_clcd);
	378	}
	379
	380	/*
	381	* Enable the relevant connector on the interface module.
	382	*/
	383	static void realview_clcd_enable(struct clcd_fb *fb)
	384	{
	385	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	386	u32 val;
	387
8ad68bbf	388	/*
9e7714d0	389	* Enable the PSUs
8ad68bbf	390	*/
9e7714d0	391	val = readl(sys_clcd);
8ad68bbf CM	392	val \|= SYS_CLCD_NLCDIOON \| SYS_CLCD_PWR3V5SWITCH;
	393	writel(val, sys_clcd);
	394	}
	395
8ad68bbf CM	396	static int realview_clcd_setup(struct clcd_fb *fb)
8ad68bbf CM	397	{
c34a1025	398	unsigned long framesize;
8ad68bbf CM	399	dma_addr_t dma;
8ad68bbf CM	400
c34a1025 CT	401	if (machine_is_realview_eb())
	402	/* VGA, 16bpp */
	403	framesize = 640 * 480 * 2;
	404	else
	405	/* XVGA, 16bpp */
	406	framesize = 1024 * 768 * 2;
	407
8ad68bbf CM	408	fb->panel = realview_clcd_panel();
	409
	410	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
	411	&dma, GFP_KERNEL);
	412	if (!fb->fb.screen_base) {
	413	printk(KERN_ERR "CLCD: unable to map framebuffer\n");
	414	return -ENOMEM;
	415	}
	416
	417	fb->fb.fix.smem_start = dma;
	418	fb->fb.fix.smem_len = framesize;
	419
	420	return 0;
	421	}
	422
	423	static int realview_clcd_mmap(struct clcd_fb fb, struct vm_area_struct vma)
	424	{
	425	return dma_mmap_writecombine(&fb->dev->dev, vma,
	426	fb->fb.screen_base,
	427	fb->fb.fix.smem_start,
	428	fb->fb.fix.smem_len);
	429	}
	430
	431	static void realview_clcd_remove(struct clcd_fb *fb)
	432	{
	433	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
	434	fb->fb.screen_base, fb->fb.fix.smem_start);
	435	}
	436
	437	struct clcd_board clcd_plat_data = {
	438	.name = "RealView",
	439	.check = clcdfb_check,
	440	.decode = clcdfb_decode,
	441	.disable = realview_clcd_disable,
	442	.enable = realview_clcd_enable,
	443	.setup = realview_clcd_setup,
	444	.mmap = realview_clcd_mmap,
	445	.remove = realview_clcd_remove,
	446	};
	447
	448	#ifdef CONFIG_LEDS
	449	#define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
	450
	451	void realview_leds_event(led_event_t ledevt)
	452	{
	453	unsigned long flags;
	454	u32 val;
	455
	456	local_irq_save(flags);
	457	val = readl(VA_LEDS_BASE);
	458
	459	switch (ledevt) {
	460	case led_idle_start:
	461	val = val & ~REALVIEW_SYS_LED0;
	462	break;
	463
	464	case led_idle_end:
	465	val = val \| REALVIEW_SYS_LED0;
	466	break;
	467
	468	case led_timer:
	469	val = val ^ REALVIEW_SYS_LED1;
	470	break;
	471
472	case led_halted:
473	val = 0;
474	break;
475
476	default:
477	break;
478	}
479
480	writel(val, VA_LEDS_BASE);
481	local_irq_restore(flags);
482	}
483	#endif /* CONFIG_LEDS */
484
485	/*
486	* Where is the timer (VA)?
487	*/
80192735 CM	488	void __iomem *timer0_va_base;
	489	void __iomem *timer1_va_base;
	490	void __iomem *timer2_va_base;
	491	void __iomem *timer3_va_base;
8ad68bbf CM	492
	493	/*
	494	* How long is the timer interval?
	495	*/
	496	#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
	497	#if TIMER_INTERVAL >= 0x100000
	498	#define TIMER_RELOAD (TIMER_INTERVAL >> 8)
	499	#define TIMER_DIVISOR (TIMER_CTRL_DIV256)
	500	#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
	501	#elif TIMER_INTERVAL >= 0x10000
	502	#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
	503	#define TIMER_DIVISOR (TIMER_CTRL_DIV16)
	504	#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
	505	#else
	506	#define TIMER_RELOAD (TIMER_INTERVAL)
	507	#define TIMER_DIVISOR (TIMER_CTRL_DIV1)
	508	#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
	509	#endif
	510
ae30ceac CM	511	static void timer_set_mode(enum clock_event_mode mode,
	512	struct clock_event_device *clk)
	513	{
	514	unsigned long ctrl;
	515
	516	switch(mode) {
	517	case CLOCK_EVT_MODE_PERIODIC:
80192735	518	writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD);
ae30ceac CM	519
	520	ctrl = TIMER_CTRL_PERIODIC;
	521	ctrl \|= TIMER_CTRL_32BIT \| TIMER_CTRL_IE \| TIMER_CTRL_ENABLE;
	522	break;
	523	case CLOCK_EVT_MODE_ONESHOT:
	524	/* period set, and timer enabled in 'next_event' hook */
	525	ctrl = TIMER_CTRL_ONESHOT;
	526	ctrl \|= TIMER_CTRL_32BIT \| TIMER_CTRL_IE;
	527	break;
	528	case CLOCK_EVT_MODE_UNUSED:
	529	case CLOCK_EVT_MODE_SHUTDOWN:
	530	default:
	531	ctrl = 0;
	532	}
	533
80192735	534	writel(ctrl, timer0_va_base + TIMER_CTRL);
ae30ceac CM	535	}
	536
	537	static int timer_set_next_event(unsigned long evt,
	538	struct clock_event_device *unused)
	539	{
80192735	540	unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL);
ae30ceac	541
80192735 CM	542	writel(evt, timer0_va_base + TIMER_LOAD);
80192735 CM	543	writel(ctrl \| TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL);
ae30ceac CM	544
	545	return 0;
	546	}
	547
	548	static struct clock_event_device timer0_clockevent = {
	549	.name = "timer0",
	550	.shift = 32,
	551	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	552	.set_mode = timer_set_mode,
	553	.set_next_event = timer_set_next_event,
	554	.rating = 300,
ae30ceac CM	555	.cpumask = CPU_MASK_ALL,
	556	};
	557
8cc4c548	558	static void __init realview_clockevents_init(unsigned int timer_irq)
ae30ceac	559	{
8cc4c548	560	timer0_clockevent.irq = timer_irq;
ae30ceac CM	561	timer0_clockevent.mult =
	562	div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
	563	timer0_clockevent.max_delta_ns =
	564	clockevent_delta2ns(0xffffffff, &timer0_clockevent);
	565	timer0_clockevent.min_delta_ns =
	566	clockevent_delta2ns(0xf, &timer0_clockevent);
	567
	568	clockevents_register_device(&timer0_clockevent);
	569	}
	570
8ad68bbf CM	571	/*
	572	* IRQ handler for the timer
	573	*/
0cd61b68	574	static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
8ad68bbf	575	{
ae30ceac	576	struct clock_event_device *evt = &timer0_clockevent;
8ad68bbf	577
ae30ceac	578	/* clear the interrupt */
80192735	579	writel(1, timer0_va_base + TIMER_INTCLR);
8ad68bbf	580
ae30ceac	581	evt->event_handler(evt);
dbebb4cb	582
8ad68bbf CM	583	return IRQ_HANDLED;
	584	}
	585
	586	static struct irqaction realview_timer_irq = {
	587	.name = "RealView Timer Tick",
b30fabad	588	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
8ad68bbf CM	589	.handler = realview_timer_interrupt,
	590	};
	591
85802afe CM	592	static cycle_t realview_get_cycles(void)
85802afe CM	593	{
80192735	594	return ~readl(timer3_va_base + TIMER_VALUE);
85802afe CM	595	}
	596
	597	static struct clocksource clocksource_realview = {
	598	.name = "timer3",
	599	.rating = 200,
	600	.read = realview_get_cycles,
	601	.mask = CLOCKSOURCE_MASK(32),
	602	.shift = 20,
	603	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	604	};
	605
	606	static void __init realview_clocksource_init(void)
	607	{
	608	/* setup timer 0 as free-running clocksource */
80192735 CM	609	writel(0, timer3_va_base + TIMER_CTRL);
	610	writel(0xffffffff, timer3_va_base + TIMER_LOAD);
	611	writel(0xffffffff, timer3_va_base + TIMER_VALUE);
85802afe	612	writel(TIMER_CTRL_32BIT \| TIMER_CTRL_ENABLE \| TIMER_CTRL_PERIODIC,
80192735	613	timer3_va_base + TIMER_CTRL);
85802afe CM	614
	615	clocksource_realview.mult =
	616	clocksource_khz2mult(1000, clocksource_realview.shift);
	617	clocksource_register(&clocksource_realview);
	618	}
	619
8ad68bbf	620	/*
a8655e83	621	* Set up the clock source and clock events devices
8ad68bbf	622	*/
8cc4c548	623	void __init realview_timer_init(unsigned int timer_irq)
8ad68bbf CM	624	{
	625	u32 val;
	626
a8655e83 CM	627	#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
	628	/*
	629	* The dummy clock device has to be registered before the main device
	630	* so that the latter will broadcast the clock events
	631	*/
ebac6546	632	local_timer_setup();
a8655e83 CM	633	#endif
a8655e83 CM	634
8ad68bbf CM	635	/*
	636	* set clock frequency:
	637	* REALVIEW_REFCLK is 32KHz
	638	* REALVIEW_TIMCLK is 1MHz
	639	*/
	640	val = readl(__io_address(REALVIEW_SCTL_BASE));
	641	writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) \|
	642	(REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) \|
	643	(REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) \|
	644	(REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) \| val,
	645	__io_address(REALVIEW_SCTL_BASE));
	646
	647	/*
	648	* Initialise to a known state (all timers off)
	649	*/
80192735 CM	650	writel(0, timer0_va_base + TIMER_CTRL);
	651	writel(0, timer1_va_base + TIMER_CTRL);
	652	writel(0, timer2_va_base + TIMER_CTRL);
	653	writel(0, timer3_va_base + TIMER_CTRL);
8ad68bbf	654
8ad68bbf CM	655	/*
	656	* Make irqs happen for the system timer
	657	*/
8cc4c548	658	setup_irq(timer_irq, &realview_timer_irq);
85802afe CM	659
85802afe CM	660	realview_clocksource_init();
8cc4c548	661	realview_clockevents_init(timer_irq);
8ad68bbf	662	}