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8ad68bbf CM |
1 | /* |
2 | * linux/arch/arm/mach-realview/core.c | |
3 | * | |
4 | * Copyright (C) 1999 - 2003 ARM Limited | |
5 | * Copyright (C) 2000 Deep Blue Solutions Ltd | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
8ad68bbf | 21 | #include <linux/init.h> |
1be7228d | 22 | #include <linux/platform_device.h> |
8ad68bbf CM |
23 | #include <linux/dma-mapping.h> |
24 | #include <linux/sysdev.h> | |
25 | #include <linux/interrupt.h> | |
a62c80e5 RK |
26 | #include <linux/amba/bus.h> |
27 | #include <linux/amba/clcd.h> | |
85802afe | 28 | #include <linux/clocksource.h> |
ae30ceac | 29 | #include <linux/clockchips.h> |
fced80c7 | 30 | #include <linux/io.h> |
0a5b2f6b | 31 | #include <linux/smc911x.h> |
6be62ba2 | 32 | #include <linux/ata_platform.h> |
8ad68bbf | 33 | |
cf30fb4a | 34 | #include <asm/clkdev.h> |
8ad68bbf | 35 | #include <asm/system.h> |
a09e64fb | 36 | #include <mach/hardware.h> |
8ad68bbf CM |
37 | #include <asm/irq.h> |
38 | #include <asm/leds.h> | |
68c3d935 | 39 | #include <asm/mach-types.h> |
8ad68bbf CM |
40 | #include <asm/hardware/arm_timer.h> |
41 | #include <asm/hardware/icst307.h> | |
42 | ||
43 | #include <asm/mach/arch.h> | |
44 | #include <asm/mach/flash.h> | |
45 | #include <asm/mach/irq.h> | |
8ad68bbf CM |
46 | #include <asm/mach/map.h> |
47 | #include <asm/mach/mmc.h> | |
48 | ||
49 | #include <asm/hardware/gic.h> | |
50 | ||
51 | #include "core.h" | |
52 | #include "clock.h" | |
53 | ||
54 | #define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET) | |
55 | ||
1bbdf637 | 56 | /* used by entry-macro.S and platsmp.c */ |
c4057f52 CM |
57 | void __iomem *gic_cpu_base_addr; |
58 | ||
8ad68bbf CM |
59 | /* |
60 | * This is the RealView sched_clock implementation. This has | |
61 | * a resolution of 41.7ns, and a maximum value of about 179s. | |
62 | */ | |
63 | unsigned long long sched_clock(void) | |
64 | { | |
65 | unsigned long long v; | |
66 | ||
67 | v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125; | |
68 | do_div(v, 3); | |
69 | ||
70 | return v; | |
71 | } | |
72 | ||
73 | ||
74 | #define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET) | |
75 | ||
76 | static int realview_flash_init(void) | |
77 | { | |
78 | u32 val; | |
79 | ||
80 | val = __raw_readl(REALVIEW_FLASHCTRL); | |
81 | val &= ~REALVIEW_FLASHPROG_FLVPPEN; | |
82 | __raw_writel(val, REALVIEW_FLASHCTRL); | |
83 | ||
84 | return 0; | |
85 | } | |
86 | ||
87 | static void realview_flash_exit(void) | |
88 | { | |
89 | u32 val; | |
90 | ||
91 | val = __raw_readl(REALVIEW_FLASHCTRL); | |
92 | val &= ~REALVIEW_FLASHPROG_FLVPPEN; | |
93 | __raw_writel(val, REALVIEW_FLASHCTRL); | |
94 | } | |
95 | ||
96 | static void realview_flash_set_vpp(int on) | |
97 | { | |
98 | u32 val; | |
99 | ||
100 | val = __raw_readl(REALVIEW_FLASHCTRL); | |
101 | if (on) | |
102 | val |= REALVIEW_FLASHPROG_FLVPPEN; | |
103 | else | |
104 | val &= ~REALVIEW_FLASHPROG_FLVPPEN; | |
105 | __raw_writel(val, REALVIEW_FLASHCTRL); | |
106 | } | |
107 | ||
108 | static struct flash_platform_data realview_flash_data = { | |
109 | .map_name = "cfi_probe", | |
110 | .width = 4, | |
111 | .init = realview_flash_init, | |
112 | .exit = realview_flash_exit, | |
113 | .set_vpp = realview_flash_set_vpp, | |
114 | }; | |
115 | ||
8ad68bbf CM |
116 | struct platform_device realview_flash_device = { |
117 | .name = "armflash", | |
118 | .id = 0, | |
119 | .dev = { | |
120 | .platform_data = &realview_flash_data, | |
121 | }, | |
8ad68bbf CM |
122 | }; |
123 | ||
a44ddfd5 CM |
124 | int realview_flash_register(struct resource *res, u32 num) |
125 | { | |
126 | realview_flash_device.resource = res; | |
127 | realview_flash_device.num_resources = num; | |
128 | return platform_device_register(&realview_flash_device); | |
129 | } | |
130 | ||
0a5b2f6b CM |
131 | static struct smc911x_platdata realview_smc911x_platdata = { |
132 | .flags = SMC911X_USE_32BIT, | |
133 | .irq_flags = IRQF_SHARED, | |
134 | .irq_polarity = 1, | |
135 | }; | |
136 | ||
0a381330 CM |
137 | static struct platform_device realview_eth_device = { |
138 | .name = "smc911x", | |
139 | .id = 0, | |
140 | .num_resources = 2, | |
141 | }; | |
142 | ||
143 | int realview_eth_register(const char *name, struct resource *res) | |
144 | { | |
145 | if (name) | |
146 | realview_eth_device.name = name; | |
147 | realview_eth_device.resource = res; | |
0a5b2f6b CM |
148 | if (strcmp(realview_eth_device.name, "smc911x") == 0) |
149 | realview_eth_device.dev.platform_data = &realview_smc911x_platdata; | |
0a381330 CM |
150 | |
151 | return platform_device_register(&realview_eth_device); | |
7db21712 CM |
152 | } |
153 | ||
154 | struct platform_device realview_usb_device = { | |
155 | .name = "isp1760", | |
156 | .num_resources = 2, | |
157 | }; | |
158 | ||
159 | int realview_usb_register(struct resource *res) | |
160 | { | |
161 | realview_usb_device.resource = res; | |
162 | return platform_device_register(&realview_usb_device); | |
0a381330 CM |
163 | } |
164 | ||
6be62ba2 CM |
165 | static struct pata_platform_info pata_platform_data = { |
166 | .ioport_shift = 1, | |
167 | }; | |
168 | ||
169 | static struct resource pata_resources[] = { | |
170 | [0] = { | |
171 | .start = REALVIEW_CF_BASE, | |
172 | .end = REALVIEW_CF_BASE + 0xff, | |
173 | .flags = IORESOURCE_MEM, | |
174 | }, | |
175 | [1] = { | |
176 | .start = REALVIEW_CF_BASE + 0x100, | |
177 | .end = REALVIEW_CF_BASE + SZ_4K - 1, | |
178 | .flags = IORESOURCE_MEM, | |
179 | }, | |
180 | }; | |
181 | ||
182 | struct platform_device realview_cf_device = { | |
183 | .name = "pata_platform", | |
184 | .id = -1, | |
185 | .num_resources = ARRAY_SIZE(pata_resources), | |
186 | .resource = pata_resources, | |
187 | .dev = { | |
188 | .platform_data = &pata_platform_data, | |
189 | }, | |
190 | }; | |
191 | ||
6b65cd74 RK |
192 | static struct resource realview_i2c_resource = { |
193 | .start = REALVIEW_I2C_BASE, | |
194 | .end = REALVIEW_I2C_BASE + SZ_4K - 1, | |
195 | .flags = IORESOURCE_MEM, | |
196 | }; | |
197 | ||
198 | struct platform_device realview_i2c_device = { | |
199 | .name = "versatile-i2c", | |
533ad5e6 | 200 | .id = 0, |
6b65cd74 RK |
201 | .num_resources = 1, |
202 | .resource = &realview_i2c_resource, | |
203 | }; | |
204 | ||
533ad5e6 CM |
205 | static struct i2c_board_info realview_i2c_board_info[] = { |
206 | { | |
207 | I2C_BOARD_INFO("rtc-ds1307", 0xd0 >> 1), | |
208 | .type = "ds1338", | |
209 | }, | |
210 | }; | |
211 | ||
212 | static int __init realview_i2c_init(void) | |
213 | { | |
214 | return i2c_register_board_info(0, realview_i2c_board_info, | |
215 | ARRAY_SIZE(realview_i2c_board_info)); | |
216 | } | |
217 | arch_initcall(realview_i2c_init); | |
218 | ||
8ad68bbf CM |
219 | #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET) |
220 | ||
221 | static unsigned int realview_mmc_status(struct device *dev) | |
222 | { | |
223 | struct amba_device *adev = container_of(dev, struct amba_device, dev); | |
224 | u32 mask; | |
225 | ||
226 | if (adev->res.start == REALVIEW_MMCI0_BASE) | |
227 | mask = 1; | |
228 | else | |
229 | mask = 2; | |
230 | ||
231 | return readl(REALVIEW_SYSMCI) & mask; | |
232 | } | |
233 | ||
234 | struct mmc_platform_data realview_mmc0_plat_data = { | |
235 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, | |
236 | .status = realview_mmc_status, | |
237 | }; | |
238 | ||
239 | struct mmc_platform_data realview_mmc1_plat_data = { | |
240 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, | |
241 | .status = realview_mmc_status, | |
242 | }; | |
243 | ||
244 | /* | |
245 | * Clock handling | |
246 | */ | |
247 | static const struct icst307_params realview_oscvco_params = { | |
248 | .ref = 24000, | |
249 | .vco_max = 200000, | |
250 | .vd_min = 4 + 8, | |
251 | .vd_max = 511 + 8, | |
252 | .rd_min = 1 + 2, | |
253 | .rd_max = 127 + 2, | |
254 | }; | |
255 | ||
256 | static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco) | |
257 | { | |
258 | void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET; | |
68c3d935 | 259 | void __iomem *sys_osc; |
8ad68bbf CM |
260 | u32 val; |
261 | ||
68c3d935 CT |
262 | if (machine_is_realview_pb1176()) |
263 | sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET; | |
264 | else | |
265 | sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET; | |
266 | ||
8ad68bbf CM |
267 | val = readl(sys_osc) & ~0x7ffff; |
268 | val |= vco.v | (vco.r << 9) | (vco.s << 16); | |
269 | ||
270 | writel(0xa05f, sys_lock); | |
271 | writel(val, sys_osc); | |
272 | writel(0, sys_lock); | |
273 | } | |
274 | ||
cf30fb4a | 275 | static struct clk oscvco_clk = { |
8ad68bbf CM |
276 | .params = &realview_oscvco_params, |
277 | .setvco = realview_oscvco_set, | |
278 | }; | |
279 | ||
cf30fb4a RK |
280 | /* |
281 | * These are fixed clocks. | |
282 | */ | |
283 | static struct clk ref24_clk = { | |
284 | .rate = 24000000, | |
285 | }; | |
286 | ||
287 | static struct clk_lookup lookups[] = { | |
288 | { /* UART0 */ | |
289 | .dev_id = "dev:f1", | |
290 | .clk = &ref24_clk, | |
291 | }, { /* UART1 */ | |
292 | .dev_id = "dev:f2", | |
293 | .clk = &ref24_clk, | |
294 | }, { /* UART2 */ | |
295 | .dev_id = "dev:f3", | |
296 | .clk = &ref24_clk, | |
297 | }, { /* UART3 */ | |
298 | .dev_id = "fpga:09", | |
299 | .clk = &ref24_clk, | |
300 | }, { /* KMI0 */ | |
301 | .dev_id = "fpga:06", | |
302 | .clk = &ref24_clk, | |
303 | }, { /* KMI1 */ | |
304 | .dev_id = "fpga:07", | |
305 | .clk = &ref24_clk, | |
306 | }, { /* MMC0 */ | |
307 | .dev_id = "fpga:05", | |
308 | .clk = &ref24_clk, | |
309 | }, { /* EB:CLCD */ | |
310 | .dev_id = "dev:20", | |
311 | .clk = &oscvco_clk, | |
312 | }, { /* PB:CLCD */ | |
313 | .dev_id = "issp:20", | |
314 | .clk = &oscvco_clk, | |
315 | } | |
316 | }; | |
317 | ||
318 | static int __init clk_init(void) | |
319 | { | |
320 | int i; | |
321 | ||
322 | for (i = 0; i < ARRAY_SIZE(lookups); i++) | |
323 | clkdev_add(&lookups[i]); | |
324 | return 0; | |
325 | } | |
326 | arch_initcall(clk_init); | |
327 | ||
8ad68bbf CM |
328 | /* |
329 | * CLCD support. | |
330 | */ | |
8ad68bbf CM |
331 | #define SYS_CLCD_NLCDIOON (1 << 2) |
332 | #define SYS_CLCD_VDDPOSSWITCH (1 << 3) | |
333 | #define SYS_CLCD_PWR3V5SWITCH (1 << 4) | |
334 | #define SYS_CLCD_ID_MASK (0x1f << 8) | |
335 | #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8) | |
336 | #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8) | |
337 | #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8) | |
338 | #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8) | |
339 | #define SYS_CLCD_ID_VGA (0x1f << 8) | |
340 | ||
341 | static struct clcd_panel vga = { | |
342 | .mode = { | |
343 | .name = "VGA", | |
344 | .refresh = 60, | |
345 | .xres = 640, | |
346 | .yres = 480, | |
347 | .pixclock = 39721, | |
348 | .left_margin = 40, | |
349 | .right_margin = 24, | |
350 | .upper_margin = 32, | |
351 | .lower_margin = 11, | |
352 | .hsync_len = 96, | |
353 | .vsync_len = 2, | |
354 | .sync = 0, | |
355 | .vmode = FB_VMODE_NONINTERLACED, | |
356 | }, | |
357 | .width = -1, | |
358 | .height = -1, | |
359 | .tim2 = TIM2_BCD | TIM2_IPC, | |
4eccca20 | 360 | .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), |
8ad68bbf CM |
361 | .bpp = 16, |
362 | }; | |
363 | ||
c34a1025 CT |
364 | static struct clcd_panel xvga = { |
365 | .mode = { | |
366 | .name = "XVGA", | |
367 | .refresh = 60, | |
368 | .xres = 1024, | |
369 | .yres = 768, | |
370 | .pixclock = 15748, | |
371 | .left_margin = 152, | |
372 | .right_margin = 48, | |
373 | .upper_margin = 23, | |
374 | .lower_margin = 3, | |
375 | .hsync_len = 104, | |
376 | .vsync_len = 4, | |
377 | .sync = 0, | |
378 | .vmode = FB_VMODE_NONINTERLACED, | |
379 | }, | |
380 | .width = -1, | |
381 | .height = -1, | |
382 | .tim2 = TIM2_BCD | TIM2_IPC, | |
4eccca20 | 383 | .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), |
8ad68bbf CM |
384 | .bpp = 16, |
385 | }; | |
386 | ||
387 | static struct clcd_panel sanyo_3_8_in = { | |
388 | .mode = { | |
389 | .name = "Sanyo QVGA", | |
390 | .refresh = 116, | |
391 | .xres = 320, | |
392 | .yres = 240, | |
393 | .pixclock = 100000, | |
394 | .left_margin = 6, | |
395 | .right_margin = 6, | |
396 | .upper_margin = 5, | |
397 | .lower_margin = 5, | |
398 | .hsync_len = 6, | |
399 | .vsync_len = 6, | |
400 | .sync = 0, | |
401 | .vmode = FB_VMODE_NONINTERLACED, | |
402 | }, | |
403 | .width = -1, | |
404 | .height = -1, | |
405 | .tim2 = TIM2_BCD, | |
4eccca20 | 406 | .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), |
8ad68bbf CM |
407 | .bpp = 16, |
408 | }; | |
409 | ||
410 | static struct clcd_panel sanyo_2_5_in = { | |
411 | .mode = { | |
412 | .name = "Sanyo QVGA Portrait", | |
413 | .refresh = 116, | |
414 | .xres = 240, | |
415 | .yres = 320, | |
416 | .pixclock = 100000, | |
417 | .left_margin = 20, | |
418 | .right_margin = 10, | |
419 | .upper_margin = 2, | |
420 | .lower_margin = 2, | |
421 | .hsync_len = 10, | |
422 | .vsync_len = 2, | |
423 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
424 | .vmode = FB_VMODE_NONINTERLACED, | |
425 | }, | |
426 | .width = -1, | |
427 | .height = -1, | |
428 | .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC, | |
4eccca20 | 429 | .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), |
8ad68bbf CM |
430 | .bpp = 16, |
431 | }; | |
432 | ||
433 | static struct clcd_panel epson_2_2_in = { | |
434 | .mode = { | |
435 | .name = "Epson QCIF", | |
436 | .refresh = 390, | |
437 | .xres = 176, | |
438 | .yres = 220, | |
439 | .pixclock = 62500, | |
440 | .left_margin = 3, | |
441 | .right_margin = 2, | |
442 | .upper_margin = 1, | |
443 | .lower_margin = 0, | |
444 | .hsync_len = 3, | |
445 | .vsync_len = 2, | |
446 | .sync = 0, | |
447 | .vmode = FB_VMODE_NONINTERLACED, | |
448 | }, | |
449 | .width = -1, | |
450 | .height = -1, | |
451 | .tim2 = TIM2_BCD | TIM2_IPC, | |
4eccca20 | 452 | .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), |
8ad68bbf CM |
453 | .bpp = 16, |
454 | }; | |
455 | ||
456 | /* | |
457 | * Detect which LCD panel is connected, and return the appropriate | |
458 | * clcd_panel structure. Note: we do not have any information on | |
459 | * the required timings for the 8.4in panel, so we presently assume | |
460 | * VGA timings. | |
461 | */ | |
462 | static struct clcd_panel *realview_clcd_panel(void) | |
463 | { | |
464 | void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET; | |
c34a1025 CT |
465 | struct clcd_panel *vga_panel; |
466 | struct clcd_panel *panel; | |
8ad68bbf CM |
467 | u32 val; |
468 | ||
c34a1025 CT |
469 | if (machine_is_realview_eb()) |
470 | vga_panel = &vga; | |
471 | else | |
472 | vga_panel = &xvga; | |
473 | ||
8ad68bbf CM |
474 | val = readl(sys_clcd) & SYS_CLCD_ID_MASK; |
475 | if (val == SYS_CLCD_ID_SANYO_3_8) | |
476 | panel = &sanyo_3_8_in; | |
477 | else if (val == SYS_CLCD_ID_SANYO_2_5) | |
478 | panel = &sanyo_2_5_in; | |
479 | else if (val == SYS_CLCD_ID_EPSON_2_2) | |
480 | panel = &epson_2_2_in; | |
481 | else if (val == SYS_CLCD_ID_VGA) | |
c34a1025 | 482 | panel = vga_panel; |
8ad68bbf CM |
483 | else { |
484 | printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n", | |
485 | val); | |
c34a1025 | 486 | panel = vga_panel; |
8ad68bbf CM |
487 | } |
488 | ||
489 | return panel; | |
490 | } | |
491 | ||
492 | /* | |
493 | * Disable all display connectors on the interface module. | |
494 | */ | |
495 | static void realview_clcd_disable(struct clcd_fb *fb) | |
496 | { | |
497 | void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET; | |
498 | u32 val; | |
499 | ||
500 | val = readl(sys_clcd); | |
501 | val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH; | |
502 | writel(val, sys_clcd); | |
503 | } | |
504 | ||
505 | /* | |
506 | * Enable the relevant connector on the interface module. | |
507 | */ | |
508 | static void realview_clcd_enable(struct clcd_fb *fb) | |
509 | { | |
510 | void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET; | |
511 | u32 val; | |
512 | ||
8ad68bbf | 513 | /* |
9e7714d0 | 514 | * Enable the PSUs |
8ad68bbf | 515 | */ |
9e7714d0 | 516 | val = readl(sys_clcd); |
8ad68bbf CM |
517 | val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH; |
518 | writel(val, sys_clcd); | |
519 | } | |
520 | ||
8ad68bbf CM |
521 | static int realview_clcd_setup(struct clcd_fb *fb) |
522 | { | |
c34a1025 | 523 | unsigned long framesize; |
8ad68bbf CM |
524 | dma_addr_t dma; |
525 | ||
c34a1025 CT |
526 | if (machine_is_realview_eb()) |
527 | /* VGA, 16bpp */ | |
528 | framesize = 640 * 480 * 2; | |
529 | else | |
530 | /* XVGA, 16bpp */ | |
531 | framesize = 1024 * 768 * 2; | |
532 | ||
8ad68bbf CM |
533 | fb->panel = realview_clcd_panel(); |
534 | ||
535 | fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize, | |
536 | &dma, GFP_KERNEL); | |
537 | if (!fb->fb.screen_base) { | |
538 | printk(KERN_ERR "CLCD: unable to map framebuffer\n"); | |
539 | return -ENOMEM; | |
540 | } | |
541 | ||
542 | fb->fb.fix.smem_start = dma; | |
543 | fb->fb.fix.smem_len = framesize; | |
544 | ||
545 | return 0; | |
546 | } | |
547 | ||
548 | static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma) | |
549 | { | |
550 | return dma_mmap_writecombine(&fb->dev->dev, vma, | |
551 | fb->fb.screen_base, | |
552 | fb->fb.fix.smem_start, | |
553 | fb->fb.fix.smem_len); | |
554 | } | |
555 | ||
556 | static void realview_clcd_remove(struct clcd_fb *fb) | |
557 | { | |
558 | dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len, | |
559 | fb->fb.screen_base, fb->fb.fix.smem_start); | |
560 | } | |
561 | ||
562 | struct clcd_board clcd_plat_data = { | |
563 | .name = "RealView", | |
564 | .check = clcdfb_check, | |
565 | .decode = clcdfb_decode, | |
566 | .disable = realview_clcd_disable, | |
567 | .enable = realview_clcd_enable, | |
568 | .setup = realview_clcd_setup, | |
569 | .mmap = realview_clcd_mmap, | |
570 | .remove = realview_clcd_remove, | |
571 | }; | |
572 | ||
573 | #ifdef CONFIG_LEDS | |
574 | #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET) | |
575 | ||
576 | void realview_leds_event(led_event_t ledevt) | |
577 | { | |
578 | unsigned long flags; | |
579 | u32 val; | |
580 | ||
581 | local_irq_save(flags); | |
582 | val = readl(VA_LEDS_BASE); | |
583 | ||
584 | switch (ledevt) { | |
585 | case led_idle_start: | |
586 | val = val & ~REALVIEW_SYS_LED0; | |
587 | break; | |
588 | ||
589 | case led_idle_end: | |
590 | val = val | REALVIEW_SYS_LED0; | |
591 | break; | |
592 | ||
593 | case led_timer: | |
594 | val = val ^ REALVIEW_SYS_LED1; | |
595 | break; | |
596 | ||
597 | case led_halted: | |
598 | val = 0; | |
599 | break; | |
600 | ||
601 | default: | |
602 | break; | |
603 | } | |
604 | ||
605 | writel(val, VA_LEDS_BASE); | |
606 | local_irq_restore(flags); | |
607 | } | |
608 | #endif /* CONFIG_LEDS */ | |
609 | ||
610 | /* | |
611 | * Where is the timer (VA)? | |
612 | */ | |
80192735 CM |
613 | void __iomem *timer0_va_base; |
614 | void __iomem *timer1_va_base; | |
615 | void __iomem *timer2_va_base; | |
616 | void __iomem *timer3_va_base; | |
8ad68bbf CM |
617 | |
618 | /* | |
619 | * How long is the timer interval? | |
620 | */ | |
621 | #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10) | |
622 | #if TIMER_INTERVAL >= 0x100000 | |
623 | #define TIMER_RELOAD (TIMER_INTERVAL >> 8) | |
624 | #define TIMER_DIVISOR (TIMER_CTRL_DIV256) | |
625 | #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC) | |
626 | #elif TIMER_INTERVAL >= 0x10000 | |
627 | #define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */ | |
628 | #define TIMER_DIVISOR (TIMER_CTRL_DIV16) | |
629 | #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC) | |
630 | #else | |
631 | #define TIMER_RELOAD (TIMER_INTERVAL) | |
632 | #define TIMER_DIVISOR (TIMER_CTRL_DIV1) | |
633 | #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC) | |
634 | #endif | |
635 | ||
ae30ceac CM |
636 | static void timer_set_mode(enum clock_event_mode mode, |
637 | struct clock_event_device *clk) | |
638 | { | |
639 | unsigned long ctrl; | |
640 | ||
641 | switch(mode) { | |
642 | case CLOCK_EVT_MODE_PERIODIC: | |
80192735 | 643 | writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD); |
ae30ceac CM |
644 | |
645 | ctrl = TIMER_CTRL_PERIODIC; | |
646 | ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE; | |
647 | break; | |
648 | case CLOCK_EVT_MODE_ONESHOT: | |
649 | /* period set, and timer enabled in 'next_event' hook */ | |
650 | ctrl = TIMER_CTRL_ONESHOT; | |
651 | ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE; | |
652 | break; | |
653 | case CLOCK_EVT_MODE_UNUSED: | |
654 | case CLOCK_EVT_MODE_SHUTDOWN: | |
655 | default: | |
656 | ctrl = 0; | |
657 | } | |
658 | ||
80192735 | 659 | writel(ctrl, timer0_va_base + TIMER_CTRL); |
ae30ceac CM |
660 | } |
661 | ||
662 | static int timer_set_next_event(unsigned long evt, | |
663 | struct clock_event_device *unused) | |
664 | { | |
80192735 | 665 | unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL); |
ae30ceac | 666 | |
80192735 CM |
667 | writel(evt, timer0_va_base + TIMER_LOAD); |
668 | writel(ctrl | TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL); | |
ae30ceac CM |
669 | |
670 | return 0; | |
671 | } | |
672 | ||
673 | static struct clock_event_device timer0_clockevent = { | |
674 | .name = "timer0", | |
675 | .shift = 32, | |
676 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
677 | .set_mode = timer_set_mode, | |
678 | .set_next_event = timer_set_next_event, | |
679 | .rating = 300, | |
320ab2b0 | 680 | .cpumask = cpu_all_mask, |
ae30ceac CM |
681 | }; |
682 | ||
8cc4c548 | 683 | static void __init realview_clockevents_init(unsigned int timer_irq) |
ae30ceac | 684 | { |
8cc4c548 | 685 | timer0_clockevent.irq = timer_irq; |
ae30ceac CM |
686 | timer0_clockevent.mult = |
687 | div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift); | |
688 | timer0_clockevent.max_delta_ns = | |
689 | clockevent_delta2ns(0xffffffff, &timer0_clockevent); | |
690 | timer0_clockevent.min_delta_ns = | |
691 | clockevent_delta2ns(0xf, &timer0_clockevent); | |
692 | ||
693 | clockevents_register_device(&timer0_clockevent); | |
694 | } | |
695 | ||
8ad68bbf CM |
696 | /* |
697 | * IRQ handler for the timer | |
698 | */ | |
0cd61b68 | 699 | static irqreturn_t realview_timer_interrupt(int irq, void *dev_id) |
8ad68bbf | 700 | { |
ae30ceac | 701 | struct clock_event_device *evt = &timer0_clockevent; |
8ad68bbf | 702 | |
ae30ceac | 703 | /* clear the interrupt */ |
80192735 | 704 | writel(1, timer0_va_base + TIMER_INTCLR); |
8ad68bbf | 705 | |
ae30ceac | 706 | evt->event_handler(evt); |
dbebb4cb | 707 | |
8ad68bbf CM |
708 | return IRQ_HANDLED; |
709 | } | |
710 | ||
711 | static struct irqaction realview_timer_irq = { | |
712 | .name = "RealView Timer Tick", | |
b30fabad | 713 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
8ad68bbf CM |
714 | .handler = realview_timer_interrupt, |
715 | }; | |
716 | ||
85802afe CM |
717 | static cycle_t realview_get_cycles(void) |
718 | { | |
80192735 | 719 | return ~readl(timer3_va_base + TIMER_VALUE); |
85802afe CM |
720 | } |
721 | ||
722 | static struct clocksource clocksource_realview = { | |
723 | .name = "timer3", | |
724 | .rating = 200, | |
725 | .read = realview_get_cycles, | |
726 | .mask = CLOCKSOURCE_MASK(32), | |
727 | .shift = 20, | |
728 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
729 | }; | |
730 | ||
731 | static void __init realview_clocksource_init(void) | |
732 | { | |
733 | /* setup timer 0 as free-running clocksource */ | |
80192735 CM |
734 | writel(0, timer3_va_base + TIMER_CTRL); |
735 | writel(0xffffffff, timer3_va_base + TIMER_LOAD); | |
736 | writel(0xffffffff, timer3_va_base + TIMER_VALUE); | |
85802afe | 737 | writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, |
80192735 | 738 | timer3_va_base + TIMER_CTRL); |
85802afe CM |
739 | |
740 | clocksource_realview.mult = | |
741 | clocksource_khz2mult(1000, clocksource_realview.shift); | |
742 | clocksource_register(&clocksource_realview); | |
743 | } | |
744 | ||
8ad68bbf | 745 | /* |
a8655e83 | 746 | * Set up the clock source and clock events devices |
8ad68bbf | 747 | */ |
8cc4c548 | 748 | void __init realview_timer_init(unsigned int timer_irq) |
8ad68bbf CM |
749 | { |
750 | u32 val; | |
751 | ||
a8655e83 CM |
752 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
753 | /* | |
754 | * The dummy clock device has to be registered before the main device | |
755 | * so that the latter will broadcast the clock events | |
756 | */ | |
ebac6546 | 757 | local_timer_setup(); |
a8655e83 CM |
758 | #endif |
759 | ||
8ad68bbf CM |
760 | /* |
761 | * set clock frequency: | |
762 | * REALVIEW_REFCLK is 32KHz | |
763 | * REALVIEW_TIMCLK is 1MHz | |
764 | */ | |
765 | val = readl(__io_address(REALVIEW_SCTL_BASE)); | |
766 | writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) | | |
767 | (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) | | |
768 | (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) | | |
769 | (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val, | |
770 | __io_address(REALVIEW_SCTL_BASE)); | |
771 | ||
772 | /* | |
773 | * Initialise to a known state (all timers off) | |
774 | */ | |
80192735 CM |
775 | writel(0, timer0_va_base + TIMER_CTRL); |
776 | writel(0, timer1_va_base + TIMER_CTRL); | |
777 | writel(0, timer2_va_base + TIMER_CTRL); | |
778 | writel(0, timer3_va_base + TIMER_CTRL); | |
8ad68bbf | 779 | |
8ad68bbf CM |
780 | /* |
781 | * Make irqs happen for the system timer | |
782 | */ | |
8cc4c548 | 783 | setup_irq(timer_irq, &realview_timer_irq); |
85802afe CM |
784 | |
785 | realview_clocksource_init(); | |
8cc4c548 | 786 | realview_clockevents_init(timer_irq); |
8ad68bbf | 787 | } |