[deliverable/linux.git] / arch / arm / mach-realview / core.c

/*
 *  linux/arch/arm/mach-realview/core.c
 *
 *  Copyright (C) 1999 - 2003 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/sysdev.h>
#include <linux/interrupt.h>
#include <linux/amba/bus.h>
#include <linux/amba/clcd.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/io.h>
#include <linux/smc911x.h>

#include <asm/clkdev.h>
#include <asm/system.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/leds.h>
#include <asm/mach-types.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/icst307.h>

#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/mmc.h>

#include <asm/hardware/gic.h>

#include "core.h"
#include "clock.h"

#define REALVIEW_REFCOUNTER	(__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)

/* used by entry-macro.S and platsmp.c */
void __iomem *gic_cpu_base_addr;

/*
 * This is the RealView sched_clock implementation.  This has
 * a resolution of 41.7ns, and a maximum value of about 179s.
 */
unsigned long long sched_clock(void)
{
	unsigned long long v;

	v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
	do_div(v, 3);

	return v;
}


#define REALVIEW_FLASHCTRL    (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)

static int realview_flash_init(void)
{
	u32 val;

	val = __raw_readl(REALVIEW_FLASHCTRL);
	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	__raw_writel(val, REALVIEW_FLASHCTRL);

	return 0;
}

static void realview_flash_exit(void)
{
	u32 val;

	val = __raw_readl(REALVIEW_FLASHCTRL);
	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	__raw_writel(val, REALVIEW_FLASHCTRL);
}

static void realview_flash_set_vpp(int on)
{
	u32 val;

	val = __raw_readl(REALVIEW_FLASHCTRL);
	if (on)
		val |= REALVIEW_FLASHPROG_FLVPPEN;
	else
		val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	__raw_writel(val, REALVIEW_FLASHCTRL);
}

static struct flash_platform_data realview_flash_data = {
	.map_name		= "cfi_probe",
	.width			= 4,
	.init			= realview_flash_init,
	.exit			= realview_flash_exit,
	.set_vpp		= realview_flash_set_vpp,
};

struct platform_device realview_flash_device = {
	.name			= "armflash",
	.id			= 0,
	.dev			= {
		.platform_data	= &realview_flash_data,
	},
};

int realview_flash_register(struct resource *res, u32 num)
{
	realview_flash_device.resource = res;
	realview_flash_device.num_resources = num;
	return platform_device_register(&realview_flash_device);
}

static struct smc911x_platdata realview_smc911x_platdata = {
	.flags		= SMC911X_USE_32BIT,
	.irq_flags	= IRQF_SHARED,
	.irq_polarity	= 1,
};

static struct platform_device realview_eth_device = {
	.name		= "smc911x",
	.id		= 0,
	.num_resources	= 2,
};

int realview_eth_register(const char *name, struct resource *res)
{
	if (name)
		realview_eth_device.name = name;
	realview_eth_device.resource = res;
	if (strcmp(realview_eth_device.name, "smc911x") == 0)
		realview_eth_device.dev.platform_data = &realview_smc911x_platdata;

	return platform_device_register(&realview_eth_device);
}

static struct resource realview_i2c_resource = {
	.start		= REALVIEW_I2C_BASE,
	.end		= REALVIEW_I2C_BASE + SZ_4K - 1,
	.flags		= IORESOURCE_MEM,
};

struct platform_device realview_i2c_device = {
	.name		= "versatile-i2c",
	.id		= 0,
	.num_resources	= 1,
	.resource	= &realview_i2c_resource,
};

static struct i2c_board_info realview_i2c_board_info[] = {
	{
		I2C_BOARD_INFO("rtc-ds1307", 0xd0 >> 1),
		.type = "ds1338",
	},
};

static int __init realview_i2c_init(void)
{
	return i2c_register_board_info(0, realview_i2c_board_info,
				       ARRAY_SIZE(realview_i2c_board_info));
}
arch_initcall(realview_i2c_init);

#define REALVIEW_SYSMCI	(__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)

static unsigned int realview_mmc_status(struct device *dev)
{
	struct amba_device *adev = container_of(dev, struct amba_device, dev);
	u32 mask;

	if (adev->res.start == REALVIEW_MMCI0_BASE)
		mask = 1;
	else
		mask = 2;

	return readl(REALVIEW_SYSMCI) & mask;
}

struct mmc_platform_data realview_mmc0_plat_data = {
	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
	.status		= realview_mmc_status,
};

struct mmc_platform_data realview_mmc1_plat_data = {
	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
	.status		= realview_mmc_status,
};

/*
 * Clock handling
 */
static const struct icst307_params realview_oscvco_params = {
	.ref		= 24000,
	.vco_max	= 200000,
	.vd_min		= 4 + 8,
	.vd_max		= 511 + 8,
	.rd_min		= 1 + 2,
	.rd_max		= 127 + 2,
};

static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
{
	void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
	void __iomem *sys_osc;
	u32 val;

	if (machine_is_realview_pb1176())
		sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
	else
		sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;

	val = readl(sys_osc) & ~0x7ffff;
	val |= vco.v | (vco.r << 9) | (vco.s << 16);

	writel(0xa05f, sys_lock);
	writel(val, sys_osc);
	writel(0, sys_lock);
}

static struct clk oscvco_clk = {
	.params	= &realview_oscvco_params,
	.setvco = realview_oscvco_set,
};

/*
 * These are fixed clocks.
 */
static struct clk ref24_clk = {
	.rate	= 24000000,
};

static struct clk_lookup lookups[] = {
	{	/* UART0 */
		.dev_id		= "dev:f1",
		.clk		= &ref24_clk,
	}, {	/* UART1 */
		.dev_id		= "dev:f2",
		.clk		= &ref24_clk,
	}, {	/* UART2 */
		.dev_id		= "dev:f3",
		.clk		= &ref24_clk,
	}, {	/* UART3 */
		.dev_id		= "fpga:09",
		.clk		= &ref24_clk,
	}, {	/* KMI0 */
		.dev_id		= "fpga:06",
		.clk		= &ref24_clk,
	}, {	/* KMI1 */
		.dev_id		= "fpga:07",
		.clk		= &ref24_clk,
	}, {	/* MMC0 */
		.dev_id		= "fpga:05",
		.clk		= &ref24_clk,
	}, {	/* EB:CLCD */
		.dev_id		= "dev:20",
		.clk		= &oscvco_clk,
	}, {	/* PB:CLCD */
		.dev_id		= "issp:20",
		.clk		= &oscvco_clk,
	}
};

static int __init clk_init(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(lookups); i++)
		clkdev_add(&lookups[i]);
	return 0;
}
arch_initcall(clk_init);

/*
 * CLCD support.
 */
#define SYS_CLCD_NLCDIOON	(1 << 2)
#define SYS_CLCD_VDDPOSSWITCH	(1 << 3)
#define SYS_CLCD_PWR3V5SWITCH	(1 << 4)
#define SYS_CLCD_ID_MASK	(0x1f << 8)
#define SYS_CLCD_ID_SANYO_3_8	(0x00 << 8)
#define SYS_CLCD_ID_UNKNOWN_8_4	(0x01 << 8)
#define SYS_CLCD_ID_EPSON_2_2	(0x02 << 8)
#define SYS_CLCD_ID_SANYO_2_5	(0x07 << 8)
#define SYS_CLCD_ID_VGA		(0x1f << 8)

static struct clcd_panel vga = {
	.mode		= {
		.name		= "VGA",
		.refresh	= 60,
		.xres		= 640,
		.yres		= 480,
		.pixclock	= 39721,
		.left_margin	= 40,
		.right_margin	= 24,
		.upper_margin	= 32,
		.lower_margin	= 11,
		.hsync_len	= 96,
		.vsync_len	= 2,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static struct clcd_panel xvga = {
	.mode		= {
		.name		= "XVGA",
		.refresh	= 60,
		.xres		= 1024,
		.yres		= 768,
		.pixclock	= 15748,
		.left_margin	= 152,
		.right_margin	= 48,
		.upper_margin	= 23,
		.lower_margin	= 3,
		.hsync_len	= 104,
		.vsync_len	= 4,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static struct clcd_panel sanyo_3_8_in = {
	.mode		= {
		.name		= "Sanyo QVGA",
		.refresh	= 116,
		.xres		= 320,
		.yres		= 240,
		.pixclock	= 100000,
		.left_margin	= 6,
		.right_margin	= 6,
		.upper_margin	= 5,
		.lower_margin	= 5,
		.hsync_len	= 6,
		.vsync_len	= 6,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static struct clcd_panel sanyo_2_5_in = {
	.mode		= {
		.name		= "Sanyo QVGA Portrait",
		.refresh	= 116,
		.xres		= 240,
		.yres		= 320,
		.pixclock	= 100000,
		.left_margin	= 20,
		.right_margin	= 10,
		.upper_margin	= 2,
		.lower_margin	= 2,
		.hsync_len	= 10,
		.vsync_len	= 2,
		.sync		= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_IVS | TIM2_IHS | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static struct clcd_panel epson_2_2_in = {
	.mode		= {
		.name		= "Epson QCIF",
		.refresh	= 390,
		.xres		= 176,
		.yres		= 220,
		.pixclock	= 62500,
		.left_margin	= 3,
		.right_margin	= 2,
		.upper_margin	= 1,
		.lower_margin	= 0,
		.hsync_len	= 3,
		.vsync_len	= 2,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

/*
 * Detect which LCD panel is connected, and return the appropriate
 * clcd_panel structure.  Note: we do not have any information on
 * the required timings for the 8.4in panel, so we presently assume
 * VGA timings.
 */
static struct clcd_panel *realview_clcd_panel(void)
{
	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	struct clcd_panel *vga_panel;
	struct clcd_panel *panel;
	u32 val;

	if (machine_is_realview_eb())
		vga_panel = &vga;
	else
		vga_panel = &xvga;

	val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
	if (val == SYS_CLCD_ID_SANYO_3_8)
		panel = &sanyo_3_8_in;
	else if (val == SYS_CLCD_ID_SANYO_2_5)
		panel = &sanyo_2_5_in;
	else if (val == SYS_CLCD_ID_EPSON_2_2)
		panel = &epson_2_2_in;
	else if (val == SYS_CLCD_ID_VGA)
		panel = vga_panel;
	else {
		printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
			val);
		panel = vga_panel;
	}

	return panel;
}

/*
 * Disable all display connectors on the interface module.
 */
static void realview_clcd_disable(struct clcd_fb *fb)
{
	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	u32 val;

	val = readl(sys_clcd);
	val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
	writel(val, sys_clcd);
}

/*
 * Enable the relevant connector on the interface module.
 */
static void realview_clcd_enable(struct clcd_fb *fb)
{
	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	u32 val;

	/*
	 * Enable the PSUs
	 */
	val = readl(sys_clcd);
	val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
	writel(val, sys_clcd);
}

static int realview_clcd_setup(struct clcd_fb *fb)
{
	unsigned long framesize;
	dma_addr_t dma;

	if (machine_is_realview_eb())
		/* VGA, 16bpp */
		framesize = 640 * 480 * 2;
	else
		/* XVGA, 16bpp */
		framesize = 1024 * 768 * 2;

	fb->panel		= realview_clcd_panel();

	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
						    &dma, GFP_KERNEL);
	if (!fb->fb.screen_base) {
		printk(KERN_ERR "CLCD: unable to map framebuffer\n");
		return -ENOMEM;
	}

	fb->fb.fix.smem_start	= dma;
	fb->fb.fix.smem_len	= framesize;

	return 0;
}

static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
{
	return dma_mmap_writecombine(&fb->dev->dev, vma,
				     fb->fb.screen_base,
				     fb->fb.fix.smem_start,
				     fb->fb.fix.smem_len);
}

static void realview_clcd_remove(struct clcd_fb *fb)
{
	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
			      fb->fb.screen_base, fb->fb.fix.smem_start);
}

struct clcd_board clcd_plat_data = {
	.name		= "RealView",
	.check		= clcdfb_check,
	.decode		= clcdfb_decode,
	.disable	= realview_clcd_disable,
	.enable		= realview_clcd_enable,
	.setup		= realview_clcd_setup,
	.mmap		= realview_clcd_mmap,
	.remove		= realview_clcd_remove,
};

#ifdef CONFIG_LEDS
#define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)

void realview_leds_event(led_event_t ledevt)
{
	unsigned long flags;
	u32 val;

	local_irq_save(flags);
	val = readl(VA_LEDS_BASE);

	switch (ledevt) {
	case led_idle_start:
		val = val & ~REALVIEW_SYS_LED0;
		break;

	case led_idle_end:
		val = val | REALVIEW_SYS_LED0;
		break;

	case led_timer:
		val = val ^ REALVIEW_SYS_LED1;
		break;

	case led_halted:
		val = 0;
		break;

	default:
		break;
	}

	writel(val, VA_LEDS_BASE);
	local_irq_restore(flags);
}
#endif	/* CONFIG_LEDS */

/*
 * Where is the timer (VA)?
 */
void __iomem *timer0_va_base;
void __iomem *timer1_va_base;
void __iomem *timer2_va_base;
void __iomem *timer3_va_base;

/*
 * How long is the timer interval?
 */
#define TIMER_INTERVAL	(TICKS_PER_uSEC * mSEC_10)
#if TIMER_INTERVAL >= 0x100000
#define TIMER_RELOAD	(TIMER_INTERVAL >> 8)
#define TIMER_DIVISOR	(TIMER_CTRL_DIV256)
#define TICKS2USECS(x)	(256 * (x) / TICKS_PER_uSEC)
#elif TIMER_INTERVAL >= 0x10000
#define TIMER_RELOAD	(TIMER_INTERVAL >> 4)		/* Divide by 16 */
#define TIMER_DIVISOR	(TIMER_CTRL_DIV16)
#define TICKS2USECS(x)	(16 * (x) / TICKS_PER_uSEC)
#else
#define TIMER_RELOAD	(TIMER_INTERVAL)
#define TIMER_DIVISOR	(TIMER_CTRL_DIV1)
#define TICKS2USECS(x)	((x) / TICKS_PER_uSEC)
#endif

static void timer_set_mode(enum clock_event_mode mode,
			   struct clock_event_device *clk)
{
	unsigned long ctrl;

	switch(mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD);

		ctrl = TIMER_CTRL_PERIODIC;
		ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		/* period set, and timer enabled in 'next_event' hook */
		ctrl = TIMER_CTRL_ONESHOT;
		ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	default:
		ctrl = 0;
	}

	writel(ctrl, timer0_va_base + TIMER_CTRL);
}

static int timer_set_next_event(unsigned long evt,
				struct clock_event_device *unused)
{
	unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL);

	writel(evt, timer0_va_base + TIMER_LOAD);
	writel(ctrl | TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL);

	return 0;
}

static struct clock_event_device timer0_clockevent =	 {
	.name		= "timer0",
	.shift		= 32,
	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_mode	= timer_set_mode,
	.set_next_event	= timer_set_next_event,
	.rating		= 300,
	.cpumask	= cpu_all_mask,
};

static void __init realview_clockevents_init(unsigned int timer_irq)
{
	timer0_clockevent.irq = timer_irq;
	timer0_clockevent.mult =
		div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
	timer0_clockevent.max_delta_ns =
		clockevent_delta2ns(0xffffffff, &timer0_clockevent);
	timer0_clockevent.min_delta_ns =
		clockevent_delta2ns(0xf, &timer0_clockevent);

	clockevents_register_device(&timer0_clockevent);
}

/*
 * IRQ handler for the timer
 */
static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = &timer0_clockevent;

	/* clear the interrupt */
	writel(1, timer0_va_base + TIMER_INTCLR);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction realview_timer_irq = {
	.name		= "RealView Timer Tick",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= realview_timer_interrupt,
};

static cycle_t realview_get_cycles(void)
{
	return ~readl(timer3_va_base + TIMER_VALUE);
}

static struct clocksource clocksource_realview = {
	.name	= "timer3",
	.rating	= 200,
	.read	= realview_get_cycles,
	.mask	= CLOCKSOURCE_MASK(32),
	.shift	= 20,
	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
};

static void __init realview_clocksource_init(void)
{
	/* setup timer 0 as free-running clocksource */
	writel(0, timer3_va_base + TIMER_CTRL);
	writel(0xffffffff, timer3_va_base + TIMER_LOAD);
	writel(0xffffffff, timer3_va_base + TIMER_VALUE);
	writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
		timer3_va_base + TIMER_CTRL);

	clocksource_realview.mult =
		clocksource_khz2mult(1000, clocksource_realview.shift);
	clocksource_register(&clocksource_realview);
}

/*
 * Set up the clock source and clock events devices
 */
void __init realview_timer_init(unsigned int timer_irq)
{
	u32 val;

#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
	/*
	 * The dummy clock device has to be registered before the main device
	 * so that the latter will broadcast the clock events
	 */
	local_timer_setup();
#endif

	/* 
	 * set clock frequency: 
	 *	REALVIEW_REFCLK is 32KHz
	 *	REALVIEW_TIMCLK is 1MHz
	 */
	val = readl(__io_address(REALVIEW_SCTL_BASE));
	writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
	       (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) | 
	       (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
	       (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
	       __io_address(REALVIEW_SCTL_BASE));

	/*
	 * Initialise to a known state (all timers off)
	 */
	writel(0, timer0_va_base + TIMER_CTRL);
	writel(0, timer1_va_base + TIMER_CTRL);
	writel(0, timer2_va_base + TIMER_CTRL);
	writel(0, timer3_va_base + TIMER_CTRL);

	/* 
	 * Make irqs happen for the system timer
	 */
	setup_irq(timer_irq, &realview_timer_irq);

	realview_clocksource_init();
	realview_clockevents_init(timer_irq);
}
Commit	Line	Data
8ad68bbf CM	1	/*
	2	* linux/arch/arm/mach-realview/core.c
	3	*
	4	* Copyright (C) 1999 - 2003 ARM Limited
	5	* Copyright (C) 2000 Deep Blue Solutions Ltd
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
8ad68bbf	21	#include <linux/init.h>
1be7228d	22	#include <linux/platform_device.h>
8ad68bbf CM	23	#include <linux/dma-mapping.h>
	24	#include <linux/sysdev.h>
	25	#include <linux/interrupt.h>
a62c80e5 RK	26	#include <linux/amba/bus.h>
a62c80e5 RK	27	#include <linux/amba/clcd.h>
85802afe	28	#include <linux/clocksource.h>
ae30ceac	29	#include <linux/clockchips.h>
fced80c7	30	#include <linux/io.h>
0a5b2f6b	31	#include <linux/smc911x.h>
8ad68bbf	32
cf30fb4a	33	#include <asm/clkdev.h>
8ad68bbf	34	#include <asm/system.h>
a09e64fb	35	#include <mach/hardware.h>
8ad68bbf CM	36	#include <asm/irq.h>
8ad68bbf CM	37	#include <asm/leds.h>
68c3d935	38	#include <asm/mach-types.h>
8ad68bbf CM	39	#include <asm/hardware/arm_timer.h>
	40	#include <asm/hardware/icst307.h>
	41
	42	#include <asm/mach/arch.h>
	43	#include <asm/mach/flash.h>
	44	#include <asm/mach/irq.h>
8ad68bbf CM	45	#include <asm/mach/map.h>
	46	#include <asm/mach/mmc.h>
	47
	48	#include <asm/hardware/gic.h>
	49
	50	#include "core.h"
	51	#include "clock.h"
	52
	53	#define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
	54
1bbdf637	55	/* used by entry-macro.S and platsmp.c */
c4057f52 CM	56	void __iomem *gic_cpu_base_addr;
c4057f52 CM	57
8ad68bbf CM	58	/*
	59	* This is the RealView sched_clock implementation. This has
	60	* a resolution of 41.7ns, and a maximum value of about 179s.
	61	*/
	62	unsigned long long sched_clock(void)
	63	{
	64	unsigned long long v;
	65
	66	v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
	67	do_div(v, 3);
	68
	69	return v;
	70	}
	71
	72
	73	#define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
	74
	75	static int realview_flash_init(void)
	76	{
	77	u32 val;
	78
	79	val = __raw_readl(REALVIEW_FLASHCTRL);
	80	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	81	__raw_writel(val, REALVIEW_FLASHCTRL);
	82
	83	return 0;
	84	}
	85
	86	static void realview_flash_exit(void)
	87	{
	88	u32 val;
	89
	90	val = __raw_readl(REALVIEW_FLASHCTRL);
	91	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	92	__raw_writel(val, REALVIEW_FLASHCTRL);
	93	}
	94
	95	static void realview_flash_set_vpp(int on)
	96	{
	97	u32 val;
	98
	99	val = __raw_readl(REALVIEW_FLASHCTRL);
	100	if (on)
	101	val \|= REALVIEW_FLASHPROG_FLVPPEN;
	102	else
	103	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	104	__raw_writel(val, REALVIEW_FLASHCTRL);
	105	}
	106
	107	static struct flash_platform_data realview_flash_data = {
	108	.map_name = "cfi_probe",
	109	.width = 4,
	110	.init = realview_flash_init,
	111	.exit = realview_flash_exit,
	112	.set_vpp = realview_flash_set_vpp,
	113	};
	114
8ad68bbf CM	115	struct platform_device realview_flash_device = {
	116	.name = "armflash",
	117	.id = 0,
	118	.dev = {
	119	.platform_data = &realview_flash_data,
	120	},
8ad68bbf CM	121	};
8ad68bbf CM	122
a44ddfd5 CM	123	int realview_flash_register(struct resource *res, u32 num)
	124	{
	125	realview_flash_device.resource = res;
	126	realview_flash_device.num_resources = num;
	127	return platform_device_register(&realview_flash_device);
	128	}
	129
0a5b2f6b CM	130	static struct smc911x_platdata realview_smc911x_platdata = {
	131	.flags = SMC911X_USE_32BIT,
	132	.irq_flags = IRQF_SHARED,
	133	.irq_polarity = 1,
	134	};
	135
0a381330 CM	136	static struct platform_device realview_eth_device = {
	137	.name = "smc911x",
	138	.id = 0,
	139	.num_resources = 2,
	140	};
	141
	142	int realview_eth_register(const char name, struct resource res)
	143	{
	144	if (name)
	145	realview_eth_device.name = name;
	146	realview_eth_device.resource = res;
0a5b2f6b CM	147	if (strcmp(realview_eth_device.name, "smc911x") == 0)
0a5b2f6b CM	148	realview_eth_device.dev.platform_data = &realview_smc911x_platdata;
0a381330 CM	149
	150	return platform_device_register(&realview_eth_device);
	151	}
	152
6b65cd74 RK	153	static struct resource realview_i2c_resource = {
	154	.start = REALVIEW_I2C_BASE,
	155	.end = REALVIEW_I2C_BASE + SZ_4K - 1,
	156	.flags = IORESOURCE_MEM,
	157	};
	158
	159	struct platform_device realview_i2c_device = {
	160	.name = "versatile-i2c",
533ad5e6	161	.id = 0,
6b65cd74 RK	162	.num_resources = 1,
	163	.resource = &realview_i2c_resource,
	164	};
	165
533ad5e6 CM	166	static struct i2c_board_info realview_i2c_board_info[] = {
	167	{
	168	I2C_BOARD_INFO("rtc-ds1307", 0xd0 >> 1),
	169	.type = "ds1338",
	170	},
	171	};
	172
	173	static int __init realview_i2c_init(void)
	174	{
	175	return i2c_register_board_info(0, realview_i2c_board_info,
	176	ARRAY_SIZE(realview_i2c_board_info));
	177	}
	178	arch_initcall(realview_i2c_init);
	179
8ad68bbf CM	180	#define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
	181
	182	static unsigned int realview_mmc_status(struct device *dev)
	183	{
	184	struct amba_device *adev = container_of(dev, struct amba_device, dev);
	185	u32 mask;
	186
	187	if (adev->res.start == REALVIEW_MMCI0_BASE)
	188	mask = 1;
	189	else
	190	mask = 2;
	191
	192	return readl(REALVIEW_SYSMCI) & mask;
	193	}
	194
	195	struct mmc_platform_data realview_mmc0_plat_data = {
	196	.ocr_mask = MMC_VDD_32_33\|MMC_VDD_33_34,
	197	.status = realview_mmc_status,
	198	};
	199
	200	struct mmc_platform_data realview_mmc1_plat_data = {
	201	.ocr_mask = MMC_VDD_32_33\|MMC_VDD_33_34,
	202	.status = realview_mmc_status,
	203	};
	204
	205	/*
	206	* Clock handling
	207	*/
	208	static const struct icst307_params realview_oscvco_params = {
	209	.ref = 24000,
	210	.vco_max = 200000,
	211	.vd_min = 4 + 8,
	212	.vd_max = 511 + 8,
	213	.rd_min = 1 + 2,
	214	.rd_max = 127 + 2,
	215	};
	216
	217	static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
	218	{
	219	void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
68c3d935	220	void __iomem *sys_osc;
8ad68bbf CM	221	u32 val;
8ad68bbf CM	222
68c3d935 CT	223	if (machine_is_realview_pb1176())
	224	sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
	225	else
	226	sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
	227
8ad68bbf CM	228	val = readl(sys_osc) & ~0x7ffff;
	229	val \|= vco.v \| (vco.r << 9) \| (vco.s << 16);
	230
	231	writel(0xa05f, sys_lock);
	232	writel(val, sys_osc);
	233	writel(0, sys_lock);
	234	}
	235
cf30fb4a	236	static struct clk oscvco_clk = {
8ad68bbf CM	237	.params = &realview_oscvco_params,
	238	.setvco = realview_oscvco_set,
	239	};
	240
cf30fb4a RK	241	/*
	242	* These are fixed clocks.
	243	*/
	244	static struct clk ref24_clk = {
	245	.rate = 24000000,
	246	};
	247
	248	static struct clk_lookup lookups[] = {
	249	{ /* UART0 */
	250	.dev_id = "dev:f1",
	251	.clk = &ref24_clk,
	252	}, { /* UART1 */
	253	.dev_id = "dev:f2",
	254	.clk = &ref24_clk,
	255	}, { /* UART2 */
	256	.dev_id = "dev:f3",
	257	.clk = &ref24_clk,
	258	}, { /* UART3 */
	259	.dev_id = "fpga:09",
	260	.clk = &ref24_clk,
	261	}, { /* KMI0 */
	262	.dev_id = "fpga:06",
	263	.clk = &ref24_clk,
	264	}, { /* KMI1 */
	265	.dev_id = "fpga:07",
	266	.clk = &ref24_clk,
	267	}, { /* MMC0 */
	268	.dev_id = "fpga:05",
	269	.clk = &ref24_clk,
	270	}, { /* EB:CLCD */
	271	.dev_id = "dev:20",
	272	.clk = &oscvco_clk,
	273	}, { /* PB:CLCD */
	274	.dev_id = "issp:20",
	275	.clk = &oscvco_clk,
	276	}
	277	};
	278
	279	static int __init clk_init(void)
	280	{
	281	int i;
	282
	283	for (i = 0; i < ARRAY_SIZE(lookups); i++)
	284	clkdev_add(&lookups[i]);
	285	return 0;
	286	}
	287	arch_initcall(clk_init);
	288
8ad68bbf CM	289	/*
	290	* CLCD support.
	291	*/
8ad68bbf CM	292	#define SYS_CLCD_NLCDIOON (1 << 2)
	293	#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
	294	#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
	295	#define SYS_CLCD_ID_MASK (0x1f << 8)
	296	#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
	297	#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
	298	#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
	299	#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
	300	#define SYS_CLCD_ID_VGA (0x1f << 8)
	301
	302	static struct clcd_panel vga = {
	303	.mode = {
	304	.name = "VGA",
	305	.refresh = 60,
	306	.xres = 640,
	307	.yres = 480,
	308	.pixclock = 39721,
	309	.left_margin = 40,
	310	.right_margin = 24,
	311	.upper_margin = 32,
	312	.lower_margin = 11,
	313	.hsync_len = 96,
	314	.vsync_len = 2,
	315	.sync = 0,
	316	.vmode = FB_VMODE_NONINTERLACED,
	317	},
	318	.width = -1,
	319	.height = -1,
	320	.tim2 = TIM2_BCD \| TIM2_IPC,
4eccca20	321	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
8ad68bbf CM	322	.bpp = 16,
	323	};
	324
c34a1025 CT	325	static struct clcd_panel xvga = {
	326	.mode = {
	327	.name = "XVGA",
	328	.refresh = 60,
	329	.xres = 1024,
	330	.yres = 768,
	331	.pixclock = 15748,
	332	.left_margin = 152,
	333	.right_margin = 48,
	334	.upper_margin = 23,
	335	.lower_margin = 3,
	336	.hsync_len = 104,
	337	.vsync_len = 4,
	338	.sync = 0,
	339	.vmode = FB_VMODE_NONINTERLACED,
	340	},
	341	.width = -1,
	342	.height = -1,
	343	.tim2 = TIM2_BCD \| TIM2_IPC,
4eccca20	344	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
8ad68bbf CM	345	.bpp = 16,
	346	};
	347
	348	static struct clcd_panel sanyo_3_8_in = {
	349	.mode = {
	350	.name = "Sanyo QVGA",
	351	.refresh = 116,
	352	.xres = 320,
	353	.yres = 240,
	354	.pixclock = 100000,
	355	.left_margin = 6,
	356	.right_margin = 6,
	357	.upper_margin = 5,
	358	.lower_margin = 5,
	359	.hsync_len = 6,
	360	.vsync_len = 6,
	361	.sync = 0,
	362	.vmode = FB_VMODE_NONINTERLACED,
	363	},
	364	.width = -1,
	365	.height = -1,
	366	.tim2 = TIM2_BCD,
4eccca20	367	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
8ad68bbf CM	368	.bpp = 16,
	369	};
	370
	371	static struct clcd_panel sanyo_2_5_in = {
	372	.mode = {
	373	.name = "Sanyo QVGA Portrait",
	374	.refresh = 116,
	375	.xres = 240,
	376	.yres = 320,
	377	.pixclock = 100000,
	378	.left_margin = 20,
	379	.right_margin = 10,
	380	.upper_margin = 2,
	381	.lower_margin = 2,
	382	.hsync_len = 10,
	383	.vsync_len = 2,
	384	.sync = FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	385	.vmode = FB_VMODE_NONINTERLACED,
	386	},
	387	.width = -1,
	388	.height = -1,
	389	.tim2 = TIM2_IVS \| TIM2_IHS \| TIM2_IPC,
4eccca20	390	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
8ad68bbf CM	391	.bpp = 16,
	392	};
	393
	394	static struct clcd_panel epson_2_2_in = {
	395	.mode = {
	396	.name = "Epson QCIF",
	397	.refresh = 390,
	398	.xres = 176,
	399	.yres = 220,
	400	.pixclock = 62500,
	401	.left_margin = 3,
	402	.right_margin = 2,
	403	.upper_margin = 1,
	404	.lower_margin = 0,
	405	.hsync_len = 3,
	406	.vsync_len = 2,
	407	.sync = 0,
	408	.vmode = FB_VMODE_NONINTERLACED,
	409	},
	410	.width = -1,
	411	.height = -1,
	412	.tim2 = TIM2_BCD \| TIM2_IPC,
4eccca20	413	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
8ad68bbf CM	414	.bpp = 16,
	415	};
	416
	417	/*
	418	* Detect which LCD panel is connected, and return the appropriate
	419	* clcd_panel structure. Note: we do not have any information on
	420	* the required timings for the 8.4in panel, so we presently assume
	421	* VGA timings.
	422	*/
	423	static struct clcd_panel *realview_clcd_panel(void)
	424	{
	425	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
c34a1025 CT	426	struct clcd_panel *vga_panel;
c34a1025 CT	427	struct clcd_panel *panel;
8ad68bbf CM	428	u32 val;
8ad68bbf CM	429
c34a1025 CT	430	if (machine_is_realview_eb())
	431	vga_panel = &vga;
	432	else
	433	vga_panel = &xvga;
	434
8ad68bbf CM	435	val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
	436	if (val == SYS_CLCD_ID_SANYO_3_8)
	437	panel = &sanyo_3_8_in;
	438	else if (val == SYS_CLCD_ID_SANYO_2_5)
	439	panel = &sanyo_2_5_in;
	440	else if (val == SYS_CLCD_ID_EPSON_2_2)
	441	panel = &epson_2_2_in;
	442	else if (val == SYS_CLCD_ID_VGA)
c34a1025	443	panel = vga_panel;
8ad68bbf CM	444	else {
	445	printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
	446	val);
c34a1025	447	panel = vga_panel;
8ad68bbf CM	448	}
	449
	450	return panel;
	451	}
	452
	453	/*
	454	* Disable all display connectors on the interface module.
	455	*/
	456	static void realview_clcd_disable(struct clcd_fb *fb)
	457	{
	458	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	459	u32 val;
	460
	461	val = readl(sys_clcd);
	462	val &= ~SYS_CLCD_NLCDIOON \| SYS_CLCD_PWR3V5SWITCH;
	463	writel(val, sys_clcd);
	464	}
	465
	466	/*
	467	* Enable the relevant connector on the interface module.
	468	*/
	469	static void realview_clcd_enable(struct clcd_fb *fb)
	470	{
	471	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	472	u32 val;
	473
8ad68bbf	474	/*
9e7714d0	475	* Enable the PSUs
8ad68bbf	476	*/
9e7714d0	477	val = readl(sys_clcd);
8ad68bbf CM	478	val \|= SYS_CLCD_NLCDIOON \| SYS_CLCD_PWR3V5SWITCH;
	479	writel(val, sys_clcd);
	480	}
	481
8ad68bbf CM	482	static int realview_clcd_setup(struct clcd_fb *fb)
8ad68bbf CM	483	{
c34a1025	484	unsigned long framesize;
8ad68bbf CM	485	dma_addr_t dma;
8ad68bbf CM	486
c34a1025 CT	487	if (machine_is_realview_eb())
	488	/* VGA, 16bpp */
	489	framesize = 640 * 480 * 2;
	490	else
	491	/* XVGA, 16bpp */
	492	framesize = 1024 * 768 * 2;
	493
8ad68bbf CM	494	fb->panel = realview_clcd_panel();
	495
	496	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
	497	&dma, GFP_KERNEL);
	498	if (!fb->fb.screen_base) {
	499	printk(KERN_ERR "CLCD: unable to map framebuffer\n");
	500	return -ENOMEM;
	501	}
	502
	503	fb->fb.fix.smem_start = dma;
	504	fb->fb.fix.smem_len = framesize;
	505
	506	return 0;
	507	}
	508
	509	static int realview_clcd_mmap(struct clcd_fb fb, struct vm_area_struct vma)
	510	{
	511	return dma_mmap_writecombine(&fb->dev->dev, vma,
	512	fb->fb.screen_base,
	513	fb->fb.fix.smem_start,
	514	fb->fb.fix.smem_len);
	515	}
	516
	517	static void realview_clcd_remove(struct clcd_fb *fb)
	518	{
	519	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
	520	fb->fb.screen_base, fb->fb.fix.smem_start);
	521	}
	522
	523	struct clcd_board clcd_plat_data = {
	524	.name = "RealView",
	525	.check = clcdfb_check,
	526	.decode = clcdfb_decode,
	527	.disable = realview_clcd_disable,
	528	.enable = realview_clcd_enable,
	529	.setup = realview_clcd_setup,
	530	.mmap = realview_clcd_mmap,
	531	.remove = realview_clcd_remove,
	532	};
	533
	534	#ifdef CONFIG_LEDS
	535	#define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
	536
	537	void realview_leds_event(led_event_t ledevt)
	538	{
	539	unsigned long flags;
	540	u32 val;
	541
	542	local_irq_save(flags);
	543	val = readl(VA_LEDS_BASE);
	544
	545	switch (ledevt) {
	546	case led_idle_start:
	547	val = val & ~REALVIEW_SYS_LED0;
	548	break;
	549
	550	case led_idle_end:
	551	val = val \| REALVIEW_SYS_LED0;
	552	break;
	553
	554	case led_timer:
	555	val = val ^ REALVIEW_SYS_LED1;
	556	break;
	557
558	case led_halted:
559	val = 0;
560	break;
561
562	default:
563	break;
564	}
565
566	writel(val, VA_LEDS_BASE);
567	local_irq_restore(flags);
568	}
569	#endif /* CONFIG_LEDS */
570
571	/*
572	* Where is the timer (VA)?
573	*/
80192735 CM	574	void __iomem *timer0_va_base;
	575	void __iomem *timer1_va_base;
	576	void __iomem *timer2_va_base;
	577	void __iomem *timer3_va_base;
8ad68bbf CM	578
	579	/*
	580	* How long is the timer interval?
	581	*/
	582	#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
	583	#if TIMER_INTERVAL >= 0x100000
	584	#define TIMER_RELOAD (TIMER_INTERVAL >> 8)
	585	#define TIMER_DIVISOR (TIMER_CTRL_DIV256)
	586	#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
	587	#elif TIMER_INTERVAL >= 0x10000
	588	#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
	589	#define TIMER_DIVISOR (TIMER_CTRL_DIV16)
	590	#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
	591	#else
	592	#define TIMER_RELOAD (TIMER_INTERVAL)
	593	#define TIMER_DIVISOR (TIMER_CTRL_DIV1)
	594	#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
	595	#endif
	596
ae30ceac CM	597	static void timer_set_mode(enum clock_event_mode mode,
	598	struct clock_event_device *clk)
	599	{
	600	unsigned long ctrl;
	601
	602	switch(mode) {
	603	case CLOCK_EVT_MODE_PERIODIC:
80192735	604	writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD);
ae30ceac CM	605
	606	ctrl = TIMER_CTRL_PERIODIC;
	607	ctrl \|= TIMER_CTRL_32BIT \| TIMER_CTRL_IE \| TIMER_CTRL_ENABLE;
	608	break;
	609	case CLOCK_EVT_MODE_ONESHOT:
	610	/* period set, and timer enabled in 'next_event' hook */
	611	ctrl = TIMER_CTRL_ONESHOT;
	612	ctrl \|= TIMER_CTRL_32BIT \| TIMER_CTRL_IE;
	613	break;
	614	case CLOCK_EVT_MODE_UNUSED:
	615	case CLOCK_EVT_MODE_SHUTDOWN:
	616	default:
	617	ctrl = 0;
	618	}
	619
80192735	620	writel(ctrl, timer0_va_base + TIMER_CTRL);
ae30ceac CM	621	}
	622
	623	static int timer_set_next_event(unsigned long evt,
	624	struct clock_event_device *unused)
	625	{
80192735	626	unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL);
ae30ceac	627
80192735 CM	628	writel(evt, timer0_va_base + TIMER_LOAD);
80192735 CM	629	writel(ctrl \| TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL);
ae30ceac CM	630
	631	return 0;
	632	}
	633
	634	static struct clock_event_device timer0_clockevent = {
	635	.name = "timer0",
	636	.shift = 32,
	637	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	638	.set_mode = timer_set_mode,
	639	.set_next_event = timer_set_next_event,
	640	.rating = 300,
320ab2b0	641	.cpumask = cpu_all_mask,
ae30ceac CM	642	};
ae30ceac CM	643
8cc4c548	644	static void __init realview_clockevents_init(unsigned int timer_irq)
ae30ceac	645	{
8cc4c548	646	timer0_clockevent.irq = timer_irq;
ae30ceac CM	647	timer0_clockevent.mult =
	648	div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
	649	timer0_clockevent.max_delta_ns =
	650	clockevent_delta2ns(0xffffffff, &timer0_clockevent);
	651	timer0_clockevent.min_delta_ns =
	652	clockevent_delta2ns(0xf, &timer0_clockevent);
	653
	654	clockevents_register_device(&timer0_clockevent);
	655	}
	656
8ad68bbf CM	657	/*
	658	* IRQ handler for the timer
	659	*/
0cd61b68	660	static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
8ad68bbf	661	{
ae30ceac	662	struct clock_event_device *evt = &timer0_clockevent;
8ad68bbf	663
ae30ceac	664	/* clear the interrupt */
80192735	665	writel(1, timer0_va_base + TIMER_INTCLR);
8ad68bbf	666
ae30ceac	667	evt->event_handler(evt);
dbebb4cb	668
8ad68bbf CM	669	return IRQ_HANDLED;
	670	}
	671
	672	static struct irqaction realview_timer_irq = {
	673	.name = "RealView Timer Tick",
b30fabad	674	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
8ad68bbf CM	675	.handler = realview_timer_interrupt,
	676	};
	677
85802afe CM	678	static cycle_t realview_get_cycles(void)
85802afe CM	679	{
80192735	680	return ~readl(timer3_va_base + TIMER_VALUE);
85802afe CM	681	}
	682
	683	static struct clocksource clocksource_realview = {
	684	.name = "timer3",
	685	.rating = 200,
	686	.read = realview_get_cycles,
	687	.mask = CLOCKSOURCE_MASK(32),
	688	.shift = 20,
	689	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	690	};
	691
	692	static void __init realview_clocksource_init(void)
	693	{
	694	/* setup timer 0 as free-running clocksource */
80192735 CM	695	writel(0, timer3_va_base + TIMER_CTRL);
	696	writel(0xffffffff, timer3_va_base + TIMER_LOAD);
	697	writel(0xffffffff, timer3_va_base + TIMER_VALUE);
85802afe	698	writel(TIMER_CTRL_32BIT \| TIMER_CTRL_ENABLE \| TIMER_CTRL_PERIODIC,
80192735	699	timer3_va_base + TIMER_CTRL);
85802afe CM	700
	701	clocksource_realview.mult =
	702	clocksource_khz2mult(1000, clocksource_realview.shift);
	703	clocksource_register(&clocksource_realview);
	704	}
	705
8ad68bbf	706	/*
a8655e83	707	* Set up the clock source and clock events devices
8ad68bbf	708	*/
8cc4c548	709	void __init realview_timer_init(unsigned int timer_irq)
8ad68bbf CM	710	{
	711	u32 val;
	712
a8655e83 CM	713	#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
	714	/*
	715	* The dummy clock device has to be registered before the main device
	716	* so that the latter will broadcast the clock events
	717	*/
ebac6546	718	local_timer_setup();
a8655e83 CM	719	#endif
a8655e83 CM	720
8ad68bbf CM	721	/*
	722	* set clock frequency:
	723	* REALVIEW_REFCLK is 32KHz
	724	* REALVIEW_TIMCLK is 1MHz
	725	*/
	726	val = readl(__io_address(REALVIEW_SCTL_BASE));
	727	writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) \|
	728	(REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) \|
	729	(REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) \|
	730	(REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) \| val,
	731	__io_address(REALVIEW_SCTL_BASE));
	732
	733	/*
	734	* Initialise to a known state (all timers off)
	735	*/
80192735 CM	736	writel(0, timer0_va_base + TIMER_CTRL);
	737	writel(0, timer1_va_base + TIMER_CTRL);
	738	writel(0, timer2_va_base + TIMER_CTRL);
	739	writel(0, timer3_va_base + TIMER_CTRL);
8ad68bbf	740
8ad68bbf CM	741	/*
	742	* Make irqs happen for the system timer
	743	*/
8cc4c548	744	setup_irq(timer_irq, &realview_timer_irq);
85802afe CM	745
85802afe CM	746	realview_clocksource_init();
8cc4c548	747	realview_clockevents_init(timer_irq);
8ad68bbf	748	}