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8ad68bbf CM |
1 | /* |
2 | * linux/arch/arm/mach-realview/core.c | |
3 | * | |
4 | * Copyright (C) 1999 - 2003 ARM Limited | |
5 | * Copyright (C) 2000 Deep Blue Solutions Ltd | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
8ad68bbf | 21 | #include <linux/init.h> |
1be7228d | 22 | #include <linux/platform_device.h> |
8ad68bbf | 23 | #include <linux/dma-mapping.h> |
edbaa603 | 24 | #include <linux/device.h> |
8ad68bbf | 25 | #include <linux/interrupt.h> |
a62c80e5 RK |
26 | #include <linux/amba/bus.h> |
27 | #include <linux/amba/clcd.h> | |
fced80c7 | 28 | #include <linux/io.h> |
c5142e84 | 29 | #include <linux/smsc911x.h> |
6be62ba2 | 30 | #include <linux/ata_platform.h> |
6ef297f8 | 31 | #include <linux/amba/mmci.h> |
5a0e3ad6 | 32 | #include <linux/gfp.h> |
6d803ba7 | 33 | #include <linux/clkdev.h> |
b8b87aef | 34 | #include <linux/mtd/physmap.h> |
8ad68bbf | 35 | |
a09e64fb | 36 | #include <mach/hardware.h> |
8ad68bbf CM |
37 | #include <asm/irq.h> |
38 | #include <asm/leds.h> | |
68c3d935 | 39 | #include <asm/mach-types.h> |
8ad68bbf | 40 | #include <asm/hardware/arm_timer.h> |
c5a0adb5 | 41 | #include <asm/hardware/icst.h> |
8ad68bbf CM |
42 | |
43 | #include <asm/mach/arch.h> | |
8ad68bbf | 44 | #include <asm/mach/irq.h> |
8ad68bbf | 45 | #include <asm/mach/map.h> |
8ad68bbf CM |
46 | |
47 | #include <asm/hardware/gic.h> | |
48 | ||
ee8c9571 CM |
49 | #include <mach/platform.h> |
50 | #include <mach/irqs.h> | |
8a9618f5 | 51 | #include <asm/hardware/timer-sp.h> |
ee8c9571 | 52 | |
3cb5ee49 | 53 | #include <plat/clcd.h> |
1da0c89c RK |
54 | #include <plat/sched_clock.h> |
55 | ||
8ad68bbf | 56 | #include "core.h" |
8ad68bbf | 57 | |
8ad68bbf CM |
58 | #define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET) |
59 | ||
667f390b | 60 | static void realview_flash_set_vpp(struct platform_device *pdev, int on) |
8ad68bbf CM |
61 | { |
62 | u32 val; | |
63 | ||
64 | val = __raw_readl(REALVIEW_FLASHCTRL); | |
65 | if (on) | |
66 | val |= REALVIEW_FLASHPROG_FLVPPEN; | |
67 | else | |
68 | val &= ~REALVIEW_FLASHPROG_FLVPPEN; | |
69 | __raw_writel(val, REALVIEW_FLASHCTRL); | |
70 | } | |
71 | ||
b8b87aef | 72 | static struct physmap_flash_data realview_flash_data = { |
8ad68bbf | 73 | .width = 4, |
8ad68bbf CM |
74 | .set_vpp = realview_flash_set_vpp, |
75 | }; | |
76 | ||
8ad68bbf | 77 | struct platform_device realview_flash_device = { |
b8b87aef | 78 | .name = "physmap-flash", |
8ad68bbf CM |
79 | .id = 0, |
80 | .dev = { | |
81 | .platform_data = &realview_flash_data, | |
82 | }, | |
8ad68bbf CM |
83 | }; |
84 | ||
a44ddfd5 CM |
85 | int realview_flash_register(struct resource *res, u32 num) |
86 | { | |
87 | realview_flash_device.resource = res; | |
88 | realview_flash_device.num_resources = num; | |
89 | return platform_device_register(&realview_flash_device); | |
90 | } | |
91 | ||
c5142e84 SG |
92 | static struct smsc911x_platform_config smsc911x_config = { |
93 | .flags = SMSC911X_USE_32BIT, | |
94 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, | |
95 | .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, | |
96 | .phy_interface = PHY_INTERFACE_MODE_MII, | |
0a5b2f6b CM |
97 | }; |
98 | ||
0a381330 | 99 | static struct platform_device realview_eth_device = { |
c5142e84 | 100 | .name = "smsc911x", |
0a381330 CM |
101 | .id = 0, |
102 | .num_resources = 2, | |
103 | }; | |
104 | ||
105 | int realview_eth_register(const char *name, struct resource *res) | |
106 | { | |
107 | if (name) | |
108 | realview_eth_device.name = name; | |
109 | realview_eth_device.resource = res; | |
c5142e84 SG |
110 | if (strcmp(realview_eth_device.name, "smsc911x") == 0) |
111 | realview_eth_device.dev.platform_data = &smsc911x_config; | |
0a381330 CM |
112 | |
113 | return platform_device_register(&realview_eth_device); | |
7db21712 CM |
114 | } |
115 | ||
116 | struct platform_device realview_usb_device = { | |
117 | .name = "isp1760", | |
118 | .num_resources = 2, | |
119 | }; | |
120 | ||
121 | int realview_usb_register(struct resource *res) | |
122 | { | |
123 | realview_usb_device.resource = res; | |
124 | return platform_device_register(&realview_usb_device); | |
0a381330 CM |
125 | } |
126 | ||
6be62ba2 CM |
127 | static struct pata_platform_info pata_platform_data = { |
128 | .ioport_shift = 1, | |
129 | }; | |
130 | ||
131 | static struct resource pata_resources[] = { | |
132 | [0] = { | |
133 | .start = REALVIEW_CF_BASE, | |
134 | .end = REALVIEW_CF_BASE + 0xff, | |
135 | .flags = IORESOURCE_MEM, | |
136 | }, | |
137 | [1] = { | |
138 | .start = REALVIEW_CF_BASE + 0x100, | |
139 | .end = REALVIEW_CF_BASE + SZ_4K - 1, | |
140 | .flags = IORESOURCE_MEM, | |
141 | }, | |
142 | }; | |
143 | ||
144 | struct platform_device realview_cf_device = { | |
145 | .name = "pata_platform", | |
146 | .id = -1, | |
147 | .num_resources = ARRAY_SIZE(pata_resources), | |
148 | .resource = pata_resources, | |
149 | .dev = { | |
150 | .platform_data = &pata_platform_data, | |
151 | }, | |
152 | }; | |
153 | ||
6b65cd74 RK |
154 | static struct resource realview_i2c_resource = { |
155 | .start = REALVIEW_I2C_BASE, | |
156 | .end = REALVIEW_I2C_BASE + SZ_4K - 1, | |
157 | .flags = IORESOURCE_MEM, | |
158 | }; | |
159 | ||
160 | struct platform_device realview_i2c_device = { | |
161 | .name = "versatile-i2c", | |
533ad5e6 | 162 | .id = 0, |
6b65cd74 RK |
163 | .num_resources = 1, |
164 | .resource = &realview_i2c_resource, | |
165 | }; | |
166 | ||
533ad5e6 CM |
167 | static struct i2c_board_info realview_i2c_board_info[] = { |
168 | { | |
64e8be6e | 169 | I2C_BOARD_INFO("ds1338", 0xd0 >> 1), |
533ad5e6 CM |
170 | }, |
171 | }; | |
172 | ||
173 | static int __init realview_i2c_init(void) | |
174 | { | |
175 | return i2c_register_board_info(0, realview_i2c_board_info, | |
176 | ARRAY_SIZE(realview_i2c_board_info)); | |
177 | } | |
178 | arch_initcall(realview_i2c_init); | |
179 | ||
8ad68bbf CM |
180 | #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET) |
181 | ||
98b0979f RK |
182 | /* |
183 | * This is only used if GPIOLIB support is disabled | |
184 | */ | |
8ad68bbf CM |
185 | static unsigned int realview_mmc_status(struct device *dev) |
186 | { | |
187 | struct amba_device *adev = container_of(dev, struct amba_device, dev); | |
188 | u32 mask; | |
189 | ||
48f1d5a3 LW |
190 | if (machine_is_realview_pb1176()) { |
191 | static bool inserted = false; | |
192 | ||
193 | /* | |
194 | * The PB1176 does not have the status register, | |
195 | * assume it is inserted at startup, then invert | |
196 | * for each call so card insertion/removal will | |
197 | * be detected anyway. This will not be called if | |
198 | * GPIO on PL061 is active, which is the proper | |
199 | * way to do this on the PB1176. | |
200 | */ | |
201 | inserted = !inserted; | |
202 | return inserted ? 0 : 1; | |
203 | } | |
204 | ||
8ad68bbf CM |
205 | if (adev->res.start == REALVIEW_MMCI0_BASE) |
206 | mask = 1; | |
207 | else | |
208 | mask = 2; | |
209 | ||
74bc8093 | 210 | return readl(REALVIEW_SYSMCI) & mask; |
8ad68bbf CM |
211 | } |
212 | ||
6ef297f8 | 213 | struct mmci_platform_data realview_mmc0_plat_data = { |
8ad68bbf CM |
214 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, |
215 | .status = realview_mmc_status, | |
98b0979f RK |
216 | .gpio_wp = 17, |
217 | .gpio_cd = 16, | |
29719445 | 218 | .cd_invert = true, |
8ad68bbf CM |
219 | }; |
220 | ||
6ef297f8 | 221 | struct mmci_platform_data realview_mmc1_plat_data = { |
8ad68bbf CM |
222 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, |
223 | .status = realview_mmc_status, | |
98b0979f RK |
224 | .gpio_wp = 19, |
225 | .gpio_cd = 18, | |
29719445 | 226 | .cd_invert = true, |
8ad68bbf CM |
227 | }; |
228 | ||
229 | /* | |
230 | * Clock handling | |
231 | */ | |
39c0cb02 | 232 | static const struct icst_params realview_oscvco_params = { |
64fceb1d | 233 | .ref = 24000000, |
4de2edbd | 234 | .vco_max = ICST307_VCO_MAX, |
e73a46a3 | 235 | .vco_min = ICST307_VCO_MIN, |
8ad68bbf CM |
236 | .vd_min = 4 + 8, |
237 | .vd_max = 511 + 8, | |
238 | .rd_min = 1 + 2, | |
239 | .rd_max = 127 + 2, | |
232eaf7f RK |
240 | .s2div = icst307_s2div, |
241 | .idx2s = icst307_idx2s, | |
8ad68bbf CM |
242 | }; |
243 | ||
39c0cb02 | 244 | static void realview_oscvco_set(struct clk *clk, struct icst_vco vco) |
8ad68bbf CM |
245 | { |
246 | void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET; | |
8ad68bbf CM |
247 | u32 val; |
248 | ||
d1914c7e | 249 | val = readl(clk->vcoreg) & ~0x7ffff; |
8ad68bbf CM |
250 | val |= vco.v | (vco.r << 9) | (vco.s << 16); |
251 | ||
252 | writel(0xa05f, sys_lock); | |
d1914c7e | 253 | writel(val, clk->vcoreg); |
8ad68bbf CM |
254 | writel(0, sys_lock); |
255 | } | |
256 | ||
9bf5b2ef RK |
257 | static const struct clk_ops oscvco_clk_ops = { |
258 | .round = icst_clk_round, | |
259 | .set = icst_clk_set, | |
260 | .setvco = realview_oscvco_set, | |
261 | }; | |
262 | ||
cf30fb4a | 263 | static struct clk oscvco_clk = { |
9bf5b2ef | 264 | .ops = &oscvco_clk_ops, |
8ad68bbf | 265 | .params = &realview_oscvco_params, |
8ad68bbf CM |
266 | }; |
267 | ||
cf30fb4a RK |
268 | /* |
269 | * These are fixed clocks. | |
270 | */ | |
271 | static struct clk ref24_clk = { | |
272 | .rate = 24000000, | |
273 | }; | |
274 | ||
7ff550de RK |
275 | static struct clk sp804_clk = { |
276 | .rate = 1000000, | |
277 | }; | |
278 | ||
3126c7bc RK |
279 | static struct clk dummy_apb_pclk; |
280 | ||
cf30fb4a | 281 | static struct clk_lookup lookups[] = { |
3126c7bc RK |
282 | { /* Bus clock */ |
283 | .con_id = "apb_pclk", | |
284 | .clk = &dummy_apb_pclk, | |
285 | }, { /* UART0 */ | |
4321532c | 286 | .dev_id = "dev:uart0", |
cf30fb4a RK |
287 | .clk = &ref24_clk, |
288 | }, { /* UART1 */ | |
4321532c | 289 | .dev_id = "dev:uart1", |
cf30fb4a RK |
290 | .clk = &ref24_clk, |
291 | }, { /* UART2 */ | |
4321532c | 292 | .dev_id = "dev:uart2", |
cf30fb4a RK |
293 | .clk = &ref24_clk, |
294 | }, { /* UART3 */ | |
4321532c | 295 | .dev_id = "fpga:uart3", |
cf30fb4a | 296 | .clk = &ref24_clk, |
48f1d5a3 LW |
297 | }, { /* UART3 is on the dev chip in PB1176 */ |
298 | .dev_id = "dev:uart3", | |
299 | .clk = &ref24_clk, | |
300 | }, { /* UART4 only exists in PB1176 */ | |
301 | .dev_id = "fpga:uart4", | |
302 | .clk = &ref24_clk, | |
cf30fb4a | 303 | }, { /* KMI0 */ |
4321532c | 304 | .dev_id = "fpga:kmi0", |
cf30fb4a RK |
305 | .clk = &ref24_clk, |
306 | }, { /* KMI1 */ | |
4321532c | 307 | .dev_id = "fpga:kmi1", |
cf30fb4a RK |
308 | .clk = &ref24_clk, |
309 | }, { /* MMC0 */ | |
4321532c | 310 | .dev_id = "fpga:mmc0", |
cf30fb4a | 311 | .clk = &ref24_clk, |
48f1d5a3 | 312 | }, { /* CLCD is in the PB1176 and EB DevChip */ |
4321532c | 313 | .dev_id = "dev:clcd", |
cf30fb4a RK |
314 | .clk = &oscvco_clk, |
315 | }, { /* PB:CLCD */ | |
4321532c | 316 | .dev_id = "issp:clcd", |
cf30fb4a | 317 | .clk = &oscvco_clk, |
d6ada860 LW |
318 | }, { /* SSP */ |
319 | .dev_id = "dev:ssp0", | |
320 | .clk = &ref24_clk, | |
7ff550de RK |
321 | }, { /* SP804 timers */ |
322 | .dev_id = "sp804", | |
323 | .clk = &sp804_clk, | |
324 | }, | |
cf30fb4a RK |
325 | }; |
326 | ||
631e55f9 | 327 | void __init realview_init_early(void) |
cf30fb4a | 328 | { |
631e55f9 RK |
329 | void __iomem *sys = __io_address(REALVIEW_SYS_BASE); |
330 | ||
d1914c7e | 331 | if (machine_is_realview_pb1176()) |
631e55f9 | 332 | oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC0_OFFSET; |
d1914c7e | 333 | else |
631e55f9 | 334 | oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC4_OFFSET; |
d1914c7e | 335 | |
0a0300dc | 336 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); |
d1914c7e | 337 | |
631e55f9 | 338 | versatile_sched_clock_init(sys + REALVIEW_SYS_24MHz_OFFSET, 24000000); |
cf30fb4a | 339 | } |
cf30fb4a | 340 | |
8ad68bbf CM |
341 | /* |
342 | * CLCD support. | |
343 | */ | |
8ad68bbf CM |
344 | #define SYS_CLCD_NLCDIOON (1 << 2) |
345 | #define SYS_CLCD_VDDPOSSWITCH (1 << 3) | |
346 | #define SYS_CLCD_PWR3V5SWITCH (1 << 4) | |
347 | #define SYS_CLCD_ID_MASK (0x1f << 8) | |
348 | #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8) | |
349 | #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8) | |
350 | #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8) | |
351 | #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8) | |
352 | #define SYS_CLCD_ID_VGA (0x1f << 8) | |
353 | ||
8ad68bbf CM |
354 | /* |
355 | * Disable all display connectors on the interface module. | |
356 | */ | |
357 | static void realview_clcd_disable(struct clcd_fb *fb) | |
358 | { | |
359 | void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET; | |
360 | u32 val; | |
361 | ||
362 | val = readl(sys_clcd); | |
363 | val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH; | |
364 | writel(val, sys_clcd); | |
365 | } | |
366 | ||
367 | /* | |
368 | * Enable the relevant connector on the interface module. | |
369 | */ | |
370 | static void realview_clcd_enable(struct clcd_fb *fb) | |
371 | { | |
372 | void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET; | |
373 | u32 val; | |
374 | ||
8ad68bbf | 375 | /* |
9e7714d0 | 376 | * Enable the PSUs |
8ad68bbf | 377 | */ |
9e7714d0 | 378 | val = readl(sys_clcd); |
8ad68bbf CM |
379 | val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH; |
380 | writel(val, sys_clcd); | |
381 | } | |
382 | ||
3cb5ee49 RK |
383 | /* |
384 | * Detect which LCD panel is connected, and return the appropriate | |
385 | * clcd_panel structure. Note: we do not have any information on | |
386 | * the required timings for the 8.4in panel, so we presently assume | |
387 | * VGA timings. | |
388 | */ | |
8ad68bbf CM |
389 | static int realview_clcd_setup(struct clcd_fb *fb) |
390 | { | |
3cb5ee49 RK |
391 | void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET; |
392 | const char *panel_name, *vga_panel_name; | |
c34a1025 | 393 | unsigned long framesize; |
3cb5ee49 | 394 | u32 val; |
8ad68bbf | 395 | |
3cb5ee49 | 396 | if (machine_is_realview_eb()) { |
c34a1025 CT |
397 | /* VGA, 16bpp */ |
398 | framesize = 640 * 480 * 2; | |
3cb5ee49 RK |
399 | vga_panel_name = "VGA"; |
400 | } else { | |
c34a1025 CT |
401 | /* XVGA, 16bpp */ |
402 | framesize = 1024 * 768 * 2; | |
3cb5ee49 | 403 | vga_panel_name = "XVGA"; |
8ad68bbf CM |
404 | } |
405 | ||
3cb5ee49 RK |
406 | val = readl(sys_clcd) & SYS_CLCD_ID_MASK; |
407 | if (val == SYS_CLCD_ID_SANYO_3_8) | |
408 | panel_name = "Sanyo TM38QV67A02A"; | |
409 | else if (val == SYS_CLCD_ID_SANYO_2_5) | |
410 | panel_name = "Sanyo QVGA Portrait"; | |
411 | else if (val == SYS_CLCD_ID_EPSON_2_2) | |
412 | panel_name = "Epson L2F50113T00"; | |
413 | else if (val == SYS_CLCD_ID_VGA) | |
414 | panel_name = vga_panel_name; | |
415 | else { | |
416 | pr_err("CLCD: unknown LCD panel ID 0x%08x, using VGA\n", val); | |
417 | panel_name = vga_panel_name; | |
418 | } | |
8ad68bbf | 419 | |
3cb5ee49 RK |
420 | fb->panel = versatile_clcd_get_panel(panel_name); |
421 | if (!fb->panel) | |
422 | return -EINVAL; | |
8ad68bbf | 423 | |
3cb5ee49 | 424 | return versatile_clcd_setup_dma(fb, framesize); |
8ad68bbf CM |
425 | } |
426 | ||
427 | struct clcd_board clcd_plat_data = { | |
428 | .name = "RealView", | |
3cb5ee49 | 429 | .caps = CLCD_CAP_ALL, |
8ad68bbf CM |
430 | .check = clcdfb_check, |
431 | .decode = clcdfb_decode, | |
432 | .disable = realview_clcd_disable, | |
433 | .enable = realview_clcd_enable, | |
434 | .setup = realview_clcd_setup, | |
3cb5ee49 RK |
435 | .mmap = versatile_clcd_mmap_dma, |
436 | .remove = versatile_clcd_remove_dma, | |
8ad68bbf CM |
437 | }; |
438 | ||
439 | #ifdef CONFIG_LEDS | |
440 | #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET) | |
441 | ||
442 | void realview_leds_event(led_event_t ledevt) | |
443 | { | |
444 | unsigned long flags; | |
445 | u32 val; | |
da055eb5 | 446 | u32 led = 1 << smp_processor_id(); |
8ad68bbf CM |
447 | |
448 | local_irq_save(flags); | |
449 | val = readl(VA_LEDS_BASE); | |
450 | ||
451 | switch (ledevt) { | |
452 | case led_idle_start: | |
da055eb5 | 453 | val = val & ~led; |
8ad68bbf CM |
454 | break; |
455 | ||
456 | case led_idle_end: | |
da055eb5 | 457 | val = val | led; |
8ad68bbf CM |
458 | break; |
459 | ||
460 | case led_timer: | |
da055eb5 | 461 | val = val ^ REALVIEW_SYS_LED7; |
8ad68bbf CM |
462 | break; |
463 | ||
464 | case led_halted: | |
465 | val = 0; | |
466 | break; | |
467 | ||
468 | default: | |
469 | break; | |
470 | } | |
471 | ||
472 | writel(val, VA_LEDS_BASE); | |
473 | local_irq_restore(flags); | |
474 | } | |
475 | #endif /* CONFIG_LEDS */ | |
476 | ||
477 | /* | |
478 | * Where is the timer (VA)? | |
479 | */ | |
80192735 CM |
480 | void __iomem *timer0_va_base; |
481 | void __iomem *timer1_va_base; | |
482 | void __iomem *timer2_va_base; | |
483 | void __iomem *timer3_va_base; | |
8ad68bbf | 484 | |
8ad68bbf | 485 | /* |
a8655e83 | 486 | * Set up the clock source and clock events devices |
8ad68bbf | 487 | */ |
8cc4c548 | 488 | void __init realview_timer_init(unsigned int timer_irq) |
8ad68bbf CM |
489 | { |
490 | u32 val; | |
491 | ||
492 | /* | |
493 | * set clock frequency: | |
494 | * REALVIEW_REFCLK is 32KHz | |
495 | * REALVIEW_TIMCLK is 1MHz | |
496 | */ | |
497 | val = readl(__io_address(REALVIEW_SCTL_BASE)); | |
498 | writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) | | |
499 | (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) | | |
500 | (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) | | |
501 | (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val, | |
502 | __io_address(REALVIEW_SCTL_BASE)); | |
503 | ||
504 | /* | |
505 | * Initialise to a known state (all timers off) | |
506 | */ | |
80192735 CM |
507 | writel(0, timer0_va_base + TIMER_CTRL); |
508 | writel(0, timer1_va_base + TIMER_CTRL); | |
509 | writel(0, timer2_va_base + TIMER_CTRL); | |
510 | writel(0, timer3_va_base + TIMER_CTRL); | |
8ad68bbf | 511 | |
fb593cf3 | 512 | sp804_clocksource_init(timer3_va_base, "timer3"); |
57cc4f7d | 513 | sp804_clockevents_init(timer0_va_base, timer_irq, "timer0"); |
8ad68bbf | 514 | } |
5b39d154 CM |
515 | |
516 | /* | |
517 | * Setup the memory banks. | |
518 | */ | |
0744a3ee | 519 | void realview_fixup(struct tag *tags, char **from, struct meminfo *meminfo) |
5b39d154 CM |
520 | { |
521 | /* | |
522 | * Most RealView platforms have 512MB contiguous RAM at 0x70000000. | |
523 | * Half of this is mirrored at 0. | |
524 | */ | |
525 | #ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET | |
526 | meminfo->bank[0].start = 0x70000000; | |
527 | meminfo->bank[0].size = SZ_512M; | |
528 | meminfo->nr_banks = 1; | |
529 | #else | |
530 | meminfo->bank[0].start = 0; | |
531 | meminfo->bank[0].size = SZ_256M; | |
532 | meminfo->nr_banks = 1; | |
533 | #endif | |
534 | } |