[deliverable/linux.git] / arch / arm / mach-realview / core.c

/*
 *  linux/arch/arm/mach-realview/core.c
 *
 *  Copyright (C) 1999 - 2003 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/sysdev.h>
#include <linux/interrupt.h>
#include <linux/amba/bus.h>
#include <linux/amba/clcd.h>
#include <linux/clocksource.h>

#include <asm/system.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/leds.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/icst307.h>

#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <asm/mach/mmc.h>

#include <asm/hardware/gic.h>

#include "core.h"
#include "clock.h"

#define REALVIEW_REFCOUNTER	(__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)

/*
 * This is the RealView sched_clock implementation.  This has
 * a resolution of 41.7ns, and a maximum value of about 179s.
 */
unsigned long long sched_clock(void)
{
	unsigned long long v;

	v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
	do_div(v, 3);

	return v;
}


#define REALVIEW_FLASHCTRL    (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)

static int realview_flash_init(void)
{
	u32 val;

	val = __raw_readl(REALVIEW_FLASHCTRL);
	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	__raw_writel(val, REALVIEW_FLASHCTRL);

	return 0;
}

static void realview_flash_exit(void)
{
	u32 val;

	val = __raw_readl(REALVIEW_FLASHCTRL);
	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	__raw_writel(val, REALVIEW_FLASHCTRL);
}

static void realview_flash_set_vpp(int on)
{
	u32 val;

	val = __raw_readl(REALVIEW_FLASHCTRL);
	if (on)
		val |= REALVIEW_FLASHPROG_FLVPPEN;
	else
		val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	__raw_writel(val, REALVIEW_FLASHCTRL);
}

static struct flash_platform_data realview_flash_data = {
	.map_name		= "cfi_probe",
	.width			= 4,
	.init			= realview_flash_init,
	.exit			= realview_flash_exit,
	.set_vpp		= realview_flash_set_vpp,
};

static struct resource realview_flash_resource = {
	.start			= REALVIEW_FLASH_BASE,
	.end			= REALVIEW_FLASH_BASE + REALVIEW_FLASH_SIZE,
	.flags			= IORESOURCE_MEM,
};

struct platform_device realview_flash_device = {
	.name			= "armflash",
	.id			= 0,
	.dev			= {
		.platform_data	= &realview_flash_data,
	},
	.num_resources		= 1,
	.resource		= &realview_flash_resource,
};

static struct resource realview_smc91x_resources[] = {
	[0] = {
		.start		= REALVIEW_ETH_BASE,
		.end		= REALVIEW_ETH_BASE + SZ_64K - 1,
		.flags		= IORESOURCE_MEM,
	},
	[1] = {
		.start		= IRQ_ETH,
		.end		= IRQ_ETH,
		.flags		= IORESOURCE_IRQ,
	},
};

struct platform_device realview_smc91x_device = {
	.name		= "smc91x",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(realview_smc91x_resources),
	.resource	= realview_smc91x_resources,
};

static struct resource realview_i2c_resource = {
	.start		= REALVIEW_I2C_BASE,
	.end		= REALVIEW_I2C_BASE + SZ_4K - 1,
	.flags		= IORESOURCE_MEM,
};

struct platform_device realview_i2c_device = {
	.name		= "versatile-i2c",
	.id		= -1,
	.num_resources	= 1,
	.resource	= &realview_i2c_resource,
};

#define REALVIEW_SYSMCI	(__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)

static unsigned int realview_mmc_status(struct device *dev)
{
	struct amba_device *adev = container_of(dev, struct amba_device, dev);
	u32 mask;

	if (adev->res.start == REALVIEW_MMCI0_BASE)
		mask = 1;
	else
		mask = 2;

	return readl(REALVIEW_SYSMCI) & mask;
}

struct mmc_platform_data realview_mmc0_plat_data = {
	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
	.status		= realview_mmc_status,
};

struct mmc_platform_data realview_mmc1_plat_data = {
	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
	.status		= realview_mmc_status,
};

/*
 * Clock handling
 */
static const struct icst307_params realview_oscvco_params = {
	.ref		= 24000,
	.vco_max	= 200000,
	.vd_min		= 4 + 8,
	.vd_max		= 511 + 8,
	.rd_min		= 1 + 2,
	.rd_max		= 127 + 2,
};

static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
{
	void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
	void __iomem *sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
	u32 val;

	val = readl(sys_osc) & ~0x7ffff;
	val |= vco.v | (vco.r << 9) | (vco.s << 16);

	writel(0xa05f, sys_lock);
	writel(val, sys_osc);
	writel(0, sys_lock);
}

struct clk realview_clcd_clk = {
	.name	= "CLCDCLK",
	.params	= &realview_oscvco_params,
	.setvco = realview_oscvco_set,
};

/*
 * CLCD support.
 */
#define SYS_CLCD_NLCDIOON	(1 << 2)
#define SYS_CLCD_VDDPOSSWITCH	(1 << 3)
#define SYS_CLCD_PWR3V5SWITCH	(1 << 4)
#define SYS_CLCD_ID_MASK	(0x1f << 8)
#define SYS_CLCD_ID_SANYO_3_8	(0x00 << 8)
#define SYS_CLCD_ID_UNKNOWN_8_4	(0x01 << 8)
#define SYS_CLCD_ID_EPSON_2_2	(0x02 << 8)
#define SYS_CLCD_ID_SANYO_2_5	(0x07 << 8)
#define SYS_CLCD_ID_VGA		(0x1f << 8)

static struct clcd_panel vga = {
	.mode		= {
		.name		= "VGA",
		.refresh	= 60,
		.xres		= 640,
		.yres		= 480,
		.pixclock	= 39721,
		.left_margin	= 40,
		.right_margin	= 24,
		.upper_margin	= 32,
		.lower_margin	= 11,
		.hsync_len	= 96,
		.vsync_len	= 2,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static struct clcd_panel sanyo_3_8_in = {
	.mode		= {
		.name		= "Sanyo QVGA",
		.refresh	= 116,
		.xres		= 320,
		.yres		= 240,
		.pixclock	= 100000,
		.left_margin	= 6,
		.right_margin	= 6,
		.upper_margin	= 5,
		.lower_margin	= 5,
		.hsync_len	= 6,
		.vsync_len	= 6,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD,
	.cntl		= CNTL_LCDTFT | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static struct clcd_panel sanyo_2_5_in = {
	.mode		= {
		.name		= "Sanyo QVGA Portrait",
		.refresh	= 116,
		.xres		= 240,
		.yres		= 320,
		.pixclock	= 100000,
		.left_margin	= 20,
		.right_margin	= 10,
		.upper_margin	= 2,
		.lower_margin	= 2,
		.hsync_len	= 10,
		.vsync_len	= 2,
		.sync		= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_IVS | TIM2_IHS | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static struct clcd_panel epson_2_2_in = {
	.mode		= {
		.name		= "Epson QCIF",
		.refresh	= 390,
		.xres		= 176,
		.yres		= 220,
		.pixclock	= 62500,
		.left_margin	= 3,
		.right_margin	= 2,
		.upper_margin	= 1,
		.lower_margin	= 0,
		.hsync_len	= 3,
		.vsync_len	= 2,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

/*
 * Detect which LCD panel is connected, and return the appropriate
 * clcd_panel structure.  Note: we do not have any information on
 * the required timings for the 8.4in panel, so we presently assume
 * VGA timings.
 */
static struct clcd_panel *realview_clcd_panel(void)
{
	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	struct clcd_panel *panel = &vga;
	u32 val;

	val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
	if (val == SYS_CLCD_ID_SANYO_3_8)
		panel = &sanyo_3_8_in;
	else if (val == SYS_CLCD_ID_SANYO_2_5)
		panel = &sanyo_2_5_in;
	else if (val == SYS_CLCD_ID_EPSON_2_2)
		panel = &epson_2_2_in;
	else if (val == SYS_CLCD_ID_VGA)
		panel = &vga;
	else {
		printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
			val);
		panel = &vga;
	}

	return panel;
}

/*
 * Disable all display connectors on the interface module.
 */
static void realview_clcd_disable(struct clcd_fb *fb)
{
	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	u32 val;

	val = readl(sys_clcd);
	val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
	writel(val, sys_clcd);
}

/*
 * Enable the relevant connector on the interface module.
 */
static void realview_clcd_enable(struct clcd_fb *fb)
{
	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	u32 val;

	/*
	 * Enable the PSUs
	 */
	val = readl(sys_clcd);
	val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
	writel(val, sys_clcd);
}

static unsigned long framesize = SZ_1M;

static int realview_clcd_setup(struct clcd_fb *fb)
{
	dma_addr_t dma;

	fb->panel		= realview_clcd_panel();

	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
						    &dma, GFP_KERNEL);
	if (!fb->fb.screen_base) {
		printk(KERN_ERR "CLCD: unable to map framebuffer\n");
		return -ENOMEM;
	}

	fb->fb.fix.smem_start	= dma;
	fb->fb.fix.smem_len	= framesize;

	return 0;
}

static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
{
	return dma_mmap_writecombine(&fb->dev->dev, vma,
				     fb->fb.screen_base,
				     fb->fb.fix.smem_start,
				     fb->fb.fix.smem_len);
}

static void realview_clcd_remove(struct clcd_fb *fb)
{
	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
			      fb->fb.screen_base, fb->fb.fix.smem_start);
}

struct clcd_board clcd_plat_data = {
	.name		= "RealView",
	.check		= clcdfb_check,
	.decode		= clcdfb_decode,
	.disable	= realview_clcd_disable,
	.enable		= realview_clcd_enable,
	.setup		= realview_clcd_setup,
	.mmap		= realview_clcd_mmap,
	.remove		= realview_clcd_remove,
};

#ifdef CONFIG_LEDS
#define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)

void realview_leds_event(led_event_t ledevt)
{
	unsigned long flags;
	u32 val;

	local_irq_save(flags);
	val = readl(VA_LEDS_BASE);

	switch (ledevt) {
	case led_idle_start:
		val = val & ~REALVIEW_SYS_LED0;
		break;

	case led_idle_end:
		val = val | REALVIEW_SYS_LED0;
		break;

	case led_timer:
		val = val ^ REALVIEW_SYS_LED1;
		break;

	case led_halted:
		val = 0;
		break;

	default:
		break;
	}

	writel(val, VA_LEDS_BASE);
	local_irq_restore(flags);
}
#endif	/* CONFIG_LEDS */

/*
 * Where is the timer (VA)?
 */
#define TIMER0_VA_BASE		 __io_address(REALVIEW_TIMER0_1_BASE)
#define TIMER1_VA_BASE		(__io_address(REALVIEW_TIMER0_1_BASE) + 0x20)
#define TIMER2_VA_BASE		 __io_address(REALVIEW_TIMER2_3_BASE)
#define TIMER3_VA_BASE		(__io_address(REALVIEW_TIMER2_3_BASE) + 0x20)

/*
 * How long is the timer interval?
 */
#define TIMER_INTERVAL	(TICKS_PER_uSEC * mSEC_10)
#if TIMER_INTERVAL >= 0x100000
#define TIMER_RELOAD	(TIMER_INTERVAL >> 8)
#define TIMER_DIVISOR	(TIMER_CTRL_DIV256)
#define TICKS2USECS(x)	(256 * (x) / TICKS_PER_uSEC)
#elif TIMER_INTERVAL >= 0x10000
#define TIMER_RELOAD	(TIMER_INTERVAL >> 4)		/* Divide by 16 */
#define TIMER_DIVISOR	(TIMER_CTRL_DIV16)
#define TICKS2USECS(x)	(16 * (x) / TICKS_PER_uSEC)
#else
#define TIMER_RELOAD	(TIMER_INTERVAL)
#define TIMER_DIVISOR	(TIMER_CTRL_DIV1)
#define TICKS2USECS(x)	((x) / TICKS_PER_uSEC)
#endif

/*
 * IRQ handler for the timer
 */
static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
{
	// ...clear the interrupt
	writel(1, TIMER0_VA_BASE + TIMER_INTCLR);

	timer_tick();

#if defined(CONFIG_SMP) && !defined(CONFIG_LOCAL_TIMERS)
	smp_send_timer();
	update_process_times(user_mode(get_irq_regs()));
#endif

	return IRQ_HANDLED;
}

static struct irqaction realview_timer_irq = {
	.name		= "RealView Timer Tick",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= realview_timer_interrupt,
};

static cycle_t realview_get_cycles(void)
{
	return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
}

static struct clocksource clocksource_realview = {
	.name	= "timer3",
	.rating	= 200,
	.read	= realview_get_cycles,
	.mask	= CLOCKSOURCE_MASK(32),
	.shift	= 20,
	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
};

static void __init realview_clocksource_init(void)
{
	/* setup timer 0 as free-running clocksource */
	writel(0, TIMER3_VA_BASE + TIMER_CTRL);
	writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
	writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
	writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
		TIMER3_VA_BASE + TIMER_CTRL);

	clocksource_realview.mult =
		clocksource_khz2mult(1000, clocksource_realview.shift);
	clocksource_register(&clocksource_realview);
}

/*
 * Set up timer interrupt, and return the current time in seconds.
 */
static void __init realview_timer_init(void)
{
	u32 val;

	/* 
	 * set clock frequency: 
	 *	REALVIEW_REFCLK is 32KHz
	 *	REALVIEW_TIMCLK is 1MHz
	 */
	val = readl(__io_address(REALVIEW_SCTL_BASE));
	writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
	       (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) | 
	       (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
	       (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
	       __io_address(REALVIEW_SCTL_BASE));

	/*
	 * Initialise to a known state (all timers off)
	 */
	writel(0, TIMER0_VA_BASE + TIMER_CTRL);
	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
	writel(0, TIMER2_VA_BASE + TIMER_CTRL);
	writel(0, TIMER3_VA_BASE + TIMER_CTRL);

	writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
	writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_VALUE);
	writel(TIMER_DIVISOR | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC |
	       TIMER_CTRL_IE, TIMER0_VA_BASE + TIMER_CTRL);

	/* 
	 * Make irqs happen for the system timer
	 */
	setup_irq(IRQ_TIMERINT0_1, &realview_timer_irq);

	realview_clocksource_init();
}

struct sys_timer realview_timer = {
	.init		= realview_timer_init,
};
Commit	Line	Data
8ad68bbf CM	1	/*
	2	* linux/arch/arm/mach-realview/core.c
	3	*
	4	* Copyright (C) 1999 - 2003 ARM Limited
	5	* Copyright (C) 2000 Deep Blue Solutions Ltd
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
8ad68bbf	21	#include <linux/init.h>
1be7228d	22	#include <linux/platform_device.h>
8ad68bbf CM	23	#include <linux/dma-mapping.h>
	24	#include <linux/sysdev.h>
	25	#include <linux/interrupt.h>
a62c80e5 RK	26	#include <linux/amba/bus.h>
a62c80e5 RK	27	#include <linux/amba/clcd.h>
85802afe	28	#include <linux/clocksource.h>
8ad68bbf CM	29
	30	#include <asm/system.h>
	31	#include <asm/hardware.h>
	32	#include <asm/io.h>
	33	#include <asm/irq.h>
	34	#include <asm/leds.h>
8ad68bbf CM	35	#include <asm/hardware/arm_timer.h>
	36	#include <asm/hardware/icst307.h>
	37
	38	#include <asm/mach/arch.h>
	39	#include <asm/mach/flash.h>
	40	#include <asm/mach/irq.h>
	41	#include <asm/mach/time.h>
	42	#include <asm/mach/map.h>
	43	#include <asm/mach/mmc.h>
	44
	45	#include <asm/hardware/gic.h>
	46
	47	#include "core.h"
	48	#include "clock.h"
	49
	50	#define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
	51
	52	/*
	53	* This is the RealView sched_clock implementation. This has
	54	* a resolution of 41.7ns, and a maximum value of about 179s.
	55	*/
	56	unsigned long long sched_clock(void)
	57	{
	58	unsigned long long v;
	59
	60	v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
	61	do_div(v, 3);
	62
	63	return v;
	64	}
	65
	66
	67	#define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
	68
	69	static int realview_flash_init(void)
	70	{
	71	u32 val;
	72
	73	val = __raw_readl(REALVIEW_FLASHCTRL);
	74	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	75	__raw_writel(val, REALVIEW_FLASHCTRL);
	76
	77	return 0;
	78	}
	79
	80	static void realview_flash_exit(void)
	81	{
	82	u32 val;
	83
	84	val = __raw_readl(REALVIEW_FLASHCTRL);
	85	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	86	__raw_writel(val, REALVIEW_FLASHCTRL);
	87	}
	88
	89	static void realview_flash_set_vpp(int on)
	90	{
	91	u32 val;
	92
	93	val = __raw_readl(REALVIEW_FLASHCTRL);
	94	if (on)
	95	val \|= REALVIEW_FLASHPROG_FLVPPEN;
	96	else
	97	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	98	__raw_writel(val, REALVIEW_FLASHCTRL);
99	}
100
101	static struct flash_platform_data realview_flash_data = {
102	.map_name = "cfi_probe",
103	.width = 4,
104	.init = realview_flash_init,
105	.exit = realview_flash_exit,
106	.set_vpp = realview_flash_set_vpp,
107	};
108
109	static struct resource realview_flash_resource = {
110	.start = REALVIEW_FLASH_BASE,
111	.end = REALVIEW_FLASH_BASE + REALVIEW_FLASH_SIZE,
112	.flags = IORESOURCE_MEM,
113	};
114
115	struct platform_device realview_flash_device = {
116	.name = "armflash",
117	.id = 0,
118	.dev = {
119	.platform_data = &realview_flash_data,
120	},
121	.num_resources = 1,
122	.resource = &realview_flash_resource,
123	};
124
125	static struct resource realview_smc91x_resources[] = {
126	[0] = {
127	.start = REALVIEW_ETH_BASE,
128	.end = REALVIEW_ETH_BASE + SZ_64K - 1,
129	.flags = IORESOURCE_MEM,
130	},
131	[1] = {
132	.start = IRQ_ETH,
133	.end = IRQ_ETH,
134	.flags = IORESOURCE_IRQ,
135	},
136	};
137
138	struct platform_device realview_smc91x_device = {
139	.name = "smc91x",
140	.id = 0,
141	.num_resources = ARRAY_SIZE(realview_smc91x_resources),
142	.resource = realview_smc91x_resources,
143	};
144
6b65cd74 RK	145	static struct resource realview_i2c_resource = {
	146	.start = REALVIEW_I2C_BASE,
	147	.end = REALVIEW_I2C_BASE + SZ_4K - 1,
	148	.flags = IORESOURCE_MEM,
	149	};
	150
	151	struct platform_device realview_i2c_device = {
	152	.name = "versatile-i2c",
	153	.id = -1,
	154	.num_resources = 1,
	155	.resource = &realview_i2c_resource,
	156	};
	157
8ad68bbf CM	158	#define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
	159
	160	static unsigned int realview_mmc_status(struct device *dev)
	161	{
	162	struct amba_device *adev = container_of(dev, struct amba_device, dev);
	163	u32 mask;
	164
	165	if (adev->res.start == REALVIEW_MMCI0_BASE)
	166	mask = 1;
	167	else
	168	mask = 2;
	169
	170	return readl(REALVIEW_SYSMCI) & mask;
	171	}
	172
	173	struct mmc_platform_data realview_mmc0_plat_data = {
	174	.ocr_mask = MMC_VDD_32_33\|MMC_VDD_33_34,
	175	.status = realview_mmc_status,
	176	};
	177
	178	struct mmc_platform_data realview_mmc1_plat_data = {
	179	.ocr_mask = MMC_VDD_32_33\|MMC_VDD_33_34,
	180	.status = realview_mmc_status,
	181	};
	182
	183	/*
	184	* Clock handling
	185	*/
	186	static const struct icst307_params realview_oscvco_params = {
	187	.ref = 24000,
	188	.vco_max = 200000,
	189	.vd_min = 4 + 8,
	190	.vd_max = 511 + 8,
	191	.rd_min = 1 + 2,
	192	.rd_max = 127 + 2,
	193	};
	194
	195	static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
	196	{
	197	void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
f557f5e5	198	void __iomem *sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
8ad68bbf CM	199	u32 val;
	200
	201	val = readl(sys_osc) & ~0x7ffff;
	202	val \|= vco.v \| (vco.r << 9) \| (vco.s << 16);
	203
	204	writel(0xa05f, sys_lock);
	205	writel(val, sys_osc);
	206	writel(0, sys_lock);
	207	}
	208
	209	struct clk realview_clcd_clk = {
	210	.name = "CLCDCLK",
	211	.params = &realview_oscvco_params,
	212	.setvco = realview_oscvco_set,
	213	};
	214
	215	/*
	216	* CLCD support.
	217	*/
8ad68bbf CM	218	#define SYS_CLCD_NLCDIOON (1 << 2)
	219	#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
	220	#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
	221	#define SYS_CLCD_ID_MASK (0x1f << 8)
	222	#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
	223	#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
	224	#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
	225	#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
	226	#define SYS_CLCD_ID_VGA (0x1f << 8)
	227
	228	static struct clcd_panel vga = {
	229	.mode = {
	230	.name = "VGA",
	231	.refresh = 60,
	232	.xres = 640,
	233	.yres = 480,
	234	.pixclock = 39721,
	235	.left_margin = 40,
	236	.right_margin = 24,
	237	.upper_margin = 32,
	238	.lower_margin = 11,
	239	.hsync_len = 96,
	240	.vsync_len = 2,
	241	.sync = 0,
	242	.vmode = FB_VMODE_NONINTERLACED,
	243	},
	244	.width = -1,
	245	.height = -1,
	246	.tim2 = TIM2_BCD \| TIM2_IPC,
	247	.cntl = CNTL_LCDTFT \| CNTL_LCDVCOMP(1),
	248	.bpp = 16,
	249	};
	250
	251	static struct clcd_panel sanyo_3_8_in = {
	252	.mode = {
	253	.name = "Sanyo QVGA",
	254	.refresh = 116,
	255	.xres = 320,
	256	.yres = 240,
	257	.pixclock = 100000,
	258	.left_margin = 6,
	259	.right_margin = 6,
	260	.upper_margin = 5,
	261	.lower_margin = 5,
	262	.hsync_len = 6,
	263	.vsync_len = 6,
	264	.sync = 0,
	265	.vmode = FB_VMODE_NONINTERLACED,
	266	},
	267	.width = -1,
	268	.height = -1,
	269	.tim2 = TIM2_BCD,
	270	.cntl = CNTL_LCDTFT \| CNTL_LCDVCOMP(1),
	271	.bpp = 16,
	272	};
	273
	274	static struct clcd_panel sanyo_2_5_in = {
	275	.mode = {
	276	.name = "Sanyo QVGA Portrait",
	277	.refresh = 116,
	278	.xres = 240,
	279	.yres = 320,
	280	.pixclock = 100000,
	281	.left_margin = 20,
282	.right_margin = 10,
283	.upper_margin = 2,
284	.lower_margin = 2,
285	.hsync_len = 10,
286	.vsync_len = 2,
287	.sync = FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
288	.vmode = FB_VMODE_NONINTERLACED,
289	},
290	.width = -1,
291	.height = -1,
292	.tim2 = TIM2_IVS \| TIM2_IHS \| TIM2_IPC,
293	.cntl = CNTL_LCDTFT \| CNTL_LCDVCOMP(1),
294	.bpp = 16,
295	};
296
297	static struct clcd_panel epson_2_2_in = {
298	.mode = {
299	.name = "Epson QCIF",
300	.refresh = 390,
301	.xres = 176,
302	.yres = 220,
303	.pixclock = 62500,
304	.left_margin = 3,
305	.right_margin = 2,
306	.upper_margin = 1,
307	.lower_margin = 0,
308	.hsync_len = 3,
309	.vsync_len = 2,
310	.sync = 0,
311	.vmode = FB_VMODE_NONINTERLACED,
312	},
313	.width = -1,
314	.height = -1,
315	.tim2 = TIM2_BCD \| TIM2_IPC,
316	.cntl = CNTL_LCDTFT \| CNTL_LCDVCOMP(1),
317	.bpp = 16,
318	};
319
320	/*
321	* Detect which LCD panel is connected, and return the appropriate
322	* clcd_panel structure. Note: we do not have any information on
323	* the required timings for the 8.4in panel, so we presently assume
324	* VGA timings.
325	*/
326	static struct clcd_panel *realview_clcd_panel(void)
327	{
328	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
329	struct clcd_panel *panel = &vga;
330	u32 val;
331
332	val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
333	if (val == SYS_CLCD_ID_SANYO_3_8)
334	panel = &sanyo_3_8_in;
335	else if (val == SYS_CLCD_ID_SANYO_2_5)
336	panel = &sanyo_2_5_in;
337	else if (val == SYS_CLCD_ID_EPSON_2_2)
338	panel = &epson_2_2_in;
339	else if (val == SYS_CLCD_ID_VGA)
340	panel = &vga;
341	else {
342	printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
343	val);
344	panel = &vga;
345	}
346
347	return panel;
348	}
349
350	/*
351	* Disable all display connectors on the interface module.
352	*/
353	static void realview_clcd_disable(struct clcd_fb *fb)
354	{
355	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
356	u32 val;
357
358	val = readl(sys_clcd);
359	val &= ~SYS_CLCD_NLCDIOON \| SYS_CLCD_PWR3V5SWITCH;
360	writel(val, sys_clcd);
361	}
362
363	/*
364	* Enable the relevant connector on the interface module.
365	*/
366	static void realview_clcd_enable(struct clcd_fb *fb)
367	{
368	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
369	u32 val;
370
8ad68bbf	371	/*
9e7714d0	372	* Enable the PSUs
8ad68bbf	373	*/
9e7714d0	374	val = readl(sys_clcd);
8ad68bbf CM	375	val \|= SYS_CLCD_NLCDIOON \| SYS_CLCD_PWR3V5SWITCH;
	376	writel(val, sys_clcd);
	377	}
	378
	379	static unsigned long framesize = SZ_1M;
	380
	381	static int realview_clcd_setup(struct clcd_fb *fb)
	382	{
	383	dma_addr_t dma;
	384
	385	fb->panel = realview_clcd_panel();
	386
	387	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
	388	&dma, GFP_KERNEL);
	389	if (!fb->fb.screen_base) {
	390	printk(KERN_ERR "CLCD: unable to map framebuffer\n");
	391	return -ENOMEM;
	392	}
	393
	394	fb->fb.fix.smem_start = dma;
	395	fb->fb.fix.smem_len = framesize;
	396
	397	return 0;
	398	}
	399
	400	static int realview_clcd_mmap(struct clcd_fb fb, struct vm_area_struct vma)
	401	{
	402	return dma_mmap_writecombine(&fb->dev->dev, vma,
	403	fb->fb.screen_base,
	404	fb->fb.fix.smem_start,
	405	fb->fb.fix.smem_len);
	406	}
	407
	408	static void realview_clcd_remove(struct clcd_fb *fb)
	409	{
	410	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
	411	fb->fb.screen_base, fb->fb.fix.smem_start);
	412	}
	413
	414	struct clcd_board clcd_plat_data = {
	415	.name = "RealView",
	416	.check = clcdfb_check,
	417	.decode = clcdfb_decode,
	418	.disable = realview_clcd_disable,
	419	.enable = realview_clcd_enable,
	420	.setup = realview_clcd_setup,
	421	.mmap = realview_clcd_mmap,
	422	.remove = realview_clcd_remove,
	423	};
	424
	425	#ifdef CONFIG_LEDS
	426	#define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
	427
	428	void realview_leds_event(led_event_t ledevt)
	429	{
	430	unsigned long flags;
	431	u32 val;
	432
	433	local_irq_save(flags);
	434	val = readl(VA_LEDS_BASE);
	435
	436	switch (ledevt) {
	437	case led_idle_start:
	438	val = val & ~REALVIEW_SYS_LED0;
439	break;
440
441	case led_idle_end:
442	val = val \| REALVIEW_SYS_LED0;
443	break;
444
445	case led_timer:
446	val = val ^ REALVIEW_SYS_LED1;
447	break;
448
449	case led_halted:
450	val = 0;
451	break;
452
453	default:
454	break;
455	}
456
457	writel(val, VA_LEDS_BASE);
458	local_irq_restore(flags);
459	}
460	#endif /* CONFIG_LEDS */
461
462	/*
463	* Where is the timer (VA)?
464	*/
465	#define TIMER0_VA_BASE __io_address(REALVIEW_TIMER0_1_BASE)
466	#define TIMER1_VA_BASE (__io_address(REALVIEW_TIMER0_1_BASE) + 0x20)
467	#define TIMER2_VA_BASE __io_address(REALVIEW_TIMER2_3_BASE)
468	#define TIMER3_VA_BASE (__io_address(REALVIEW_TIMER2_3_BASE) + 0x20)
469
470	/*
471	* How long is the timer interval?
472	*/
473	#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
474	#if TIMER_INTERVAL >= 0x100000
475	#define TIMER_RELOAD (TIMER_INTERVAL >> 8)
476	#define TIMER_DIVISOR (TIMER_CTRL_DIV256)
477	#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
478	#elif TIMER_INTERVAL >= 0x10000
479	#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
480	#define TIMER_DIVISOR (TIMER_CTRL_DIV16)
481	#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
482	#else
483	#define TIMER_RELOAD (TIMER_INTERVAL)
484	#define TIMER_DIVISOR (TIMER_CTRL_DIV1)
485	#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
486	#endif
487
8ad68bbf CM	488	/*
	489	* IRQ handler for the timer
	490	*/
0cd61b68	491	static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
8ad68bbf	492	{
8ad68bbf CM	493	// ...clear the interrupt
	494	writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
	495
0cd61b68	496	timer_tick();
8ad68bbf	497
2a98beb6	498	#if defined(CONFIG_SMP) && !defined(CONFIG_LOCAL_TIMERS)
dbebb4cb	499	smp_send_timer();
0cd61b68	500	update_process_times(user_mode(get_irq_regs()));
dbebb4cb RK	501	#endif
dbebb4cb RK	502
8ad68bbf CM	503	return IRQ_HANDLED;
	504	}
	505
	506	static struct irqaction realview_timer_irq = {
	507	.name = "RealView Timer Tick",
b30fabad	508	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
8ad68bbf CM	509	.handler = realview_timer_interrupt,
	510	};
	511
85802afe CM	512	static cycle_t realview_get_cycles(void)
	513	{
	514	return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
	515	}
	516
	517	static struct clocksource clocksource_realview = {
	518	.name = "timer3",
	519	.rating = 200,
	520	.read = realview_get_cycles,
	521	.mask = CLOCKSOURCE_MASK(32),
	522	.shift = 20,
	523	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	524	};
	525
	526	static void __init realview_clocksource_init(void)
	527	{
	528	/* setup timer 0 as free-running clocksource */
	529	writel(0, TIMER3_VA_BASE + TIMER_CTRL);
	530	writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
	531	writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
	532	writel(TIMER_CTRL_32BIT \| TIMER_CTRL_ENABLE \| TIMER_CTRL_PERIODIC,
	533	TIMER3_VA_BASE + TIMER_CTRL);
	534
	535	clocksource_realview.mult =
	536	clocksource_khz2mult(1000, clocksource_realview.shift);
	537	clocksource_register(&clocksource_realview);
	538	}
	539
8ad68bbf CM	540	/*
	541	* Set up timer interrupt, and return the current time in seconds.
	542	*/
	543	static void __init realview_timer_init(void)
	544	{
	545	u32 val;
	546
	547	/*
	548	* set clock frequency:
	549	* REALVIEW_REFCLK is 32KHz
	550	* REALVIEW_TIMCLK is 1MHz
	551	*/
	552	val = readl(__io_address(REALVIEW_SCTL_BASE));
	553	writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) \|
	554	(REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) \|
	555	(REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) \|
	556	(REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) \| val,
	557	__io_address(REALVIEW_SCTL_BASE));
	558
	559	/*
	560	* Initialise to a known state (all timers off)
	561	*/
	562	writel(0, TIMER0_VA_BASE + TIMER_CTRL);
	563	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
	564	writel(0, TIMER2_VA_BASE + TIMER_CTRL);
	565	writel(0, TIMER3_VA_BASE + TIMER_CTRL);
	566
	567	writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
	568	writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_VALUE);
	569	writel(TIMER_DIVISOR \| TIMER_CTRL_ENABLE \| TIMER_CTRL_PERIODIC \|
	570	TIMER_CTRL_IE, TIMER0_VA_BASE + TIMER_CTRL);
	571
	572	/*
	573	* Make irqs happen for the system timer
	574	*/
	575	setup_irq(IRQ_TIMERINT0_1, &realview_timer_irq);
85802afe CM	576
85802afe CM	577	realview_clocksource_init();
8ad68bbf CM	578	}
	579
	580	struct sys_timer realview_timer = {
	581	.init = realview_timer_init,
8ad68bbf	582	};