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862184fe RK |
1 | /* |
2 | * linux/arch/arm/mach-realview/platsmp.c | |
3 | * | |
4 | * Copyright (C) 2002 ARM Ltd. | |
5 | * All Rights Reserved | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/errno.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/device.h> | |
934848da | 15 | #include <linux/jiffies.h> |
862184fe | 16 | #include <linux/smp.h> |
fced80c7 | 17 | #include <linux/io.h> |
862184fe RK |
18 | |
19 | #include <asm/cacheflush.h> | |
a09e64fb | 20 | #include <mach/hardware.h> |
7dd19e75 | 21 | #include <asm/mach-types.h> |
bc28248e | 22 | #include <asm/localtimer.h> |
dff2ab16 | 23 | #include <asm/unified.h> |
862184fe | 24 | |
a09e64fb RK |
25 | #include <mach/board-eb.h> |
26 | #include <mach/board-pb11mp.h> | |
1b504bbe | 27 | #include <mach/board-pbx.h> |
49613d4d | 28 | #include <asm/smp_scu.h> |
b7b0ba94 | 29 | |
1bbdf637 CM |
30 | #include "core.h" |
31 | ||
862184fe RK |
32 | extern void realview_secondary_startup(void); |
33 | ||
34 | /* | |
35 | * control for which core is the next to come out of the secondary | |
36 | * boot "holding pen" | |
37 | */ | |
38 | volatile int __cpuinitdata pen_release = -1; | |
39 | ||
1bbdf637 CM |
40 | static void __iomem *scu_base_addr(void) |
41 | { | |
42 | if (machine_is_realview_eb_mp()) | |
43 | return __io_address(REALVIEW_EB11MP_SCU_BASE); | |
44 | else if (machine_is_realview_pb11mp()) | |
45 | return __io_address(REALVIEW_TC11MP_SCU_BASE); | |
1b504bbe CT |
46 | else if (machine_is_realview_pbx() && |
47 | (core_tile_pbx11mp() || core_tile_pbxa9mp())) | |
48 | return __io_address(REALVIEW_PBX_TILE_SCU_BASE); | |
1bbdf637 CM |
49 | else |
50 | return (void __iomem *)0; | |
51 | } | |
52 | ||
862184fe RK |
53 | static DEFINE_SPINLOCK(boot_lock); |
54 | ||
55 | void __cpuinit platform_secondary_init(unsigned int cpu) | |
56 | { | |
08383ef2 CM |
57 | trace_hardirqs_off(); |
58 | ||
862184fe RK |
59 | /* |
60 | * if any interrupts are already enabled for the primary | |
61 | * core (e.g. timer irq), then they will not have been enabled | |
62 | * for us: do so | |
63 | */ | |
1bbdf637 | 64 | gic_cpu_init(0, gic_cpu_base_addr); |
862184fe RK |
65 | |
66 | /* | |
67 | * let the primary processor know we're out of the | |
68 | * pen, then head off into the C entry point | |
69 | */ | |
70 | pen_release = -1; | |
0e0ba769 | 71 | smp_wmb(); |
862184fe RK |
72 | |
73 | /* | |
74 | * Synchronise with the boot thread. | |
75 | */ | |
76 | spin_lock(&boot_lock); | |
77 | spin_unlock(&boot_lock); | |
78 | } | |
79 | ||
80 | int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) | |
81 | { | |
82 | unsigned long timeout; | |
83 | ||
84 | /* | |
85 | * set synchronisation state between this boot processor | |
86 | * and the secondary one | |
87 | */ | |
88 | spin_lock(&boot_lock); | |
89 | ||
90 | /* | |
91 | * The secondary processor is waiting to be released from | |
92 | * the holding pen - release it, then wait for it to flag | |
93 | * that it has been released by resetting pen_release. | |
94 | * | |
95 | * Note that "pen_release" is the hardware CPU ID, whereas | |
96 | * "cpu" is Linux's internal ID. | |
97 | */ | |
98 | pen_release = cpu; | |
99 | flush_cache_all(); | |
100 | ||
101 | /* | |
aec66ba1 RK |
102 | * Send the secondary CPU a soft interrupt, thereby causing |
103 | * the boot monitor to read the system wide flags register, | |
104 | * and branch to the address found there. | |
862184fe | 105 | */ |
ad3b6993 | 106 | smp_cross_call(cpumask_of(cpu), 1); |
862184fe RK |
107 | |
108 | timeout = jiffies + (1 * HZ); | |
109 | while (time_before(jiffies, timeout)) { | |
0e0ba769 | 110 | smp_rmb(); |
862184fe RK |
111 | if (pen_release == -1) |
112 | break; | |
113 | ||
114 | udelay(10); | |
115 | } | |
116 | ||
117 | /* | |
118 | * now the secondary core is starting up let it run its | |
119 | * calibrations, then wait for it to finish | |
120 | */ | |
121 | spin_unlock(&boot_lock); | |
122 | ||
123 | return pen_release != -1 ? -ENOSYS : 0; | |
124 | } | |
125 | ||
7bbb7940 RK |
126 | /* |
127 | * Initialise the CPU possible map early - this describes the CPUs | |
128 | * which may be present or become present in the system. | |
129 | */ | |
130 | void __init smp_init_cpus(void) | |
131 | { | |
fd778f0a RK |
132 | void __iomem *scu_base = scu_base_addr(); |
133 | unsigned int i, ncores; | |
134 | ||
135 | ncores = scu_base ? scu_get_core_count(scu_base) : 1; | |
7bbb7940 | 136 | |
862184fe | 137 | /* sanity check */ |
862184fe RK |
138 | if (ncores > NR_CPUS) { |
139 | printk(KERN_WARNING | |
140 | "Realview: no. of cores (%d) greater than configured " | |
141 | "maximum of %d - clipping\n", | |
142 | ncores, NR_CPUS); | |
143 | ncores = NR_CPUS; | |
144 | } | |
145 | ||
bbc3d14e RK |
146 | for (i = 0; i < ncores; i++) |
147 | set_cpu_possible(i, true); | |
148 | } | |
149 | ||
150 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
151 | { | |
152 | unsigned int ncores = num_possible_cpus(); | |
153 | unsigned int cpu = smp_processor_id(); | |
154 | int i; | |
155 | ||
862184fe RK |
156 | smp_store_cpu_info(cpu); |
157 | ||
158 | /* | |
159 | * are we trying to boot more cores than exist? | |
160 | */ | |
161 | if (max_cpus > ncores) | |
162 | max_cpus = ncores; | |
163 | ||
164 | /* | |
7bbb7940 RK |
165 | * Initialise the present map, which describes the set of CPUs |
166 | * actually populated at the present time. | |
862184fe | 167 | */ |
7bbb7940 | 168 | for (i = 0; i < max_cpus; i++) |
e03cdade | 169 | set_cpu_present(i, true); |
862184fe | 170 | |
b7b0ba94 | 171 | if (max_cpus > 1) { |
bc28248e RK |
172 | /* |
173 | * Enable the local timer or broadcast device for the | |
174 | * boot CPU, but only if we have more than one CPU. | |
175 | */ | |
176 | percpu_timer_setup(); | |
177 | ||
a8cbcd92 | 178 | scu_enable(scu_base_addr()); |
aec66ba1 RK |
179 | |
180 | /* | |
181 | * Write the address of secondary startup into the | |
182 | * system-wide flags register. The BootMonitor waits | |
183 | * until it receives a soft interrupt, and then the | |
184 | * secondary CPU branches to this address. | |
185 | */ | |
186 | __raw_writel(BSYM(virt_to_phys(realview_secondary_startup)), | |
187 | __io_address(REALVIEW_SYS_FLAGSSET)); | |
b7b0ba94 | 188 | } |
862184fe | 189 | } |