Commit | Line | Data |
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8ad68bbf CM |
1 | /* |
2 | * linux/arch/arm/mach-realview/realview_eb.c | |
3 | * | |
4 | * Copyright (C) 2004 ARM Limited | |
5 | * Copyright (C) 2000 Deep Blue Solutions Ltd | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
8ad68bbf | 22 | #include <linux/init.h> |
1be7228d | 23 | #include <linux/platform_device.h> |
8ad68bbf | 24 | #include <linux/sysdev.h> |
a62c80e5 | 25 | #include <linux/amba/bus.h> |
eb7fffa3 | 26 | #include <linux/amba/pl061.h> |
6ef297f8 | 27 | #include <linux/amba/mmci.h> |
fced80c7 | 28 | #include <linux/io.h> |
8ad68bbf | 29 | |
a09e64fb | 30 | #include <mach/hardware.h> |
8ad68bbf CM |
31 | #include <asm/irq.h> |
32 | #include <asm/leds.h> | |
33 | #include <asm/mach-types.h> | |
34 | #include <asm/hardware/gic.h> | |
7770bddb | 35 | #include <asm/hardware/cache-l2x0.h> |
f32f4ce2 | 36 | #include <asm/localtimer.h> |
8ad68bbf CM |
37 | |
38 | #include <asm/mach/arch.h> | |
39 | #include <asm/mach/map.h> | |
8cc4c548 | 40 | #include <asm/mach/time.h> |
8ad68bbf | 41 | |
a09e64fb RK |
42 | #include <mach/board-eb.h> |
43 | #include <mach/irqs.h> | |
8ad68bbf CM |
44 | |
45 | #include "core.h" | |
8ad68bbf CM |
46 | |
47 | static struct map_desc realview_eb_io_desc[] __initdata = { | |
1ffedce7 RK |
48 | { |
49 | .virtual = IO_ADDRESS(REALVIEW_SYS_BASE), | |
50 | .pfn = __phys_to_pfn(REALVIEW_SYS_BASE), | |
51 | .length = SZ_4K, | |
52 | .type = MT_DEVICE, | |
53 | }, { | |
073b6ff3 CM |
54 | .virtual = IO_ADDRESS(REALVIEW_EB_GIC_CPU_BASE), |
55 | .pfn = __phys_to_pfn(REALVIEW_EB_GIC_CPU_BASE), | |
1ffedce7 RK |
56 | .length = SZ_4K, |
57 | .type = MT_DEVICE, | |
58 | }, { | |
073b6ff3 CM |
59 | .virtual = IO_ADDRESS(REALVIEW_EB_GIC_DIST_BASE), |
60 | .pfn = __phys_to_pfn(REALVIEW_EB_GIC_DIST_BASE), | |
1ffedce7 RK |
61 | .length = SZ_4K, |
62 | .type = MT_DEVICE, | |
63 | }, { | |
64 | .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE), | |
65 | .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE), | |
66 | .length = SZ_4K, | |
67 | .type = MT_DEVICE, | |
68 | }, { | |
80192735 CM |
69 | .virtual = IO_ADDRESS(REALVIEW_EB_TIMER0_1_BASE), |
70 | .pfn = __phys_to_pfn(REALVIEW_EB_TIMER0_1_BASE), | |
1ffedce7 RK |
71 | .length = SZ_4K, |
72 | .type = MT_DEVICE, | |
73 | }, { | |
80192735 CM |
74 | .virtual = IO_ADDRESS(REALVIEW_EB_TIMER2_3_BASE), |
75 | .pfn = __phys_to_pfn(REALVIEW_EB_TIMER2_3_BASE), | |
1ffedce7 RK |
76 | .length = SZ_4K, |
77 | .type = MT_DEVICE, | |
78 | }, | |
8ad68bbf | 79 | #ifdef CONFIG_DEBUG_LL |
1ffedce7 | 80 | { |
9a386f06 CM |
81 | .virtual = IO_ADDRESS(REALVIEW_EB_UART0_BASE), |
82 | .pfn = __phys_to_pfn(REALVIEW_EB_UART0_BASE), | |
1ffedce7 RK |
83 | .length = SZ_4K, |
84 | .type = MT_DEVICE, | |
85 | } | |
8ad68bbf CM |
86 | #endif |
87 | }; | |
88 | ||
7dd19e75 CM |
89 | static struct map_desc realview_eb11mp_io_desc[] __initdata = { |
90 | { | |
91 | .virtual = IO_ADDRESS(REALVIEW_EB11MP_GIC_CPU_BASE), | |
92 | .pfn = __phys_to_pfn(REALVIEW_EB11MP_GIC_CPU_BASE), | |
93 | .length = SZ_4K, | |
94 | .type = MT_DEVICE, | |
95 | }, { | |
96 | .virtual = IO_ADDRESS(REALVIEW_EB11MP_GIC_DIST_BASE), | |
97 | .pfn = __phys_to_pfn(REALVIEW_EB11MP_GIC_DIST_BASE), | |
98 | .length = SZ_4K, | |
99 | .type = MT_DEVICE, | |
100 | }, { | |
101 | .virtual = IO_ADDRESS(REALVIEW_EB11MP_L220_BASE), | |
102 | .pfn = __phys_to_pfn(REALVIEW_EB11MP_L220_BASE), | |
103 | .length = SZ_8K, | |
104 | .type = MT_DEVICE, | |
105 | } | |
106 | }; | |
107 | ||
8ad68bbf CM |
108 | static void __init realview_eb_map_io(void) |
109 | { | |
110 | iotable_init(realview_eb_io_desc, ARRAY_SIZE(realview_eb_io_desc)); | |
4c3ea371 | 111 | if (core_tile_eb11mp() || core_tile_a9mp()) |
7dd19e75 | 112 | iotable_init(realview_eb11mp_io_desc, ARRAY_SIZE(realview_eb11mp_io_desc)); |
8ad68bbf CM |
113 | } |
114 | ||
eb7fffa3 RK |
115 | static struct pl061_platform_data gpio0_plat_data = { |
116 | .gpio_base = 0, | |
117 | .irq_base = -1, | |
118 | }; | |
119 | ||
120 | static struct pl061_platform_data gpio1_plat_data = { | |
121 | .gpio_base = 8, | |
122 | .irq_base = -1, | |
123 | }; | |
124 | ||
125 | static struct pl061_platform_data gpio2_plat_data = { | |
126 | .gpio_base = 16, | |
127 | .irq_base = -1, | |
128 | }; | |
129 | ||
0fc2a161 CM |
130 | /* |
131 | * RealView EB AMBA devices | |
132 | */ | |
133 | ||
134 | /* | |
135 | * These devices are connected via the core APB bridge | |
136 | */ | |
137 | #define GPIO2_IRQ { IRQ_EB_GPIO2, NO_IRQ } | |
138 | #define GPIO2_DMA { 0, 0 } | |
139 | #define GPIO3_IRQ { IRQ_EB_GPIO3, NO_IRQ } | |
140 | #define GPIO3_DMA { 0, 0 } | |
141 | ||
142 | #define AACI_IRQ { IRQ_EB_AACI, NO_IRQ } | |
143 | #define AACI_DMA { 0x80, 0x81 } | |
144 | #define MMCI0_IRQ { IRQ_EB_MMCI0A, IRQ_EB_MMCI0B } | |
145 | #define MMCI0_DMA { 0x84, 0 } | |
146 | #define KMI0_IRQ { IRQ_EB_KMI0, NO_IRQ } | |
147 | #define KMI0_DMA { 0, 0 } | |
148 | #define KMI1_IRQ { IRQ_EB_KMI1, NO_IRQ } | |
149 | #define KMI1_DMA { 0, 0 } | |
150 | ||
151 | /* | |
152 | * These devices are connected directly to the multi-layer AHB switch | |
153 | */ | |
393538e6 CM |
154 | #define EB_SMC_IRQ { NO_IRQ, NO_IRQ } |
155 | #define EB_SMC_DMA { 0, 0 } | |
0fc2a161 CM |
156 | #define MPMC_IRQ { NO_IRQ, NO_IRQ } |
157 | #define MPMC_DMA { 0, 0 } | |
393538e6 CM |
158 | #define EB_CLCD_IRQ { IRQ_EB_CLCD, NO_IRQ } |
159 | #define EB_CLCD_DMA { 0, 0 } | |
0fc2a161 CM |
160 | #define DMAC_IRQ { IRQ_EB_DMA, NO_IRQ } |
161 | #define DMAC_DMA { 0, 0 } | |
162 | ||
163 | /* | |
164 | * These devices are connected via the core APB bridge | |
165 | */ | |
166 | #define SCTL_IRQ { NO_IRQ, NO_IRQ } | |
167 | #define SCTL_DMA { 0, 0 } | |
393538e6 CM |
168 | #define EB_WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ } |
169 | #define EB_WATCHDOG_DMA { 0, 0 } | |
170 | #define EB_GPIO0_IRQ { IRQ_EB_GPIO0, NO_IRQ } | |
171 | #define EB_GPIO0_DMA { 0, 0 } | |
0fc2a161 CM |
172 | #define GPIO1_IRQ { IRQ_EB_GPIO1, NO_IRQ } |
173 | #define GPIO1_DMA { 0, 0 } | |
393538e6 CM |
174 | #define EB_RTC_IRQ { IRQ_EB_RTC, NO_IRQ } |
175 | #define EB_RTC_DMA { 0, 0 } | |
0fc2a161 CM |
176 | |
177 | /* | |
178 | * These devices are connected via the DMA APB bridge | |
179 | */ | |
180 | #define SCI_IRQ { IRQ_EB_SCI, NO_IRQ } | |
181 | #define SCI_DMA { 7, 6 } | |
9a386f06 CM |
182 | #define EB_UART0_IRQ { IRQ_EB_UART0, NO_IRQ } |
183 | #define EB_UART0_DMA { 15, 14 } | |
184 | #define EB_UART1_IRQ { IRQ_EB_UART1, NO_IRQ } | |
185 | #define EB_UART1_DMA { 13, 12 } | |
186 | #define EB_UART2_IRQ { IRQ_EB_UART2, NO_IRQ } | |
187 | #define EB_UART2_DMA { 11, 10 } | |
188 | #define EB_UART3_IRQ { IRQ_EB_UART3, NO_IRQ } | |
189 | #define EB_UART3_DMA { 0x86, 0x87 } | |
393538e6 CM |
190 | #define EB_SSP_IRQ { IRQ_EB_SSP, NO_IRQ } |
191 | #define EB_SSP_DMA { 9, 8 } | |
0fc2a161 | 192 | |
8ad68bbf | 193 | /* FPGA Primecells */ |
4321532c LW |
194 | AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL); |
195 | AMBA_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data); | |
196 | AMBA_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL); | |
197 | AMBA_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL); | |
198 | AMBA_DEVICE(uart3, "fpga:uart3", EB_UART3, NULL); | |
8ad68bbf CM |
199 | |
200 | /* DevChip Primecells */ | |
4321532c LW |
201 | AMBA_DEVICE(smc, "dev:smc", EB_SMC, NULL); |
202 | AMBA_DEVICE(clcd, "dev:clcd", EB_CLCD, &clcd_plat_data); | |
203 | AMBA_DEVICE(dmac, "dev:dmac", DMAC, NULL); | |
204 | AMBA_DEVICE(sctl, "dev:sctl", SCTL, NULL); | |
205 | AMBA_DEVICE(wdog, "dev:wdog", EB_WATCHDOG, NULL); | |
206 | AMBA_DEVICE(gpio0, "dev:gpio0", EB_GPIO0, &gpio0_plat_data); | |
207 | AMBA_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data); | |
208 | AMBA_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data); | |
209 | AMBA_DEVICE(rtc, "dev:rtc", EB_RTC, NULL); | |
210 | AMBA_DEVICE(sci0, "dev:sci0", SCI, NULL); | |
211 | AMBA_DEVICE(uart0, "dev:uart0", EB_UART0, NULL); | |
212 | AMBA_DEVICE(uart1, "dev:uart1", EB_UART1, NULL); | |
213 | AMBA_DEVICE(uart2, "dev:uart2", EB_UART2, NULL); | |
214 | AMBA_DEVICE(ssp0, "dev:ssp0", EB_SSP, NULL); | |
8ad68bbf CM |
215 | |
216 | static struct amba_device *amba_devs[] __initdata = { | |
217 | &dmac_device, | |
218 | &uart0_device, | |
219 | &uart1_device, | |
220 | &uart2_device, | |
221 | &uart3_device, | |
222 | &smc_device, | |
223 | &clcd_device, | |
224 | &sctl_device, | |
225 | &wdog_device, | |
226 | &gpio0_device, | |
227 | &gpio1_device, | |
228 | &gpio2_device, | |
229 | &rtc_device, | |
230 | &sci0_device, | |
231 | &ssp0_device, | |
232 | &aaci_device, | |
233 | &mmc0_device, | |
234 | &kmi0_device, | |
235 | &kmi1_device, | |
236 | }; | |
237 | ||
0fc2a161 CM |
238 | /* |
239 | * RealView EB platform devices | |
240 | */ | |
a44ddfd5 CM |
241 | static struct resource realview_eb_flash_resource = { |
242 | .start = REALVIEW_EB_FLASH_BASE, | |
243 | .end = REALVIEW_EB_FLASH_BASE + REALVIEW_EB_FLASH_SIZE - 1, | |
244 | .flags = IORESOURCE_MEM, | |
245 | }; | |
0fc2a161 | 246 | |
be4f3c86 | 247 | static struct resource realview_eb_eth_resources[] = { |
0fc2a161 | 248 | [0] = { |
393538e6 CM |
249 | .start = REALVIEW_EB_ETH_BASE, |
250 | .end = REALVIEW_EB_ETH_BASE + SZ_64K - 1, | |
0fc2a161 CM |
251 | .flags = IORESOURCE_MEM, |
252 | }, | |
253 | [1] = { | |
254 | .start = IRQ_EB_ETH, | |
255 | .end = IRQ_EB_ETH, | |
256 | .flags = IORESOURCE_IRQ, | |
257 | }, | |
258 | }; | |
259 | ||
be4f3c86 CM |
260 | /* |
261 | * Detect and register the correct Ethernet device. RealView/EB rev D | |
262 | * platforms use the newer SMSC LAN9118 Ethernet chip | |
263 | */ | |
264 | static int eth_device_register(void) | |
265 | { | |
393538e6 | 266 | void __iomem *eth_addr = ioremap(REALVIEW_EB_ETH_BASE, SZ_4K); |
0a381330 | 267 | const char *name = NULL; |
be4f3c86 CM |
268 | u32 idrev; |
269 | ||
270 | if (!eth_addr) | |
271 | return -ENOMEM; | |
272 | ||
273 | idrev = readl(eth_addr + 0x50); | |
0a381330 CM |
274 | if ((idrev & 0xFFFF0000) != 0x01180000) |
275 | /* SMSC LAN9118 not present, use LAN91C111 instead */ | |
276 | name = "smc91x"; | |
be4f3c86 CM |
277 | |
278 | iounmap(eth_addr); | |
0a381330 | 279 | return realview_eth_register(name, realview_eb_eth_resources); |
be4f3c86 CM |
280 | } |
281 | ||
7db21712 CM |
282 | static struct resource realview_eb_isp1761_resources[] = { |
283 | [0] = { | |
284 | .start = REALVIEW_EB_USB_BASE, | |
285 | .end = REALVIEW_EB_USB_BASE + SZ_128K - 1, | |
286 | .flags = IORESOURCE_MEM, | |
287 | }, | |
288 | [1] = { | |
289 | .start = IRQ_EB_USB, | |
290 | .end = IRQ_EB_USB, | |
291 | .flags = IORESOURCE_IRQ, | |
292 | }, | |
293 | }; | |
294 | ||
8ad68bbf CM |
295 | static void __init gic_init_irq(void) |
296 | { | |
4c3ea371 | 297 | if (core_tile_eb11mp() || core_tile_a9mp()) { |
7dd19e75 CM |
298 | unsigned int pldctrl; |
299 | ||
300 | /* new irq mode */ | |
301 | writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK)); | |
302 | pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1); | |
303 | pldctrl |= 0x00800000; | |
304 | writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1); | |
305 | writel(0x00000000, __io_address(REALVIEW_SYS_LOCK)); | |
306 | ||
307 | /* core tile GIC, primary */ | |
c4057f52 | 308 | gic_cpu_base_addr = __io_address(REALVIEW_EB11MP_GIC_CPU_BASE); |
7dd19e75 | 309 | gic_dist_init(0, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE), 29); |
c4057f52 | 310 | gic_cpu_init(0, gic_cpu_base_addr); |
7dd19e75 | 311 | |
41579f49 | 312 | #ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB |
7dd19e75 | 313 | /* board GIC, secondary */ |
073b6ff3 CM |
314 | gic_dist_init(1, __io_address(REALVIEW_EB_GIC_DIST_BASE), 64); |
315 | gic_cpu_init(1, __io_address(REALVIEW_EB_GIC_CPU_BASE)); | |
7dd19e75 | 316 | gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1); |
3edf22ab | 317 | #endif |
7dd19e75 CM |
318 | } else { |
319 | /* board GIC, primary */ | |
073b6ff3 CM |
320 | gic_cpu_base_addr = __io_address(REALVIEW_EB_GIC_CPU_BASE); |
321 | gic_dist_init(0, __io_address(REALVIEW_EB_GIC_DIST_BASE), 29); | |
c4057f52 | 322 | gic_cpu_init(0, gic_cpu_base_addr); |
7dd19e75 | 323 | } |
8ad68bbf CM |
324 | } |
325 | ||
0fc2a161 CM |
326 | /* |
327 | * Fix up the IRQ numbers for the RealView EB/ARM11MPCore tile | |
328 | */ | |
329 | static void realview_eb11mp_fixup(void) | |
330 | { | |
331 | /* AMBA devices */ | |
332 | dmac_device.irq[0] = IRQ_EB11MP_DMA; | |
333 | uart0_device.irq[0] = IRQ_EB11MP_UART0; | |
334 | uart1_device.irq[0] = IRQ_EB11MP_UART1; | |
335 | uart2_device.irq[0] = IRQ_EB11MP_UART2; | |
336 | uart3_device.irq[0] = IRQ_EB11MP_UART3; | |
337 | clcd_device.irq[0] = IRQ_EB11MP_CLCD; | |
338 | wdog_device.irq[0] = IRQ_EB11MP_WDOG; | |
339 | gpio0_device.irq[0] = IRQ_EB11MP_GPIO0; | |
340 | gpio1_device.irq[0] = IRQ_EB11MP_GPIO1; | |
341 | gpio2_device.irq[0] = IRQ_EB11MP_GPIO2; | |
342 | rtc_device.irq[0] = IRQ_EB11MP_RTC; | |
343 | sci0_device.irq[0] = IRQ_EB11MP_SCI; | |
344 | ssp0_device.irq[0] = IRQ_EB11MP_SSP; | |
345 | aaci_device.irq[0] = IRQ_EB11MP_AACI; | |
346 | mmc0_device.irq[0] = IRQ_EB11MP_MMCI0A; | |
347 | mmc0_device.irq[1] = IRQ_EB11MP_MMCI0B; | |
348 | kmi0_device.irq[0] = IRQ_EB11MP_KMI0; | |
349 | kmi1_device.irq[0] = IRQ_EB11MP_KMI1; | |
350 | ||
351 | /* platform devices */ | |
be4f3c86 CM |
352 | realview_eb_eth_resources[1].start = IRQ_EB11MP_ETH; |
353 | realview_eb_eth_resources[1].end = IRQ_EB11MP_ETH; | |
7db21712 CM |
354 | realview_eb_isp1761_resources[1].start = IRQ_EB11MP_USB; |
355 | realview_eb_isp1761_resources[1].end = IRQ_EB11MP_USB; | |
0fc2a161 | 356 | } |
0fc2a161 | 357 | |
8cc4c548 CM |
358 | static void __init realview_eb_timer_init(void) |
359 | { | |
360 | unsigned int timer_irq; | |
361 | ||
80192735 CM |
362 | timer0_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE); |
363 | timer1_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE) + 0x20; | |
364 | timer2_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE); | |
365 | timer3_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE) + 0x20; | |
366 | ||
4c3ea371 | 367 | if (core_tile_eb11mp() || core_tile_a9mp()) { |
39e823e3 | 368 | #ifdef CONFIG_LOCAL_TIMERS |
ebac6546 | 369 | twd_base = __io_address(REALVIEW_EB11MP_TWD_BASE); |
39e823e3 | 370 | #endif |
8cc4c548 | 371 | timer_irq = IRQ_EB11MP_TIMER0_1; |
39e823e3 | 372 | } else |
8cc4c548 CM |
373 | timer_irq = IRQ_EB_TIMER0_1; |
374 | ||
375 | realview_timer_init(timer_irq); | |
376 | } | |
377 | ||
378 | static struct sys_timer realview_eb_timer = { | |
379 | .init = realview_eb_timer_init, | |
380 | }; | |
381 | ||
4c9f8be7 CT |
382 | static void realview_eb_reset(char mode) |
383 | { | |
384 | void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL); | |
385 | void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK); | |
386 | ||
387 | /* | |
388 | * To reset, we hit the on-board reset register | |
389 | * in the system FPGA | |
390 | */ | |
391 | __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl); | |
392 | if (core_tile_eb11mp()) | |
393 | __raw_writel(0x0008, reset_ctrl); | |
394 | } | |
395 | ||
8ad68bbf CM |
396 | static void __init realview_eb_init(void) |
397 | { | |
398 | int i; | |
399 | ||
4c3ea371 | 400 | if (core_tile_eb11mp() || core_tile_a9mp()) { |
7dd19e75 CM |
401 | realview_eb11mp_fixup(); |
402 | ||
ba927951 | 403 | #ifdef CONFIG_CACHE_L2X0 |
7dd19e75 CM |
404 | /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled |
405 | * Bits: .... ...0 0111 1001 0000 .... .... .... */ | |
406 | l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff); | |
ba927951 | 407 | #endif |
7dd19e75 | 408 | } |
0fc2a161 | 409 | |
a44ddfd5 | 410 | realview_flash_register(&realview_eb_flash_resource, 1); |
6b65cd74 | 411 | platform_device_register(&realview_i2c_device); |
be4f3c86 | 412 | eth_device_register(); |
7db21712 | 413 | realview_usb_register(realview_eb_isp1761_resources); |
8ad68bbf CM |
414 | |
415 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { | |
416 | struct amba_device *d = amba_devs[i]; | |
417 | amba_device_register(d, &iomem_resource); | |
418 | } | |
419 | ||
420 | #ifdef CONFIG_LEDS | |
421 | leds_event = realview_leds_event; | |
422 | #endif | |
4c9f8be7 | 423 | realview_reset = realview_eb_reset; |
8ad68bbf CM |
424 | } |
425 | ||
426 | MACHINE_START(REALVIEW_EB, "ARM-RealView EB") | |
427 | /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ | |
9a386f06 CM |
428 | .phys_io = REALVIEW_EB_UART0_BASE, |
429 | .io_pg_offst = (IO_ADDRESS(REALVIEW_EB_UART0_BASE) >> 18) & 0xfffc, | |
70bb62f8 | 430 | .boot_params = PHYS_OFFSET + 0x00000100, |
5b39d154 | 431 | .fixup = realview_fixup, |
8ad68bbf CM |
432 | .map_io = realview_eb_map_io, |
433 | .init_irq = gic_init_irq, | |
8cc4c548 | 434 | .timer = &realview_eb_timer, |
8ad68bbf CM |
435 | .init_machine = realview_eb_init, |
436 | MACHINE_END |