Commit | Line | Data |
---|---|---|
a9b67db5 BB |
1 | /* |
2 | * linux/arch/arm/mach-realview/realview_pb11mp.c | |
3 | * | |
4 | * Copyright (C) 2008 ARM Limited | |
5 | * Copyright (C) 2000 Deep Blue Solutions Ltd | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
22 | #include <linux/init.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/sysdev.h> | |
25 | #include <linux/amba/bus.h> | |
eb7fffa3 | 26 | #include <linux/amba/pl061.h> |
6ef297f8 | 27 | #include <linux/amba/mmci.h> |
d6ada860 | 28 | #include <linux/amba/pl022.h> |
fced80c7 | 29 | #include <linux/io.h> |
a9b67db5 | 30 | |
a09e64fb | 31 | #include <mach/hardware.h> |
a9b67db5 BB |
32 | #include <asm/irq.h> |
33 | #include <asm/leds.h> | |
34 | #include <asm/mach-types.h> | |
f417cbad | 35 | #include <asm/pmu.h> |
cc9897df | 36 | #include <asm/pgtable.h> |
a9b67db5 | 37 | #include <asm/hardware/gic.h> |
a9b67db5 | 38 | #include <asm/hardware/cache-l2x0.h> |
f32f4ce2 | 39 | #include <asm/localtimer.h> |
a9b67db5 BB |
40 | |
41 | #include <asm/mach/arch.h> | |
42 | #include <asm/mach/flash.h> | |
43 | #include <asm/mach/map.h> | |
a9b67db5 BB |
44 | #include <asm/mach/time.h> |
45 | ||
a09e64fb RK |
46 | #include <mach/board-pb11mp.h> |
47 | #include <mach/irqs.h> | |
a9b67db5 BB |
48 | |
49 | #include "core.h" | |
a9b67db5 BB |
50 | |
51 | static struct map_desc realview_pb11mp_io_desc[] __initdata = { | |
52 | { | |
53 | .virtual = IO_ADDRESS(REALVIEW_SYS_BASE), | |
54 | .pfn = __phys_to_pfn(REALVIEW_SYS_BASE), | |
55 | .length = SZ_4K, | |
56 | .type = MT_DEVICE, | |
57 | }, { | |
58 | .virtual = IO_ADDRESS(REALVIEW_PB11MP_GIC_CPU_BASE), | |
59 | .pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_CPU_BASE), | |
60 | .length = SZ_4K, | |
61 | .type = MT_DEVICE, | |
62 | }, { | |
63 | .virtual = IO_ADDRESS(REALVIEW_PB11MP_GIC_DIST_BASE), | |
64 | .pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_DIST_BASE), | |
65 | .length = SZ_4K, | |
66 | .type = MT_DEVICE, | |
67 | }, { | |
68 | .virtual = IO_ADDRESS(REALVIEW_TC11MP_GIC_CPU_BASE), | |
69 | .pfn = __phys_to_pfn(REALVIEW_TC11MP_GIC_CPU_BASE), | |
70 | .length = SZ_4K, | |
71 | .type = MT_DEVICE, | |
72 | }, { | |
73 | .virtual = IO_ADDRESS(REALVIEW_TC11MP_GIC_DIST_BASE), | |
74 | .pfn = __phys_to_pfn(REALVIEW_TC11MP_GIC_DIST_BASE), | |
75 | .length = SZ_4K, | |
76 | .type = MT_DEVICE, | |
77 | }, { | |
78 | .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE), | |
79 | .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE), | |
80 | .length = SZ_4K, | |
81 | .type = MT_DEVICE, | |
82 | }, { | |
83 | .virtual = IO_ADDRESS(REALVIEW_PB11MP_TIMER0_1_BASE), | |
84 | .pfn = __phys_to_pfn(REALVIEW_PB11MP_TIMER0_1_BASE), | |
85 | .length = SZ_4K, | |
86 | .type = MT_DEVICE, | |
87 | }, { | |
88 | .virtual = IO_ADDRESS(REALVIEW_PB11MP_TIMER2_3_BASE), | |
89 | .pfn = __phys_to_pfn(REALVIEW_PB11MP_TIMER2_3_BASE), | |
90 | .length = SZ_4K, | |
91 | .type = MT_DEVICE, | |
92 | }, { | |
93 | .virtual = IO_ADDRESS(REALVIEW_TC11MP_L220_BASE), | |
94 | .pfn = __phys_to_pfn(REALVIEW_TC11MP_L220_BASE), | |
95 | .length = SZ_8K, | |
96 | .type = MT_DEVICE, | |
97 | }, | |
98 | #ifdef CONFIG_DEBUG_LL | |
99 | { | |
100 | .virtual = IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE), | |
101 | .pfn = __phys_to_pfn(REALVIEW_PB11MP_UART0_BASE), | |
102 | .length = SZ_4K, | |
103 | .type = MT_DEVICE, | |
104 | }, | |
105 | #endif | |
106 | }; | |
107 | ||
108 | static void __init realview_pb11mp_map_io(void) | |
109 | { | |
110 | iotable_init(realview_pb11mp_io_desc, ARRAY_SIZE(realview_pb11mp_io_desc)); | |
111 | } | |
112 | ||
eb7fffa3 RK |
113 | static struct pl061_platform_data gpio0_plat_data = { |
114 | .gpio_base = 0, | |
115 | .irq_base = -1, | |
116 | }; | |
117 | ||
118 | static struct pl061_platform_data gpio1_plat_data = { | |
119 | .gpio_base = 8, | |
120 | .irq_base = -1, | |
121 | }; | |
122 | ||
123 | static struct pl061_platform_data gpio2_plat_data = { | |
124 | .gpio_base = 16, | |
125 | .irq_base = -1, | |
126 | }; | |
127 | ||
d6ada860 LW |
128 | static struct pl022_ssp_controller ssp0_plat_data = { |
129 | .bus_id = 0, | |
130 | .enable_dma = 0, | |
131 | .num_chipselect = 1, | |
132 | }; | |
133 | ||
a9b67db5 BB |
134 | /* |
135 | * RealView PB11MPCore AMBA devices | |
136 | */ | |
137 | ||
138 | #define GPIO2_IRQ { IRQ_PB11MP_GPIO2, NO_IRQ } | |
139 | #define GPIO2_DMA { 0, 0 } | |
140 | #define GPIO3_IRQ { IRQ_PB11MP_GPIO3, NO_IRQ } | |
141 | #define GPIO3_DMA { 0, 0 } | |
142 | #define AACI_IRQ { IRQ_TC11MP_AACI, NO_IRQ } | |
143 | #define AACI_DMA { 0x80, 0x81 } | |
144 | #define MMCI0_IRQ { IRQ_TC11MP_MMCI0A, IRQ_TC11MP_MMCI0B } | |
145 | #define MMCI0_DMA { 0x84, 0 } | |
146 | #define KMI0_IRQ { IRQ_TC11MP_KMI0, NO_IRQ } | |
147 | #define KMI0_DMA { 0, 0 } | |
148 | #define KMI1_IRQ { IRQ_TC11MP_KMI1, NO_IRQ } | |
149 | #define KMI1_DMA { 0, 0 } | |
150 | #define PB11MP_SMC_IRQ { NO_IRQ, NO_IRQ } | |
151 | #define PB11MP_SMC_DMA { 0, 0 } | |
152 | #define MPMC_IRQ { NO_IRQ, NO_IRQ } | |
153 | #define MPMC_DMA { 0, 0 } | |
154 | #define PB11MP_CLCD_IRQ { IRQ_PB11MP_CLCD, NO_IRQ } | |
155 | #define PB11MP_CLCD_DMA { 0, 0 } | |
156 | #define DMAC_IRQ { IRQ_PB11MP_DMAC, NO_IRQ } | |
157 | #define DMAC_DMA { 0, 0 } | |
158 | #define SCTL_IRQ { NO_IRQ, NO_IRQ } | |
159 | #define SCTL_DMA { 0, 0 } | |
160 | #define PB11MP_WATCHDOG_IRQ { IRQ_PB11MP_WATCHDOG, NO_IRQ } | |
161 | #define PB11MP_WATCHDOG_DMA { 0, 0 } | |
162 | #define PB11MP_GPIO0_IRQ { IRQ_PB11MP_GPIO0, NO_IRQ } | |
163 | #define PB11MP_GPIO0_DMA { 0, 0 } | |
164 | #define GPIO1_IRQ { IRQ_PB11MP_GPIO1, NO_IRQ } | |
165 | #define GPIO1_DMA { 0, 0 } | |
166 | #define PB11MP_RTC_IRQ { IRQ_TC11MP_RTC, NO_IRQ } | |
167 | #define PB11MP_RTC_DMA { 0, 0 } | |
168 | #define SCI_IRQ { IRQ_PB11MP_SCI, NO_IRQ } | |
169 | #define SCI_DMA { 7, 6 } | |
170 | #define PB11MP_UART0_IRQ { IRQ_TC11MP_UART0, NO_IRQ } | |
171 | #define PB11MP_UART0_DMA { 15, 14 } | |
172 | #define PB11MP_UART1_IRQ { IRQ_TC11MP_UART1, NO_IRQ } | |
173 | #define PB11MP_UART1_DMA { 13, 12 } | |
174 | #define PB11MP_UART2_IRQ { IRQ_PB11MP_UART2, NO_IRQ } | |
175 | #define PB11MP_UART2_DMA { 11, 10 } | |
176 | #define PB11MP_UART3_IRQ { IRQ_PB11MP_UART3, NO_IRQ } | |
177 | #define PB11MP_UART3_DMA { 0x86, 0x87 } | |
178 | #define PB11MP_SSP_IRQ { IRQ_PB11MP_SSP, NO_IRQ } | |
179 | #define PB11MP_SSP_DMA { 9, 8 } | |
180 | ||
181 | /* FPGA Primecells */ | |
4321532c LW |
182 | AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL); |
183 | AMBA_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data); | |
184 | AMBA_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL); | |
185 | AMBA_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL); | |
186 | AMBA_DEVICE(uart3, "fpga:uart3", PB11MP_UART3, NULL); | |
a9b67db5 BB |
187 | |
188 | /* DevChip Primecells */ | |
4321532c LW |
189 | AMBA_DEVICE(smc, "dev:smc", PB11MP_SMC, NULL); |
190 | AMBA_DEVICE(sctl, "dev:sctl", SCTL, NULL); | |
191 | AMBA_DEVICE(wdog, "dev:wdog", PB11MP_WATCHDOG, NULL); | |
192 | AMBA_DEVICE(gpio0, "dev:gpio0", PB11MP_GPIO0, &gpio0_plat_data); | |
193 | AMBA_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data); | |
194 | AMBA_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data); | |
195 | AMBA_DEVICE(rtc, "dev:rtc", PB11MP_RTC, NULL); | |
196 | AMBA_DEVICE(sci0, "dev:sci0", SCI, NULL); | |
197 | AMBA_DEVICE(uart0, "dev:uart0", PB11MP_UART0, NULL); | |
198 | AMBA_DEVICE(uart1, "dev:uart1", PB11MP_UART1, NULL); | |
199 | AMBA_DEVICE(uart2, "dev:uart2", PB11MP_UART2, NULL); | |
d6ada860 | 200 | AMBA_DEVICE(ssp0, "dev:ssp0", PB11MP_SSP, &ssp0_plat_data); |
a9b67db5 BB |
201 | |
202 | /* Primecells on the NEC ISSP chip */ | |
4321532c LW |
203 | AMBA_DEVICE(clcd, "issp:clcd", PB11MP_CLCD, &clcd_plat_data); |
204 | AMBA_DEVICE(dmac, "issp:dmac", DMAC, NULL); | |
a9b67db5 BB |
205 | |
206 | static struct amba_device *amba_devs[] __initdata = { | |
207 | &dmac_device, | |
208 | &uart0_device, | |
209 | &uart1_device, | |
210 | &uart2_device, | |
211 | &uart3_device, | |
212 | &smc_device, | |
213 | &clcd_device, | |
214 | &sctl_device, | |
215 | &wdog_device, | |
216 | &gpio0_device, | |
217 | &gpio1_device, | |
218 | &gpio2_device, | |
219 | &rtc_device, | |
220 | &sci0_device, | |
221 | &ssp0_device, | |
222 | &aaci_device, | |
223 | &mmc0_device, | |
224 | &kmi0_device, | |
225 | &kmi1_device, | |
226 | }; | |
227 | ||
228 | /* | |
229 | * RealView PB11MPCore platform devices | |
230 | */ | |
231 | static struct resource realview_pb11mp_flash_resource[] = { | |
232 | [0] = { | |
233 | .start = REALVIEW_PB11MP_FLASH0_BASE, | |
234 | .end = REALVIEW_PB11MP_FLASH0_BASE + REALVIEW_PB11MP_FLASH0_SIZE - 1, | |
235 | .flags = IORESOURCE_MEM, | |
236 | }, | |
237 | [1] = { | |
238 | .start = REALVIEW_PB11MP_FLASH1_BASE, | |
239 | .end = REALVIEW_PB11MP_FLASH1_BASE + REALVIEW_PB11MP_FLASH1_SIZE - 1, | |
240 | .flags = IORESOURCE_MEM, | |
241 | }, | |
242 | }; | |
243 | ||
244 | static struct resource realview_pb11mp_smsc911x_resources[] = { | |
245 | [0] = { | |
246 | .start = REALVIEW_PB11MP_ETH_BASE, | |
247 | .end = REALVIEW_PB11MP_ETH_BASE + SZ_64K - 1, | |
248 | .flags = IORESOURCE_MEM, | |
249 | }, | |
250 | [1] = { | |
251 | .start = IRQ_TC11MP_ETH, | |
252 | .end = IRQ_TC11MP_ETH, | |
253 | .flags = IORESOURCE_IRQ, | |
254 | }, | |
255 | }; | |
256 | ||
7db21712 CM |
257 | static struct resource realview_pb11mp_isp1761_resources[] = { |
258 | [0] = { | |
259 | .start = REALVIEW_PB11MP_USB_BASE, | |
260 | .end = REALVIEW_PB11MP_USB_BASE + SZ_128K - 1, | |
261 | .flags = IORESOURCE_MEM, | |
262 | }, | |
263 | [1] = { | |
264 | .start = IRQ_TC11MP_USB, | |
265 | .end = IRQ_TC11MP_USB, | |
266 | .flags = IORESOURCE_IRQ, | |
267 | }, | |
268 | }; | |
269 | ||
f417cbad WD |
270 | static struct resource pmu_resources[] = { |
271 | [0] = { | |
272 | .start = IRQ_TC11MP_PMU_CPU0, | |
273 | .end = IRQ_TC11MP_PMU_CPU0, | |
274 | .flags = IORESOURCE_IRQ, | |
275 | }, | |
276 | [1] = { | |
277 | .start = IRQ_TC11MP_PMU_CPU1, | |
278 | .end = IRQ_TC11MP_PMU_CPU1, | |
279 | .flags = IORESOURCE_IRQ, | |
280 | }, | |
281 | [2] = { | |
282 | .start = IRQ_TC11MP_PMU_CPU2, | |
283 | .end = IRQ_TC11MP_PMU_CPU2, | |
284 | .flags = IORESOURCE_IRQ, | |
285 | }, | |
286 | [3] = { | |
287 | .start = IRQ_TC11MP_PMU_CPU3, | |
288 | .end = IRQ_TC11MP_PMU_CPU3, | |
289 | .flags = IORESOURCE_IRQ, | |
290 | }, | |
291 | }; | |
292 | ||
293 | static struct platform_device pmu_device = { | |
294 | .name = "arm-pmu", | |
295 | .id = ARM_PMU_DEVICE_CPU, | |
296 | .num_resources = ARRAY_SIZE(pmu_resources), | |
297 | .resource = pmu_resources, | |
298 | }; | |
299 | ||
a9b67db5 BB |
300 | static void __init gic_init_irq(void) |
301 | { | |
302 | unsigned int pldctrl; | |
303 | ||
304 | /* new irq mode with no DCC */ | |
305 | writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK)); | |
306 | pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1); | |
307 | pldctrl |= 2 << 22; | |
308 | writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1); | |
309 | writel(0x00000000, __io_address(REALVIEW_SYS_LOCK)); | |
310 | ||
311 | /* ARM11MPCore test chip GIC, primary */ | |
312 | gic_cpu_base_addr = __io_address(REALVIEW_TC11MP_GIC_CPU_BASE); | |
313 | gic_dist_init(0, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE), 29); | |
314 | gic_cpu_init(0, gic_cpu_base_addr); | |
315 | ||
316 | /* board GIC, secondary */ | |
317 | gic_dist_init(1, __io_address(REALVIEW_PB11MP_GIC_DIST_BASE), IRQ_PB11MP_GIC_START); | |
318 | gic_cpu_init(1, __io_address(REALVIEW_PB11MP_GIC_CPU_BASE)); | |
319 | gic_cascade_irq(1, IRQ_TC11MP_PB_IRQ1); | |
320 | } | |
321 | ||
322 | static void __init realview_pb11mp_timer_init(void) | |
323 | { | |
324 | timer0_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE); | |
325 | timer1_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE) + 0x20; | |
326 | timer2_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE); | |
327 | timer3_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE) + 0x20; | |
328 | ||
329 | #ifdef CONFIG_LOCAL_TIMERS | |
ebac6546 | 330 | twd_base = __io_address(REALVIEW_TC11MP_TWD_BASE); |
a9b67db5 BB |
331 | #endif |
332 | realview_timer_init(IRQ_TC11MP_TIMER0_1); | |
333 | } | |
334 | ||
335 | static struct sys_timer realview_pb11mp_timer = { | |
336 | .init = realview_pb11mp_timer_init, | |
337 | }; | |
338 | ||
426fcd2a PJ |
339 | static void realview_pb11mp_reset(char mode) |
340 | { | |
4c9f8be7 CT |
341 | void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL); |
342 | void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK); | |
426fcd2a PJ |
343 | |
344 | /* | |
345 | * To reset, we hit the on-board reset register | |
346 | * in the system FPGA | |
347 | */ | |
4c9f8be7 CT |
348 | __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl); |
349 | __raw_writel(0x0000, reset_ctrl); | |
350 | __raw_writel(0x0004, reset_ctrl); | |
426fcd2a PJ |
351 | } |
352 | ||
a9b67db5 BB |
353 | static void __init realview_pb11mp_init(void) |
354 | { | |
355 | int i; | |
356 | ||
ba927951 | 357 | #ifdef CONFIG_CACHE_L2X0 |
a9b67db5 BB |
358 | /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled |
359 | * Bits: .... ...0 0111 1001 0000 .... .... .... */ | |
360 | l2x0_init(__io_address(REALVIEW_TC11MP_L220_BASE), 0x00790000, 0xfe000fff); | |
ba927951 | 361 | #endif |
a9b67db5 | 362 | |
a9b67db5 BB |
363 | realview_flash_register(realview_pb11mp_flash_resource, |
364 | ARRAY_SIZE(realview_pb11mp_flash_resource)); | |
0a381330 | 365 | realview_eth_register(NULL, realview_pb11mp_smsc911x_resources); |
a9b67db5 | 366 | platform_device_register(&realview_i2c_device); |
6be62ba2 | 367 | platform_device_register(&realview_cf_device); |
7db21712 | 368 | realview_usb_register(realview_pb11mp_isp1761_resources); |
f417cbad | 369 | platform_device_register(&pmu_device); |
a9b67db5 BB |
370 | |
371 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { | |
372 | struct amba_device *d = amba_devs[i]; | |
373 | amba_device_register(d, &iomem_resource); | |
374 | } | |
375 | ||
376 | #ifdef CONFIG_LEDS | |
377 | leds_event = realview_leds_event; | |
378 | #endif | |
426fcd2a | 379 | realview_reset = realview_pb11mp_reset; |
a9b67db5 BB |
380 | } |
381 | ||
382 | MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore") | |
383 | /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ | |
70bb62f8 | 384 | .boot_params = PHYS_OFFSET + 0x00000100, |
5b39d154 | 385 | .fixup = realview_fixup, |
a9b67db5 BB |
386 | .map_io = realview_pb11mp_map_io, |
387 | .init_irq = gic_init_irq, | |
388 | .timer = &realview_pb11mp_timer, | |
389 | .init_machine = realview_pb11mp_init, | |
390 | MACHINE_END |