[deliverable/linux.git] / arch / arm / mach-rockchip / platsmp.c

/*
 * Copyright (c) 2013 MundoReader S.L.
 * Author: Heiko Stuebner <heiko@sntech.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/delay.h>
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>

#include <linux/reset.h>
#include <linux/cpu.h>
#include <asm/cacheflush.h>
#include <asm/cp15.h>
#include <asm/smp_scu.h>
#include <asm/smp_plat.h>
#include <asm/mach/map.h>

#include "core.h"

static void __iomem *scu_base_addr;
static void __iomem *sram_base_addr;
static int ncores;

#define PMU_PWRDN_CON		0x08
#define PMU_PWRDN_ST		0x0c

#define PMU_PWRDN_SCU		4

static struct regmap *pmu;
static int has_pmu = true;

static int pmu_power_domain_is_on(int pd)
{
	u32 val;
	int ret;

	ret = regmap_read(pmu, PMU_PWRDN_ST, &val);
	if (ret < 0)
		return ret;

	return !(val & BIT(pd));
}

static struct reset_control *rockchip_get_core_reset(int cpu)
{
	struct device *dev = get_cpu_device(cpu);
	struct device_node *np;

	/* The cpu device is only available after the initial core bringup */
	if (dev)
		np = dev->of_node;
	else
		np = of_get_cpu_node(cpu, NULL);

	return of_reset_control_get(np, NULL);
}

static int pmu_set_power_domain(int pd, bool on)
{
	u32 val = (on) ? 0 : BIT(pd);
	struct reset_control *rstc = rockchip_get_core_reset(pd);
	int ret;

	if (IS_ERR(rstc) && read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
		pr_err("%s: could not get reset control for core %d\n",
		       __func__, pd);
		return PTR_ERR(rstc);
	}

	/*
	 * We need to soft reset the cpu when we turn off the cpu power domain,
	 * or else the active processors might be stalled when the individual
	 * processor is powered down.
	 */
	if (!IS_ERR(rstc) && !on)
		reset_control_assert(rstc);

	if (has_pmu) {
		ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
		if (ret < 0) {
			pr_err("%s: could not update power domain\n",
			       __func__);
			return ret;
		}

		ret = -1;
		while (ret != on) {
			ret = pmu_power_domain_is_on(pd);
			if (ret < 0) {
				pr_err("%s: could not read power domain state\n",
				       __func__);
				return ret;
			}
		}
	}

	if (!IS_ERR(rstc)) {
		if (on)
			reset_control_deassert(rstc);
		reset_control_put(rstc);
	}

	return 0;
}

/*
 * Handling of CPU cores
 */

static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
	int ret;

	if (!sram_base_addr || (has_pmu && !pmu)) {
		pr_err("%s: sram or pmu missing for cpu boot\n", __func__);
		return -ENXIO;
	}

	if (cpu >= ncores) {
		pr_err("%s: cpu %d outside maximum number of cpus %d\n",
		       __func__, cpu, ncores);
		return -ENXIO;
	}

	/* start the core */
	ret = pmu_set_power_domain(0 + cpu, true);
	if (ret < 0)
		return ret;

	if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
		/*
		 * We communicate with the bootrom to active the cpus other
		 * than cpu0, after a blob of initialize code, they will
		 * stay at wfe state, once they are actived, they will check
		 * the mailbox:
		 * sram_base_addr + 4: 0xdeadbeaf
		 * sram_base_addr + 8: start address for pc
		 * The cpu0 need to wait the other cpus other than cpu0 entering
		 * the wfe state.The wait time is affected by many aspects.
		 * (e.g: cpu frequency, bootrom frequency, sram frequency, ...)
		 */
		mdelay(1); /* ensure the cpus other than cpu0 to startup */

		writel(virt_to_phys(secondary_startup), sram_base_addr + 8);
		writel(0xDEADBEAF, sram_base_addr + 4);
		dsb_sev();
	}

	return 0;
}

/**
 * rockchip_smp_prepare_sram - populate necessary sram block
 * Starting cores execute the code residing at the start of the on-chip sram
 * after power-on. Therefore make sure, this sram region is reserved and
 * big enough. After this check, copy the trampoline code that directs the
 * core to the real startup code in ram into the sram-region.
 * @node: mmio-sram device node
 */
static int __init rockchip_smp_prepare_sram(struct device_node *node)
{
	unsigned int trampoline_sz = &rockchip_secondary_trampoline_end -
					    &rockchip_secondary_trampoline;
	struct resource res;
	unsigned int rsize;
	int ret;

	ret = of_address_to_resource(node, 0, &res);
	if (ret < 0) {
		pr_err("%s: could not get address for node %s\n",
		       __func__, node->full_name);
		return ret;
	}

	rsize = resource_size(&res);
	if (rsize < trampoline_sz) {
		pr_err("%s: reserved block with size 0x%x is to small for trampoline size 0x%x\n",
		       __func__, rsize, trampoline_sz);
		return -EINVAL;
	}

	/* set the boot function for the sram code */
	rockchip_boot_fn = virt_to_phys(secondary_startup);

	/* copy the trampoline to sram, that runs during startup of the core */
	memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz);
	flush_cache_all();
	outer_clean_range(0, trampoline_sz);

	dsb_sev();

	return 0;
}

static const struct regmap_config rockchip_pmu_regmap_config = {
	.reg_bits = 32,
	.val_bits = 32,
	.reg_stride = 4,
};

static int __init rockchip_smp_prepare_pmu(void)
{
	struct device_node *node;
	void __iomem *pmu_base;

	/*
	 * This function is only called via smp_ops->smp_prepare_cpu().
	 * That only happens if a "/cpus" device tree node exists
	 * and has an "enable-method" property that selects the SMP
	 * operations defined herein.
	 */
	node = of_find_node_by_path("/cpus");

	pmu = syscon_regmap_lookup_by_phandle(node, "rockchip,pmu");
	of_node_put(node);
	if (!IS_ERR(pmu))
		return 0;

	pmu = syscon_regmap_lookup_by_compatible("rockchip,rk3066-pmu");
	if (!IS_ERR(pmu))
		return 0;

	/* fallback, create our own regmap for the pmu area */
	pmu = NULL;
	node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu");
	if (!node) {
		pr_err("%s: could not find pmu dt node\n", __func__);
		return -ENODEV;
	}

	pmu_base = of_iomap(node, 0);
	if (!pmu_base) {
		pr_err("%s: could not map pmu registers\n", __func__);
		return -ENOMEM;
	}

	pmu = regmap_init_mmio(NULL, pmu_base, &rockchip_pmu_regmap_config);
	if (IS_ERR(pmu)) {
		int ret = PTR_ERR(pmu);

		iounmap(pmu_base);
		pmu = NULL;
		pr_err("%s: regmap init failed\n", __func__);
		return ret;
	}

	return 0;
}

static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
{
	struct device_node *node;
	unsigned int i;

	node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram");
	if (!node) {
		pr_err("%s: could not find sram dt node\n", __func__);
		return;
	}

	sram_base_addr = of_iomap(node, 0);
	if (!sram_base_addr) {
		pr_err("%s: could not map sram registers\n", __func__);
		return;
	}

	if (has_pmu && rockchip_smp_prepare_pmu())
		return;

	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
		if (rockchip_smp_prepare_sram(node))
			return;

		/* enable the SCU power domain */
		pmu_set_power_domain(PMU_PWRDN_SCU, true);

		node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
		if (!node) {
			pr_err("%s: missing scu\n", __func__);
			return;
		}

		scu_base_addr = of_iomap(node, 0);
		if (!scu_base_addr) {
			pr_err("%s: could not map scu registers\n", __func__);
			return;
		}

		/*
		 * While the number of cpus is gathered from dt, also get the
		 * number of cores from the scu to verify this value when
		 * booting the cores.
		 */
		ncores = scu_get_core_count(scu_base_addr);
		pr_err("%s: ncores %d\n", __func__, ncores);

		scu_enable(scu_base_addr);
	} else {
		unsigned int l2ctlr;

		asm ("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
		ncores = ((l2ctlr >> 24) & 0x3) + 1;
	}

	/* Make sure that all cores except the first are really off */
	for (i = 1; i < ncores; i++)
		pmu_set_power_domain(0 + i, false);
}

static void __init rk3036_smp_prepare_cpus(unsigned int max_cpus)
{
	has_pmu = false;

	rockchip_smp_prepare_cpus(max_cpus);
}

#ifdef CONFIG_HOTPLUG_CPU
static int rockchip_cpu_kill(unsigned int cpu)
{
	/*
	 * We need a delay here to ensure that the dying CPU can finish
	 * executing v7_coherency_exit() and reach the WFI/WFE state
	 * prior to having the power domain disabled.
	 */
	mdelay(1);

	pmu_set_power_domain(0 + cpu, false);
	return 1;
}

static void rockchip_cpu_die(unsigned int cpu)
{
	v7_exit_coherency_flush(louis);
	while (1)
		cpu_do_idle();
}
#endif

static const struct smp_operations rk3036_smp_ops __initconst = {
	.smp_prepare_cpus	= rk3036_smp_prepare_cpus,
	.smp_boot_secondary	= rockchip_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
	.cpu_kill		= rockchip_cpu_kill,
	.cpu_die		= rockchip_cpu_die,
#endif
};

static const struct smp_operations rockchip_smp_ops __initconst = {
	.smp_prepare_cpus	= rockchip_smp_prepare_cpus,
	.smp_boot_secondary	= rockchip_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
	.cpu_kill		= rockchip_cpu_kill,
	.cpu_die		= rockchip_cpu_die,
#endif
};

CPU_METHOD_OF_DECLARE(rk3036_smp, "rockchip,rk3036-smp", &rk3036_smp_ops);
CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);
Commit	Line	Data
a7a2b311 HS	1	/*
	2	* Copyright (c) 2013 MundoReader S.L.
	3	* Author: Heiko Stuebner <heiko@sntech.de>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#include <linux/delay.h>
	17	#include <linux/init.h>
	18	#include <linux/smp.h>
	19	#include <linux/io.h>
	20	#include <linux/of.h>
	21	#include <linux/of_address.h>
d003b58c HS	22	#include <linux/regmap.h>
d003b58c HS	23	#include <linux/mfd/syscon.h>
a7a2b311	24
3ee851e2 KY	25	#include <linux/reset.h>
3ee851e2 KY	26	#include <linux/cpu.h>
a7a2b311	27	#include <asm/cacheflush.h>
f54b91fd	28	#include <asm/cp15.h>
a7a2b311 HS	29	#include <asm/smp_scu.h>
	30	#include <asm/smp_plat.h>
	31	#include <asm/mach/map.h>
	32
	33	#include "core.h"
	34
	35	static void __iomem *scu_base_addr;
	36	static void __iomem *sram_base_addr;
	37	static int ncores;
	38
	39	#define PMU_PWRDN_CON 0x08
	40	#define PMU_PWRDN_ST 0x0c
	41
	42	#define PMU_PWRDN_SCU 4
	43
d003b58c	44	static struct regmap *pmu;
9def7ccf	45	static int has_pmu = true;
a7a2b311	46
d003b58c	47	static int pmu_power_domain_is_on(int pd)
a7a2b311	48	{
d003b58c HS	49	u32 val;
	50	int ret;
	51
	52	ret = regmap_read(pmu, PMU_PWRDN_ST, &val);
	53	if (ret < 0)
	54	return ret;
	55
	56	return !(val & BIT(pd));
a7a2b311 HS	57	}
a7a2b311 HS	58
bd76d738	59	static struct reset_control *rockchip_get_core_reset(int cpu)
3ee851e2 KY	60	{
	61	struct device *dev = get_cpu_device(cpu);
	62	struct device_node *np;
	63
	64	/* The cpu device is only available after the initial core bringup */
	65	if (dev)
	66	np = dev->of_node;
	67	else
26d51929	68	np = of_get_cpu_node(cpu, NULL);
3ee851e2 KY	69
	70	return of_reset_control_get(np, NULL);
	71	}
	72
d003b58c	73	static int pmu_set_power_domain(int pd, bool on)
a7a2b311	74	{
d003b58c	75	u32 val = (on) ? 0 : BIT(pd);
fe4407c0	76	struct reset_control *rstc = rockchip_get_core_reset(pd);
d003b58c HS	77	int ret;
d003b58c HS	78
fe4407c0 CW	79	if (IS_ERR(rstc) && read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
	80	pr_err("%s: could not get reset control for core %d\n",
	81	__func__, pd);
	82	return PTR_ERR(rstc);
	83	}
	84
3ee851e2 KY	85	/*
	86	* We need to soft reset the cpu when we turn off the cpu power domain,
	87	* or else the active processors might be stalled when the individual
	88	* processor is powered down.
	89	*/
fe4407c0 CW	90	if (!IS_ERR(rstc) && !on)
fe4407c0 CW	91	reset_control_assert(rstc);
3ee851e2	92
9def7ccf HS	93	if (has_pmu) {
9def7ccf HS	94	ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
d003b58c	95	if (ret < 0) {
9def7ccf	96	pr_err("%s: could not update power domain\n",
7f0b61ad	97	__func__);
d003b58c HS	98	return ret;
d003b58c HS	99	}
9def7ccf HS	100
	101	ret = -1;
	102	while (ret != on) {
	103	ret = pmu_power_domain_is_on(pd);
	104	if (ret < 0) {
	105	pr_err("%s: could not read power domain state\n",
	106	__func__);
	107	return ret;
	108	}
	109	}
d003b58c HS	110	}
d003b58c HS	111
fe4407c0 CW	112	if (!IS_ERR(rstc)) {
	113	if (on)
	114	reset_control_deassert(rstc);
	115	reset_control_put(rstc);
	116	}
	117
d003b58c	118	return 0;
a7a2b311 HS	119	}
	120
	121	/*
	122	* Handling of CPU cores
	123	*/
	124
374d4dd3	125	static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle)
a7a2b311	126	{
3ee851e2 KY	127	int ret;
3ee851e2 KY	128
9def7ccf	129	if (!sram_base_addr \|\| (has_pmu && !pmu)) {
a7a2b311 HS	130	pr_err("%s: sram or pmu missing for cpu boot\n", __func__);
	131	return -ENXIO;
	132	}
	133
	134	if (cpu >= ncores) {
	135	pr_err("%s: cpu %d outside maximum number of cpus %d\n",
7f0b61ad	136	__func__, cpu, ncores);
a7a2b311 HS	137	return -ENXIO;
	138	}
	139
	140	/* start the core */
3ee851e2 KY	141	ret = pmu_set_power_domain(0 + cpu, true);
	142	if (ret < 0)
	143	return ret;
	144
	145	if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
7f0b61ad CW	146	/*
7f0b61ad CW	147	* We communicate with the bootrom to active the cpus other
3ee851e2 KY	148	* than cpu0, after a blob of initialize code, they will
	149	* stay at wfe state, once they are actived, they will check
	150	* the mailbox:
	151	* sram_base_addr + 4: 0xdeadbeaf
	152	* sram_base_addr + 8: start address for pc
fe4407c0 CW	153	* The cpu0 need to wait the other cpus other than cpu0 entering
	154	* the wfe state.The wait time is affected by many aspects.
	155	* (e.g: cpu frequency, bootrom frequency, sram frequency, ...)
7f0b61ad	156	*/
fe4407c0 CW	157	mdelay(1); /* ensure the cpus other than cpu0 to startup */
fe4407c0 CW	158
cb8cc37f	159	writel(virt_to_phys(secondary_startup), sram_base_addr + 8);
3ee851e2 KY	160	writel(0xDEADBEAF, sram_base_addr + 4);
	161	dsb_sev();
	162	}
	163
	164	return 0;
a7a2b311 HS	165	}
	166
	167	/**
	168	* rockchip_smp_prepare_sram - populate necessary sram block
	169	* Starting cores execute the code residing at the start of the on-chip sram
	170	* after power-on. Therefore make sure, this sram region is reserved and
	171	* big enough. After this check, copy the trampoline code that directs the
	172	* core to the real startup code in ram into the sram-region.
	173	* @node: mmio-sram device node
	174	*/
	175	static int __init rockchip_smp_prepare_sram(struct device_node *node)
	176	{
	177	unsigned int trampoline_sz = &rockchip_secondary_trampoline_end -
	178	&rockchip_secondary_trampoline;
	179	struct resource res;
	180	unsigned int rsize;
	181	int ret;
	182
	183	ret = of_address_to_resource(node, 0, &res);
	184	if (ret < 0) {
	185	pr_err("%s: could not get address for node %s\n",
	186	__func__, node->full_name);
	187	return ret;
	188	}
	189
	190	rsize = resource_size(&res);
	191	if (rsize < trampoline_sz) {
	192	pr_err("%s: reserved block with size 0x%x is to small for trampoline size 0x%x\n",
	193	__func__, rsize, trampoline_sz);
	194	return -EINVAL;
	195	}
	196
a7a2b311	197	/* set the boot function for the sram code */
02b4e275	198	rockchip_boot_fn = virt_to_phys(secondary_startup);
a7a2b311 HS	199
	200	/* copy the trampoline to sram, that runs during startup of the core */
	201	memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz);
	202	flush_cache_all();
	203	outer_clean_range(0, trampoline_sz);
	204
	205	dsb_sev();
	206
	207	return 0;
	208	}
	209
bd76d738	210	static const struct regmap_config rockchip_pmu_regmap_config = {
d003b58c HS	211	.reg_bits = 32,
	212	.val_bits = 32,
	213	.reg_stride = 4,
	214	};
	215
	216	static int __init rockchip_smp_prepare_pmu(void)
	217	{
	218	struct device_node *node;
	219	void __iomem *pmu_base;
	220
6de2d21a HS	221	/*
	222	* This function is only called via smp_ops->smp_prepare_cpu().
	223	* That only happens if a "/cpus" device tree node exists
	224	* and has an "enable-method" property that selects the SMP
	225	* operations defined herein.
	226	*/
	227	node = of_find_node_by_path("/cpus");
	228
	229	pmu = syscon_regmap_lookup_by_phandle(node, "rockchip,pmu");
	230	of_node_put(node);
	231	if (!IS_ERR(pmu))
	232	return 0;
	233
d003b58c HS	234	pmu = syscon_regmap_lookup_by_compatible("rockchip,rk3066-pmu");
	235	if (!IS_ERR(pmu))
	236	return 0;
	237
	238	/* fallback, create our own regmap for the pmu area */
	239	pmu = NULL;
	240	node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu");
	241	if (!node) {
	242	pr_err("%s: could not find pmu dt node\n", __func__);
	243	return -ENODEV;
	244	}
	245
	246	pmu_base = of_iomap(node, 0);
	247	if (!pmu_base) {
	248	pr_err("%s: could not map pmu registers\n", __func__);
	249	return -ENOMEM;
	250	}
	251
	252	pmu = regmap_init_mmio(NULL, pmu_base, &rockchip_pmu_regmap_config);
	253	if (IS_ERR(pmu)) {
	254	int ret = PTR_ERR(pmu);
	255
	256	iounmap(pmu_base);
	257	pmu = NULL;
	258	pr_err("%s: regmap init failed\n", __func__);
	259	return ret;
	260	}
	261
	262	return 0;
	263	}
	264
a7a2b311 HS	265	static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
	266	{
	267	struct device_node *node;
	268	unsigned int i;
	269
a7a2b311 HS	270	node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram");
	271	if (!node) {
	272	pr_err("%s: could not find sram dt node\n", __func__);
	273	return;
	274	}
	275
3ee851e2 KY	276	sram_base_addr = of_iomap(node, 0);
	277	if (!sram_base_addr) {
	278	pr_err("%s: could not map sram registers\n", __func__);
a7a2b311	279	return;
3ee851e2	280	}
a7a2b311	281
9def7ccf	282	if (has_pmu && rockchip_smp_prepare_pmu())
a7a2b311	283	return;
a7a2b311	284
3ee851e2 KY	285	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
	286	if (rockchip_smp_prepare_sram(node))
	287	return;
a7a2b311	288
3ee851e2 KY	289	/* enable the SCU power domain */
	290	pmu_set_power_domain(PMU_PWRDN_SCU, true);
	291
	292	node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
	293	if (!node) {
	294	pr_err("%s: missing scu\n", __func__);
	295	return;
	296	}
a7a2b311	297
3ee851e2 KY	298	scu_base_addr = of_iomap(node, 0);
	299	if (!scu_base_addr) {
	300	pr_err("%s: could not map scu registers\n", __func__);
	301	return;
	302	}
	303
	304	/*
	305	* While the number of cpus is gathered from dt, also get the
	306	* number of cores from the scu to verify this value when
	307	* booting the cores.
	308	*/
	309	ncores = scu_get_core_count(scu_base_addr);
	310	pr_err("%s: ncores %d\n", __func__, ncores);
	311
	312	scu_enable(scu_base_addr);
	313	} else {
	314	unsigned int l2ctlr;
	315
	316	asm ("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
	317	ncores = ((l2ctlr >> 24) & 0x3) + 1;
	318	}
a7a2b311 HS	319
	320	/* Make sure that all cores except the first are really off */
	321	for (i = 1; i < ncores; i++)
	322	pmu_set_power_domain(0 + i, false);
	323	}
	324
9def7ccf HS	325	static void __init rk3036_smp_prepare_cpus(unsigned int max_cpus)
	326	{
	327	has_pmu = false;
	328
	329	rockchip_smp_prepare_cpus(max_cpus);
	330	}
	331
f54b91fd RP	332	#ifdef CONFIG_HOTPLUG_CPU
	333	static int rockchip_cpu_kill(unsigned int cpu)
	334	{
e306bc16 CW	335	/*
	336	* We need a delay here to ensure that the dying CPU can finish
	337	* executing v7_coherency_exit() and reach the WFI/WFE state
	338	* prior to having the power domain disabled.
	339	*/
	340	mdelay(1);
	341
f54b91fd RP	342	pmu_set_power_domain(0 + cpu, false);
	343	return 1;
	344	}
	345
	346	static void rockchip_cpu_die(unsigned int cpu)
	347	{
	348	v7_exit_coherency_flush(louis);
7f0b61ad	349	while (1)
f54b91fd RP	350	cpu_do_idle();
	351	}
	352	#endif
	353
26dc88fb	354	static const struct smp_operations rk3036_smp_ops __initconst = {
9def7ccf HS	355	.smp_prepare_cpus = rk3036_smp_prepare_cpus,
	356	.smp_boot_secondary = rockchip_boot_secondary,
	357	#ifdef CONFIG_HOTPLUG_CPU
	358	.cpu_kill = rockchip_cpu_kill,
	359	.cpu_die = rockchip_cpu_die,
	360	#endif
	361	};
	362
75305275	363	static const struct smp_operations rockchip_smp_ops __initconst = {
a7a2b311 HS	364	.smp_prepare_cpus = rockchip_smp_prepare_cpus,
a7a2b311 HS	365	.smp_boot_secondary = rockchip_boot_secondary,
f54b91fd RP	366	#ifdef CONFIG_HOTPLUG_CPU
	367	.cpu_kill = rockchip_cpu_kill,
	368	.cpu_die = rockchip_cpu_die,
	369	#endif
a7a2b311	370	};
7f0b61ad	371
9def7ccf	372	CPU_METHOD_OF_DECLARE(rk3036_smp, "rockchip,rk3036-smp", &rk3036_smp_ops);
26ab69cb	373	CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);