[deliverable/linux.git] / arch / arm / mach-rockchip / platsmp.c

/*
 * Copyright (c) 2013 MundoReader S.L.
 * Author: Heiko Stuebner <heiko@sntech.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/delay.h>
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>

#include <linux/reset.h>
#include <linux/cpu.h>
#include <asm/cacheflush.h>
#include <asm/cp15.h>
#include <asm/smp_scu.h>
#include <asm/smp_plat.h>
#include <asm/mach/map.h>

#include "core.h"

static void __iomem *scu_base_addr;
static void __iomem *sram_base_addr;
static int ncores;

#define PMU_PWRDN_CON		0x08
#define PMU_PWRDN_ST		0x0c

#define PMU_PWRDN_SCU		4

static struct regmap *pmu;

static int pmu_power_domain_is_on(int pd)
{
	u32 val;
	int ret;

	ret = regmap_read(pmu, PMU_PWRDN_ST, &val);
	if (ret < 0)
		return ret;

	return !(val & BIT(pd));
}

static struct reset_control *rockchip_get_core_reset(int cpu)
{
	struct device *dev = get_cpu_device(cpu);
	struct device_node *np;

	/* The cpu device is only available after the initial core bringup */
	if (dev)
		np = dev->of_node;
	else
		np = of_get_cpu_node(cpu, 0);

	return of_reset_control_get(np, NULL);
}

static int pmu_set_power_domain(int pd, bool on)
{
	u32 val = (on) ? 0 : BIT(pd);
	struct reset_control *rstc = rockchip_get_core_reset(pd);
	int ret;

	if (IS_ERR(rstc) && read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
		pr_err("%s: could not get reset control for core %d\n",
		       __func__, pd);
		return PTR_ERR(rstc);
	}

	/*
	 * We need to soft reset the cpu when we turn off the cpu power domain,
	 * or else the active processors might be stalled when the individual
	 * processor is powered down.
	 */
	if (!IS_ERR(rstc) && !on)
		reset_control_assert(rstc);

	ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
	if (ret < 0) {
		pr_err("%s: could not update power domain\n", __func__);
		return ret;
	}

	ret = -1;
	while (ret != on) {
		ret = pmu_power_domain_is_on(pd);
		if (ret < 0) {
			pr_err("%s: could not read power domain state\n",
			       __func__);
			return ret;
		}
	}

	if (!IS_ERR(rstc)) {
		if (on)
			reset_control_deassert(rstc);
		reset_control_put(rstc);
	}

	return 0;
}

/*
 * Handling of CPU cores
 */

static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
	int ret;

	if (!sram_base_addr || !pmu) {
		pr_err("%s: sram or pmu missing for cpu boot\n", __func__);
		return -ENXIO;
	}

	if (cpu >= ncores) {
		pr_err("%s: cpu %d outside maximum number of cpus %d\n",
		       __func__, cpu, ncores);
		return -ENXIO;
	}

	/* start the core */
	ret = pmu_set_power_domain(0 + cpu, true);
	if (ret < 0)
		return ret;

	if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
		/*
		 * We communicate with the bootrom to active the cpus other
		 * than cpu0, after a blob of initialize code, they will
		 * stay at wfe state, once they are actived, they will check
		 * the mailbox:
		 * sram_base_addr + 4: 0xdeadbeaf
		 * sram_base_addr + 8: start address for pc
		 * The cpu0 need to wait the other cpus other than cpu0 entering
		 * the wfe state.The wait time is affected by many aspects.
		 * (e.g: cpu frequency, bootrom frequency, sram frequency, ...)
		 */
		mdelay(1); /* ensure the cpus other than cpu0 to startup */

		writel(virt_to_phys(rockchip_secondary_startup),
		       sram_base_addr + 8);
		writel(0xDEADBEAF, sram_base_addr + 4);
		dsb_sev();
	}

	return 0;
}

/**
 * rockchip_smp_prepare_sram - populate necessary sram block
 * Starting cores execute the code residing at the start of the on-chip sram
 * after power-on. Therefore make sure, this sram region is reserved and
 * big enough. After this check, copy the trampoline code that directs the
 * core to the real startup code in ram into the sram-region.
 * @node: mmio-sram device node
 */
static int __init rockchip_smp_prepare_sram(struct device_node *node)
{
	unsigned int trampoline_sz = &rockchip_secondary_trampoline_end -
					    &rockchip_secondary_trampoline;
	struct resource res;
	unsigned int rsize;
	int ret;

	ret = of_address_to_resource(node, 0, &res);
	if (ret < 0) {
		pr_err("%s: could not get address for node %s\n",
		       __func__, node->full_name);
		return ret;
	}

	rsize = resource_size(&res);
	if (rsize < trampoline_sz) {
		pr_err("%s: reserved block with size 0x%x is to small for trampoline size 0x%x\n",
		       __func__, rsize, trampoline_sz);
		return -EINVAL;
	}

	/* set the boot function for the sram code */
	rockchip_boot_fn = virt_to_phys(secondary_startup);

	/* copy the trampoline to sram, that runs during startup of the core */
	memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz);
	flush_cache_all();
	outer_clean_range(0, trampoline_sz);

	dsb_sev();

	return 0;
}

static const struct regmap_config rockchip_pmu_regmap_config = {
	.reg_bits = 32,
	.val_bits = 32,
	.reg_stride = 4,
};

static int __init rockchip_smp_prepare_pmu(void)
{
	struct device_node *node;
	void __iomem *pmu_base;

	/*
	 * This function is only called via smp_ops->smp_prepare_cpu().
	 * That only happens if a "/cpus" device tree node exists
	 * and has an "enable-method" property that selects the SMP
	 * operations defined herein.
	 */
	node = of_find_node_by_path("/cpus");

	pmu = syscon_regmap_lookup_by_phandle(node, "rockchip,pmu");
	of_node_put(node);
	if (!IS_ERR(pmu))
		return 0;

	pmu = syscon_regmap_lookup_by_compatible("rockchip,rk3066-pmu");
	if (!IS_ERR(pmu))
		return 0;

	/* fallback, create our own regmap for the pmu area */
	pmu = NULL;
	node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu");
	if (!node) {
		pr_err("%s: could not find pmu dt node\n", __func__);
		return -ENODEV;
	}

	pmu_base = of_iomap(node, 0);
	if (!pmu_base) {
		pr_err("%s: could not map pmu registers\n", __func__);
		return -ENOMEM;
	}

	pmu = regmap_init_mmio(NULL, pmu_base, &rockchip_pmu_regmap_config);
	if (IS_ERR(pmu)) {
		int ret = PTR_ERR(pmu);

		iounmap(pmu_base);
		pmu = NULL;
		pr_err("%s: regmap init failed\n", __func__);
		return ret;
	}

	return 0;
}

static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
{
	struct device_node *node;
	unsigned int i;

	node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram");
	if (!node) {
		pr_err("%s: could not find sram dt node\n", __func__);
		return;
	}

	sram_base_addr = of_iomap(node, 0);
	if (!sram_base_addr) {
		pr_err("%s: could not map sram registers\n", __func__);
		return;
	}

	if (rockchip_smp_prepare_pmu())
		return;

	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
		if (rockchip_smp_prepare_sram(node))
			return;

		/* enable the SCU power domain */
		pmu_set_power_domain(PMU_PWRDN_SCU, true);

		node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
		if (!node) {
			pr_err("%s: missing scu\n", __func__);
			return;
		}

		scu_base_addr = of_iomap(node, 0);
		if (!scu_base_addr) {
			pr_err("%s: could not map scu registers\n", __func__);
			return;
		}

		/*
		 * While the number of cpus is gathered from dt, also get the
		 * number of cores from the scu to verify this value when
		 * booting the cores.
		 */
		ncores = scu_get_core_count(scu_base_addr);
		pr_err("%s: ncores %d\n", __func__, ncores);

		scu_enable(scu_base_addr);
	} else {
		unsigned int l2ctlr;

		asm ("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
		ncores = ((l2ctlr >> 24) & 0x3) + 1;
	}

	/* Make sure that all cores except the first are really off */
	for (i = 1; i < ncores; i++)
		pmu_set_power_domain(0 + i, false);
}

#ifdef CONFIG_HOTPLUG_CPU
static int rockchip_cpu_kill(unsigned int cpu)
{
	/*
	 * We need a delay here to ensure that the dying CPU can finish
	 * executing v7_coherency_exit() and reach the WFI/WFE state
	 * prior to having the power domain disabled.
	 */
	mdelay(1);

	pmu_set_power_domain(0 + cpu, false);
	return 1;
}

static void rockchip_cpu_die(unsigned int cpu)
{
	v7_exit_coherency_flush(louis);
	while (1)
		cpu_do_idle();
}
#endif

static struct smp_operations rockchip_smp_ops __initdata = {
	.smp_prepare_cpus	= rockchip_smp_prepare_cpus,
	.smp_boot_secondary	= rockchip_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
	.cpu_kill		= rockchip_cpu_kill,
	.cpu_die		= rockchip_cpu_die,
#endif
};

CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);
Commit	Line	Data
a7a2b311 HS	1	/*
	2	* Copyright (c) 2013 MundoReader S.L.
	3	* Author: Heiko Stuebner <heiko@sntech.de>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#include <linux/delay.h>
	17	#include <linux/init.h>
	18	#include <linux/smp.h>
	19	#include <linux/io.h>
	20	#include <linux/of.h>
	21	#include <linux/of_address.h>
d003b58c HS	22	#include <linux/regmap.h>
d003b58c HS	23	#include <linux/mfd/syscon.h>
a7a2b311	24
3ee851e2 KY	25	#include <linux/reset.h>
3ee851e2 KY	26	#include <linux/cpu.h>
a7a2b311	27	#include <asm/cacheflush.h>
f54b91fd	28	#include <asm/cp15.h>
a7a2b311 HS	29	#include <asm/smp_scu.h>
	30	#include <asm/smp_plat.h>
	31	#include <asm/mach/map.h>
	32
	33	#include "core.h"
	34
	35	static void __iomem *scu_base_addr;
	36	static void __iomem *sram_base_addr;
	37	static int ncores;
	38
	39	#define PMU_PWRDN_CON 0x08
	40	#define PMU_PWRDN_ST 0x0c
	41
	42	#define PMU_PWRDN_SCU 4
	43
d003b58c	44	static struct regmap *pmu;
a7a2b311	45
d003b58c	46	static int pmu_power_domain_is_on(int pd)
a7a2b311	47	{
d003b58c HS	48	u32 val;
	49	int ret;
	50
	51	ret = regmap_read(pmu, PMU_PWRDN_ST, &val);
	52	if (ret < 0)
	53	return ret;
	54
	55	return !(val & BIT(pd));
a7a2b311 HS	56	}
a7a2b311 HS	57
bd76d738	58	static struct reset_control *rockchip_get_core_reset(int cpu)
3ee851e2 KY	59	{
	60	struct device *dev = get_cpu_device(cpu);
	61	struct device_node *np;
	62
	63	/* The cpu device is only available after the initial core bringup */
	64	if (dev)
	65	np = dev->of_node;
	66	else
	67	np = of_get_cpu_node(cpu, 0);
	68
	69	return of_reset_control_get(np, NULL);
	70	}
	71
d003b58c	72	static int pmu_set_power_domain(int pd, bool on)
a7a2b311	73	{
d003b58c	74	u32 val = (on) ? 0 : BIT(pd);
fe4407c0	75	struct reset_control *rstc = rockchip_get_core_reset(pd);
d003b58c HS	76	int ret;
d003b58c HS	77
fe4407c0 CW	78	if (IS_ERR(rstc) && read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
	79	pr_err("%s: could not get reset control for core %d\n",
	80	__func__, pd);
	81	return PTR_ERR(rstc);
	82	}
	83
3ee851e2 KY	84	/*
	85	* We need to soft reset the cpu when we turn off the cpu power domain,
	86	* or else the active processors might be stalled when the individual
	87	* processor is powered down.
	88	*/
fe4407c0 CW	89	if (!IS_ERR(rstc) && !on)
fe4407c0 CW	90	reset_control_assert(rstc);
3ee851e2	91
d003b58c HS	92	ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
	93	if (ret < 0) {
	94	pr_err("%s: could not update power domain\n", __func__);
	95	return ret;
	96	}
	97
	98	ret = -1;
	99	while (ret != on) {
	100	ret = pmu_power_domain_is_on(pd);
	101	if (ret < 0) {
	102	pr_err("%s: could not read power domain state\n",
7f0b61ad	103	__func__);
d003b58c HS	104	return ret;
	105	}
	106	}
	107
fe4407c0 CW	108	if (!IS_ERR(rstc)) {
	109	if (on)
	110	reset_control_deassert(rstc);
	111	reset_control_put(rstc);
	112	}
	113
d003b58c	114	return 0;
a7a2b311 HS	115	}
	116
	117	/*
	118	* Handling of CPU cores
	119	*/
	120
374d4dd3	121	static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle)
a7a2b311	122	{
3ee851e2 KY	123	int ret;
3ee851e2 KY	124
d003b58c	125	if (!sram_base_addr \|\| !pmu) {
a7a2b311 HS	126	pr_err("%s: sram or pmu missing for cpu boot\n", __func__);
	127	return -ENXIO;
	128	}
	129
	130	if (cpu >= ncores) {
	131	pr_err("%s: cpu %d outside maximum number of cpus %d\n",
7f0b61ad	132	__func__, cpu, ncores);
a7a2b311 HS	133	return -ENXIO;
	134	}
	135
	136	/* start the core */
3ee851e2 KY	137	ret = pmu_set_power_domain(0 + cpu, true);
	138	if (ret < 0)
	139	return ret;
	140
	141	if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
7f0b61ad CW	142	/*
7f0b61ad CW	143	* We communicate with the bootrom to active the cpus other
3ee851e2 KY	144	* than cpu0, after a blob of initialize code, they will
	145	* stay at wfe state, once they are actived, they will check
	146	* the mailbox:
	147	* sram_base_addr + 4: 0xdeadbeaf
	148	* sram_base_addr + 8: start address for pc
fe4407c0 CW	149	* The cpu0 need to wait the other cpus other than cpu0 entering
	150	* the wfe state.The wait time is affected by many aspects.
	151	* (e.g: cpu frequency, bootrom frequency, sram frequency, ...)
7f0b61ad	152	*/
fe4407c0 CW	153	mdelay(1); /* ensure the cpus other than cpu0 to startup */
	154
	155	writel(virt_to_phys(rockchip_secondary_startup),
7f0b61ad	156	sram_base_addr + 8);
3ee851e2 KY	157	writel(0xDEADBEAF, sram_base_addr + 4);
	158	dsb_sev();
	159	}
	160
	161	return 0;
a7a2b311 HS	162	}
	163
	164	/**
	165	* rockchip_smp_prepare_sram - populate necessary sram block
	166	* Starting cores execute the code residing at the start of the on-chip sram
	167	* after power-on. Therefore make sure, this sram region is reserved and
	168	* big enough. After this check, copy the trampoline code that directs the
	169	* core to the real startup code in ram into the sram-region.
	170	* @node: mmio-sram device node
	171	*/
	172	static int __init rockchip_smp_prepare_sram(struct device_node *node)
	173	{
	174	unsigned int trampoline_sz = &rockchip_secondary_trampoline_end -
	175	&rockchip_secondary_trampoline;
	176	struct resource res;
	177	unsigned int rsize;
	178	int ret;
	179
	180	ret = of_address_to_resource(node, 0, &res);
	181	if (ret < 0) {
	182	pr_err("%s: could not get address for node %s\n",
	183	__func__, node->full_name);
	184	return ret;
	185	}
	186
	187	rsize = resource_size(&res);
	188	if (rsize < trampoline_sz) {
	189	pr_err("%s: reserved block with size 0x%x is to small for trampoline size 0x%x\n",
	190	__func__, rsize, trampoline_sz);
	191	return -EINVAL;
	192	}
	193
a7a2b311	194	/* set the boot function for the sram code */
02b4e275	195	rockchip_boot_fn = virt_to_phys(secondary_startup);
a7a2b311 HS	196
	197	/* copy the trampoline to sram, that runs during startup of the core */
	198	memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz);
	199	flush_cache_all();
	200	outer_clean_range(0, trampoline_sz);
	201
	202	dsb_sev();
	203
	204	return 0;
	205	}
	206
bd76d738	207	static const struct regmap_config rockchip_pmu_regmap_config = {
d003b58c HS	208	.reg_bits = 32,
	209	.val_bits = 32,
	210	.reg_stride = 4,
	211	};
	212
	213	static int __init rockchip_smp_prepare_pmu(void)
	214	{
	215	struct device_node *node;
	216	void __iomem *pmu_base;
	217
6de2d21a HS	218	/*
	219	* This function is only called via smp_ops->smp_prepare_cpu().
	220	* That only happens if a "/cpus" device tree node exists
	221	* and has an "enable-method" property that selects the SMP
	222	* operations defined herein.
	223	*/
	224	node = of_find_node_by_path("/cpus");
	225
	226	pmu = syscon_regmap_lookup_by_phandle(node, "rockchip,pmu");
	227	of_node_put(node);
	228	if (!IS_ERR(pmu))
	229	return 0;
	230
d003b58c HS	231	pmu = syscon_regmap_lookup_by_compatible("rockchip,rk3066-pmu");
	232	if (!IS_ERR(pmu))
	233	return 0;
	234
	235	/* fallback, create our own regmap for the pmu area */
	236	pmu = NULL;
	237	node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu");
	238	if (!node) {
	239	pr_err("%s: could not find pmu dt node\n", __func__);
	240	return -ENODEV;
	241	}
	242
	243	pmu_base = of_iomap(node, 0);
	244	if (!pmu_base) {
	245	pr_err("%s: could not map pmu registers\n", __func__);
	246	return -ENOMEM;
	247	}
	248
	249	pmu = regmap_init_mmio(NULL, pmu_base, &rockchip_pmu_regmap_config);
	250	if (IS_ERR(pmu)) {
	251	int ret = PTR_ERR(pmu);
	252
	253	iounmap(pmu_base);
	254	pmu = NULL;
	255	pr_err("%s: regmap init failed\n", __func__);
	256	return ret;
	257	}
	258
	259	return 0;
	260	}
	261
a7a2b311 HS	262	static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
	263	{
	264	struct device_node *node;
	265	unsigned int i;
	266
a7a2b311 HS	267	node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram");
	268	if (!node) {
	269	pr_err("%s: could not find sram dt node\n", __func__);
	270	return;
	271	}
	272
3ee851e2 KY	273	sram_base_addr = of_iomap(node, 0);
	274	if (!sram_base_addr) {
	275	pr_err("%s: could not map sram registers\n", __func__);
a7a2b311	276	return;
3ee851e2	277	}
a7a2b311	278
d003b58c	279	if (rockchip_smp_prepare_pmu())
a7a2b311	280	return;
a7a2b311	281
3ee851e2 KY	282	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
	283	if (rockchip_smp_prepare_sram(node))
	284	return;
a7a2b311	285
3ee851e2 KY	286	/* enable the SCU power domain */
	287	pmu_set_power_domain(PMU_PWRDN_SCU, true);
	288
	289	node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
	290	if (!node) {
	291	pr_err("%s: missing scu\n", __func__);
	292	return;
	293	}
a7a2b311	294
3ee851e2 KY	295	scu_base_addr = of_iomap(node, 0);
	296	if (!scu_base_addr) {
	297	pr_err("%s: could not map scu registers\n", __func__);
	298	return;
	299	}
	300
	301	/*
	302	* While the number of cpus is gathered from dt, also get the
	303	* number of cores from the scu to verify this value when
	304	* booting the cores.
	305	*/
	306	ncores = scu_get_core_count(scu_base_addr);
	307	pr_err("%s: ncores %d\n", __func__, ncores);
	308
	309	scu_enable(scu_base_addr);
	310	} else {
	311	unsigned int l2ctlr;
	312
	313	asm ("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
	314	ncores = ((l2ctlr >> 24) & 0x3) + 1;
	315	}
a7a2b311 HS	316
	317	/* Make sure that all cores except the first are really off */
	318	for (i = 1; i < ncores; i++)
	319	pmu_set_power_domain(0 + i, false);
	320	}
	321
f54b91fd RP	322	#ifdef CONFIG_HOTPLUG_CPU
	323	static int rockchip_cpu_kill(unsigned int cpu)
	324	{
e306bc16 CW	325	/*
	326	* We need a delay here to ensure that the dying CPU can finish
	327	* executing v7_coherency_exit() and reach the WFI/WFE state
	328	* prior to having the power domain disabled.
	329	*/
	330	mdelay(1);
	331
f54b91fd RP	332	pmu_set_power_domain(0 + cpu, false);
	333	return 1;
	334	}
	335
	336	static void rockchip_cpu_die(unsigned int cpu)
	337	{
	338	v7_exit_coherency_flush(louis);
7f0b61ad	339	while (1)
f54b91fd RP	340	cpu_do_idle();
	341	}
	342	#endif
	343
26ab69cb	344	static struct smp_operations rockchip_smp_ops __initdata = {
a7a2b311 HS	345	.smp_prepare_cpus = rockchip_smp_prepare_cpus,
a7a2b311 HS	346	.smp_boot_secondary = rockchip_boot_secondary,
f54b91fd RP	347	#ifdef CONFIG_HOTPLUG_CPU
	348	.cpu_kill = rockchip_cpu_kill,
	349	.cpu_die = rockchip_cpu_die,
	350	#endif
a7a2b311	351	};
7f0b61ad	352
26ab69cb	353	CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);