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9c1ec8e1 CZ |
1 | /* |
2 | * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd | |
3 | * Author: Tony Xie <tony.xie@rock-chips.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | */ | |
14 | ||
15 | #ifndef __MACH_ROCKCHIP_PM_H | |
16 | #define __MACH_ROCKCHIP_PM_H | |
17 | ||
18 | extern unsigned long rkpm_bootdata_cpusp; | |
19 | extern unsigned long rkpm_bootdata_cpu_code; | |
20 | extern unsigned long rkpm_bootdata_l2ctlr_f; | |
21 | extern unsigned long rkpm_bootdata_l2ctlr; | |
22 | extern unsigned long rkpm_bootdata_ddr_code; | |
23 | extern unsigned long rkpm_bootdata_ddr_data; | |
24 | extern unsigned long rk3288_bootram_sz; | |
25 | ||
26 | void rockchip_slp_cpu_resume(void); | |
27 | void __init rockchip_suspend_init(void); | |
28 | ||
29 | /****** following is rk3288 defined **********/ | |
30 | #define RK3288_PMU_WAKEUP_CFG0 0x00 | |
31 | #define RK3288_PMU_WAKEUP_CFG1 0x04 | |
32 | #define RK3288_PMU_PWRMODE_CON 0x18 | |
33 | #define RK3288_PMU_OSC_CNT 0x20 | |
34 | #define RK3288_PMU_PLL_CNT 0x24 | |
35 | #define RK3288_PMU_STABL_CNT 0x28 | |
36 | #define RK3288_PMU_DDR0IO_PWRON_CNT 0x2c | |
37 | #define RK3288_PMU_DDR1IO_PWRON_CNT 0x30 | |
38 | #define RK3288_PMU_CORE_PWRDWN_CNT 0x34 | |
39 | #define RK3288_PMU_CORE_PWRUP_CNT 0x38 | |
40 | #define RK3288_PMU_GPU_PWRDWN_CNT 0x3c | |
41 | #define RK3288_PMU_GPU_PWRUP_CNT 0x40 | |
42 | #define RK3288_PMU_WAKEUP_RST_CLR_CNT 0x44 | |
43 | #define RK3288_PMU_PWRMODE_CON1 0x90 | |
44 | ||
45 | #define RK3288_SGRF_SOC_CON0 (0x0000) | |
46 | #define RK3288_SGRF_FAST_BOOT_ADDR (0x0120) | |
47 | #define SGRF_FAST_BOOT_EN BIT(8) | |
48 | #define SGRF_FAST_BOOT_EN_WRITE BIT(24) | |
49 | ||
50 | #define RK3288_CRU_MODE_CON 0x50 | |
51 | #define RK3288_CRU_SEL0_CON 0x60 | |
52 | #define RK3288_CRU_SEL1_CON 0x64 | |
53 | #define RK3288_CRU_SEL10_CON 0x88 | |
54 | #define RK3288_CRU_SEL33_CON 0xe4 | |
55 | #define RK3288_CRU_SEL37_CON 0xf4 | |
56 | ||
57 | /* PMU_WAKEUP_CFG1 bits */ | |
58 | #define PMU_ARMINT_WAKEUP_EN BIT(0) | |
59 | ||
60 | enum rk3288_pwr_mode_con { | |
61 | PMU_PWR_MODE_EN = 0, | |
62 | PMU_CLK_CORE_SRC_GATE_EN, | |
63 | PMU_GLOBAL_INT_DISABLE, | |
64 | PMU_L2FLUSH_EN, | |
65 | PMU_BUS_PD_EN, | |
66 | PMU_A12_0_PD_EN, | |
67 | PMU_SCU_EN, | |
68 | PMU_PLL_PD_EN, | |
69 | PMU_CHIP_PD_EN, /* POWER OFF PIN ENABLE */ | |
70 | PMU_PWROFF_COMB, | |
71 | PMU_ALIVE_USE_LF, | |
72 | PMU_PMU_USE_LF, | |
73 | PMU_OSC_24M_DIS, | |
74 | PMU_INPUT_CLAMP_EN, | |
75 | PMU_WAKEUP_RESET_EN, | |
76 | PMU_SREF0_ENTER_EN, | |
77 | PMU_SREF1_ENTER_EN, | |
78 | PMU_DDR0IO_RET_EN, | |
79 | PMU_DDR1IO_RET_EN, | |
80 | PMU_DDR0_GATING_EN, | |
81 | PMU_DDR1_GATING_EN, | |
82 | PMU_DDR0IO_RET_DE_REQ, | |
83 | PMU_DDR1IO_RET_DE_REQ | |
84 | }; | |
85 | ||
86 | enum rk3288_pwr_mode_con1 { | |
87 | PMU_CLR_BUS = 0, | |
88 | PMU_CLR_CORE, | |
89 | PMU_CLR_CPUP, | |
90 | PMU_CLR_ALIVE, | |
91 | PMU_CLR_DMA, | |
92 | PMU_CLR_PERI, | |
93 | PMU_CLR_GPU, | |
94 | PMU_CLR_VIDEO, | |
95 | PMU_CLR_HEVC, | |
96 | PMU_CLR_VIO, | |
97 | }; | |
98 | ||
99 | #endif /* __MACH_ROCKCHIP_PM_H */ |