Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-rpc/dma.c | |
3 | * | |
4 | * Copyright (C) 1998 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * DMA functions specific to RiscPC architecture | |
11 | */ | |
1da177e4 LT |
12 | #include <linux/mman.h> |
13 | #include <linux/init.h> | |
14 | #include <linux/interrupt.h> | |
7cdad482 | 15 | #include <linux/dma-mapping.h> |
fced80c7 | 16 | #include <linux/io.h> |
1da177e4 LT |
17 | |
18 | #include <asm/page.h> | |
19 | #include <asm/dma.h> | |
20 | #include <asm/fiq.h> | |
1da177e4 | 21 | #include <asm/irq.h> |
a09e64fb | 22 | #include <mach/hardware.h> |
1da177e4 LT |
23 | #include <asm/uaccess.h> |
24 | ||
25 | #include <asm/mach/dma.h> | |
26 | #include <asm/hardware/iomd.h> | |
27 | ||
308d333a RK |
28 | struct iomd_dma { |
29 | struct dma_struct dma; | |
30 | unsigned int state; | |
31 | unsigned long base; /* Controller base address */ | |
32 | int irq; /* Controller IRQ */ | |
33 | struct scatterlist cur_sg; /* Current controller buffer */ | |
fa4e9989 RK |
34 | dma_addr_t dma_addr; |
35 | unsigned int dma_len; | |
308d333a RK |
36 | }; |
37 | ||
1da177e4 LT |
38 | #if 0 |
39 | typedef enum { | |
40 | dma_size_8 = 1, | |
41 | dma_size_16 = 2, | |
42 | dma_size_32 = 4, | |
43 | dma_size_128 = 16 | |
44 | } dma_size_t; | |
45 | #endif | |
46 | ||
47 | #define TRANSFER_SIZE 2 | |
48 | ||
49 | #define CURA (0) | |
50 | #define ENDA (IOMD_IO0ENDA - IOMD_IO0CURA) | |
51 | #define CURB (IOMD_IO0CURB - IOMD_IO0CURA) | |
52 | #define ENDB (IOMD_IO0ENDB - IOMD_IO0CURA) | |
53 | #define CR (IOMD_IO0CR - IOMD_IO0CURA) | |
54 | #define ST (IOMD_IO0ST - IOMD_IO0CURA) | |
55 | ||
ad9dd94c | 56 | static void iomd_get_next_sg(struct scatterlist *sg, struct iomd_dma *idma) |
1da177e4 LT |
57 | { |
58 | unsigned long end, offset, flags = 0; | |
59 | ||
ad9dd94c | 60 | if (idma->dma.sg) { |
fa4e9989 | 61 | sg->dma_address = idma->dma_addr; |
1da177e4 LT |
62 | offset = sg->dma_address & ~PAGE_MASK; |
63 | ||
fa4e9989 | 64 | end = offset + idma->dma_len; |
1da177e4 LT |
65 | |
66 | if (end > PAGE_SIZE) | |
67 | end = PAGE_SIZE; | |
68 | ||
69 | if (offset + TRANSFER_SIZE >= end) | |
70 | flags |= DMA_END_L; | |
71 | ||
72 | sg->length = end - TRANSFER_SIZE; | |
73 | ||
fa4e9989 RK |
74 | idma->dma_len -= end - offset; |
75 | idma->dma_addr += end - offset; | |
1da177e4 | 76 | |
fa4e9989 | 77 | if (idma->dma_len == 0) { |
ad9dd94c | 78 | if (idma->dma.sgcount > 1) { |
9e28d7e8 | 79 | idma->dma.sg = sg_next(idma->dma.sg); |
fa4e9989 RK |
80 | idma->dma_addr = idma->dma.sg->dma_address; |
81 | idma->dma_len = idma->dma.sg->length; | |
ad9dd94c | 82 | idma->dma.sgcount--; |
1da177e4 | 83 | } else { |
ad9dd94c | 84 | idma->dma.sg = NULL; |
1da177e4 LT |
85 | flags |= DMA_END_S; |
86 | } | |
87 | } | |
88 | } else { | |
89 | flags = DMA_END_S | DMA_END_L; | |
90 | sg->dma_address = 0; | |
91 | sg->length = 0; | |
92 | } | |
93 | ||
94 | sg->length |= flags; | |
95 | } | |
96 | ||
0cd61b68 | 97 | static irqreturn_t iomd_dma_handle(int irq, void *dev_id) |
1da177e4 | 98 | { |
ad9dd94c RK |
99 | struct iomd_dma *idma = dev_id; |
100 | unsigned long base = idma->base; | |
1da177e4 LT |
101 | |
102 | do { | |
103 | unsigned int status; | |
104 | ||
105 | status = iomd_readb(base + ST); | |
106 | if (!(status & DMA_ST_INT)) | |
107 | return IRQ_HANDLED; | |
108 | ||
ad9dd94c RK |
109 | if ((idma->state ^ status) & DMA_ST_AB) |
110 | iomd_get_next_sg(&idma->cur_sg, idma); | |
1da177e4 LT |
111 | |
112 | switch (status & (DMA_ST_OFL | DMA_ST_AB)) { | |
113 | case DMA_ST_OFL: /* OIA */ | |
114 | case DMA_ST_AB: /* .IB */ | |
ad9dd94c RK |
115 | iomd_writel(idma->cur_sg.dma_address, base + CURA); |
116 | iomd_writel(idma->cur_sg.length, base + ENDA); | |
117 | idma->state = DMA_ST_AB; | |
1da177e4 LT |
118 | break; |
119 | ||
120 | case DMA_ST_OFL | DMA_ST_AB: /* OIB */ | |
121 | case 0: /* .IA */ | |
ad9dd94c RK |
122 | iomd_writel(idma->cur_sg.dma_address, base + CURB); |
123 | iomd_writel(idma->cur_sg.length, base + ENDB); | |
124 | idma->state = 0; | |
1da177e4 LT |
125 | break; |
126 | } | |
127 | ||
128 | if (status & DMA_ST_OFL && | |
ad9dd94c | 129 | idma->cur_sg.length == (DMA_END_S|DMA_END_L)) |
1da177e4 LT |
130 | break; |
131 | } while (1); | |
132 | ||
ad9dd94c | 133 | idma->state = ~DMA_ST_AB; |
1da177e4 LT |
134 | disable_irq(irq); |
135 | ||
136 | return IRQ_HANDLED; | |
137 | } | |
138 | ||
1df81302 | 139 | static int iomd_request_dma(unsigned int chan, dma_t *dma) |
1da177e4 | 140 | { |
ad9dd94c RK |
141 | struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma); |
142 | ||
143 | return request_irq(idma->irq, iomd_dma_handle, | |
78f6db99 | 144 | 0, idma->dma.device_id, idma); |
1da177e4 LT |
145 | } |
146 | ||
1df81302 | 147 | static void iomd_free_dma(unsigned int chan, dma_t *dma) |
1da177e4 | 148 | { |
ad9dd94c RK |
149 | struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma); |
150 | ||
151 | free_irq(idma->irq, idma); | |
1da177e4 LT |
152 | } |
153 | ||
1df81302 | 154 | static void iomd_enable_dma(unsigned int chan, dma_t *dma) |
1da177e4 | 155 | { |
ad9dd94c RK |
156 | struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma); |
157 | unsigned long dma_base = idma->base; | |
1da177e4 LT |
158 | unsigned int ctrl = TRANSFER_SIZE | DMA_CR_E; |
159 | ||
ad9dd94c RK |
160 | if (idma->dma.invalid) { |
161 | idma->dma.invalid = 0; | |
1da177e4 LT |
162 | |
163 | /* | |
164 | * Cope with ISA-style drivers which expect cache | |
165 | * coherence. | |
166 | */ | |
ad9dd94c RK |
167 | if (!idma->dma.sg) { |
168 | idma->dma.sg = &idma->dma.buf; | |
169 | idma->dma.sgcount = 1; | |
170 | idma->dma.buf.length = idma->dma.count; | |
171 | idma->dma.buf.dma_address = dma_map_single(NULL, | |
172 | idma->dma.addr, idma->dma.count, | |
173 | idma->dma.dma_mode == DMA_MODE_READ ? | |
7cdad482 | 174 | DMA_FROM_DEVICE : DMA_TO_DEVICE); |
1da177e4 LT |
175 | } |
176 | ||
177 | iomd_writeb(DMA_CR_C, dma_base + CR); | |
ad9dd94c | 178 | idma->state = DMA_ST_AB; |
1da177e4 | 179 | } |
ad9dd94c RK |
180 | |
181 | if (idma->dma.dma_mode == DMA_MODE_READ) | |
1da177e4 LT |
182 | ctrl |= DMA_CR_D; |
183 | ||
184 | iomd_writeb(ctrl, dma_base + CR); | |
ad9dd94c | 185 | enable_irq(idma->irq); |
1da177e4 LT |
186 | } |
187 | ||
1df81302 | 188 | static void iomd_disable_dma(unsigned int chan, dma_t *dma) |
1da177e4 | 189 | { |
ad9dd94c RK |
190 | struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma); |
191 | unsigned long dma_base = idma->base; | |
1da177e4 LT |
192 | unsigned long flags; |
193 | ||
194 | local_irq_save(flags); | |
ad9dd94c RK |
195 | if (idma->state != ~DMA_ST_AB) |
196 | disable_irq(idma->irq); | |
1da177e4 LT |
197 | iomd_writeb(0, dma_base + CR); |
198 | local_irq_restore(flags); | |
199 | } | |
200 | ||
1df81302 | 201 | static int iomd_set_dma_speed(unsigned int chan, dma_t *dma, int cycle) |
1da177e4 LT |
202 | { |
203 | int tcr, speed; | |
204 | ||
205 | if (cycle < 188) | |
206 | speed = 3; | |
207 | else if (cycle <= 250) | |
208 | speed = 2; | |
209 | else if (cycle < 438) | |
210 | speed = 1; | |
211 | else | |
212 | speed = 0; | |
213 | ||
214 | tcr = iomd_readb(IOMD_DMATCR); | |
215 | speed &= 3; | |
216 | ||
1df81302 | 217 | switch (chan) { |
1da177e4 LT |
218 | case DMA_0: |
219 | tcr = (tcr & ~0x03) | speed; | |
220 | break; | |
221 | ||
222 | case DMA_1: | |
223 | tcr = (tcr & ~0x0c) | (speed << 2); | |
224 | break; | |
225 | ||
226 | case DMA_2: | |
227 | tcr = (tcr & ~0x30) | (speed << 4); | |
228 | break; | |
229 | ||
230 | case DMA_3: | |
231 | tcr = (tcr & ~0xc0) | (speed << 6); | |
232 | break; | |
233 | ||
234 | default: | |
235 | break; | |
236 | } | |
237 | ||
238 | iomd_writeb(tcr, IOMD_DMATCR); | |
239 | ||
240 | return speed; | |
241 | } | |
242 | ||
243 | static struct dma_ops iomd_dma_ops = { | |
244 | .type = "IOMD", | |
245 | .request = iomd_request_dma, | |
246 | .free = iomd_free_dma, | |
247 | .enable = iomd_enable_dma, | |
248 | .disable = iomd_disable_dma, | |
249 | .setspeed = iomd_set_dma_speed, | |
250 | }; | |
251 | ||
252 | static struct fiq_handler fh = { | |
253 | .name = "floppydma" | |
254 | }; | |
255 | ||
308d333a RK |
256 | struct floppy_dma { |
257 | struct dma_struct dma; | |
258 | unsigned int fiq; | |
259 | }; | |
260 | ||
1df81302 | 261 | static void floppy_enable_dma(unsigned int chan, dma_t *dma) |
1da177e4 | 262 | { |
ad9dd94c | 263 | struct floppy_dma *fdma = container_of(dma, struct floppy_dma, dma); |
1da177e4 LT |
264 | void *fiqhandler_start; |
265 | unsigned int fiqhandler_length; | |
266 | struct pt_regs regs; | |
267 | ||
ad9dd94c | 268 | if (fdma->dma.sg) |
1da177e4 LT |
269 | BUG(); |
270 | ||
ad9dd94c | 271 | if (fdma->dma.dma_mode == DMA_MODE_READ) { |
1da177e4 LT |
272 | extern unsigned char floppy_fiqin_start, floppy_fiqin_end; |
273 | fiqhandler_start = &floppy_fiqin_start; | |
274 | fiqhandler_length = &floppy_fiqin_end - &floppy_fiqin_start; | |
275 | } else { | |
276 | extern unsigned char floppy_fiqout_start, floppy_fiqout_end; | |
277 | fiqhandler_start = &floppy_fiqout_start; | |
278 | fiqhandler_length = &floppy_fiqout_end - &floppy_fiqout_start; | |
279 | } | |
280 | ||
ad9dd94c RK |
281 | regs.ARM_r9 = fdma->dma.count; |
282 | regs.ARM_r10 = (unsigned long)fdma->dma.addr; | |
1da177e4 LT |
283 | regs.ARM_fp = (unsigned long)FLOPPYDMA_BASE; |
284 | ||
285 | if (claim_fiq(&fh)) { | |
286 | printk("floppydma: couldn't claim FIQ.\n"); | |
287 | return; | |
288 | } | |
289 | ||
290 | set_fiq_handler(fiqhandler_start, fiqhandler_length); | |
291 | set_fiq_regs(®s); | |
ad9dd94c | 292 | enable_fiq(fdma->fiq); |
1da177e4 LT |
293 | } |
294 | ||
1df81302 | 295 | static void floppy_disable_dma(unsigned int chan, dma_t *dma) |
1da177e4 | 296 | { |
ad9dd94c RK |
297 | struct floppy_dma *fdma = container_of(dma, struct floppy_dma, dma); |
298 | disable_fiq(fdma->fiq); | |
1da177e4 LT |
299 | release_fiq(&fh); |
300 | } | |
301 | ||
1df81302 | 302 | static int floppy_get_residue(unsigned int chan, dma_t *dma) |
1da177e4 LT |
303 | { |
304 | struct pt_regs regs; | |
305 | get_fiq_regs(®s); | |
306 | return regs.ARM_r9; | |
307 | } | |
308 | ||
309 | static struct dma_ops floppy_dma_ops = { | |
310 | .type = "FIQDMA", | |
311 | .enable = floppy_enable_dma, | |
312 | .disable = floppy_disable_dma, | |
313 | .residue = floppy_get_residue, | |
314 | }; | |
315 | ||
316 | /* | |
317 | * This is virtual DMA - we don't need anything here. | |
318 | */ | |
1df81302 | 319 | static void sound_enable_disable_dma(unsigned int chan, dma_t *dma) |
1da177e4 LT |
320 | { |
321 | } | |
322 | ||
323 | static struct dma_ops sound_dma_ops = { | |
324 | .type = "VIRTUAL", | |
325 | .enable = sound_enable_disable_dma, | |
326 | .disable = sound_enable_disable_dma, | |
327 | }; | |
328 | ||
ad9dd94c | 329 | static struct iomd_dma iomd_dma[6]; |
2f757f2a | 330 | |
ad9dd94c RK |
331 | static struct floppy_dma floppy_dma = { |
332 | .dma = { | |
333 | .d_ops = &floppy_dma_ops, | |
334 | }, | |
335 | .fiq = FIQ_FLOPPYDATA, | |
2f757f2a RK |
336 | }; |
337 | ||
338 | static dma_t sound_dma = { | |
339 | .d_ops = &sound_dma_ops, | |
340 | }; | |
341 | ||
342 | static int __init rpc_dma_init(void) | |
1da177e4 | 343 | { |
2f757f2a RK |
344 | unsigned int i; |
345 | int ret; | |
346 | ||
1da177e4 LT |
347 | iomd_writeb(0, IOMD_IO0CR); |
348 | iomd_writeb(0, IOMD_IO1CR); | |
349 | iomd_writeb(0, IOMD_IO2CR); | |
350 | iomd_writeb(0, IOMD_IO3CR); | |
351 | ||
352 | iomd_writeb(0xa0, IOMD_DMATCR); | |
353 | ||
1da177e4 LT |
354 | /* |
355 | * Setup DMA channels 2,3 to be for podules | |
356 | * and channels 0,1 for internal devices | |
357 | */ | |
358 | iomd_writeb(DMA_EXT_IO3|DMA_EXT_IO2, IOMD_DMAEXT); | |
2f757f2a | 359 | |
ad9dd94c RK |
360 | iomd_dma[DMA_0].base = IOMD_IO0CURA; |
361 | iomd_dma[DMA_0].irq = IRQ_DMA0; | |
362 | iomd_dma[DMA_1].base = IOMD_IO1CURA; | |
363 | iomd_dma[DMA_1].irq = IRQ_DMA1; | |
364 | iomd_dma[DMA_2].base = IOMD_IO2CURA; | |
365 | iomd_dma[DMA_2].irq = IRQ_DMA2; | |
366 | iomd_dma[DMA_3].base = IOMD_IO3CURA; | |
367 | iomd_dma[DMA_3].irq = IRQ_DMA3; | |
368 | iomd_dma[DMA_S0].base = IOMD_SD0CURA; | |
369 | iomd_dma[DMA_S0].irq = IRQ_DMAS0; | |
370 | iomd_dma[DMA_S1].base = IOMD_SD1CURA; | |
371 | iomd_dma[DMA_S1].irq = IRQ_DMAS1; | |
2f757f2a RK |
372 | |
373 | for (i = DMA_0; i <= DMA_S1; i++) { | |
ad9dd94c | 374 | iomd_dma[i].dma.d_ops = &iomd_dma_ops; |
2f757f2a | 375 | |
ad9dd94c | 376 | ret = isa_dma_add(i, &iomd_dma[i].dma); |
2f757f2a RK |
377 | if (ret) |
378 | printk("IOMDDMA%u: unable to register: %d\n", i, ret); | |
379 | } | |
380 | ||
ad9dd94c | 381 | ret = isa_dma_add(DMA_VIRTUAL_FLOPPY, &floppy_dma.dma); |
2f757f2a RK |
382 | if (ret) |
383 | printk("IOMDFLOPPY: unable to register: %d\n", ret); | |
384 | ret = isa_dma_add(DMA_VIRTUAL_SOUND, &sound_dma); | |
385 | if (ret) | |
386 | printk("IOMDSOUND: unable to register: %d\n", ret); | |
387 | return 0; | |
1da177e4 | 388 | } |
2f757f2a | 389 | core_initcall(rpc_dma_init); |