[deliverable/linux.git] / arch / arm / mach-s3c2410 / clock.c

/* linux/arch/arm/mach-s3c2410/clock.c
 *
 * Copyright (c) 2004-2005 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * S3C2410 Clock control support
 *
 * Based on, and code from linux/arch/arm/mach-versatile/clock.c
 **
 **  Copyright (C) 2004 ARM Limited.
 **  Written by Deep Blue Solutions Limited.
 *
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*/

#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/sysdev.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/clk.h>
#include <linux/mutex.h>

#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/io.h>

#include <asm/arch/regs-clock.h>

#include "clock.h"
#include "cpu.h"

/* clock information */

static LIST_HEAD(clocks);
static DEFINE_MUTEX(clocks_mutex);

/* old functions */

void inline s3c24xx_clk_enable(unsigned int clocks, unsigned int enable)
{
	unsigned long clkcon;

	clkcon = __raw_readl(S3C2410_CLKCON);

	if (enable)
		clkcon |= clocks;
	else
		clkcon &= ~clocks;

	/* ensure none of the special function bits set */
	clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER);

	__raw_writel(clkcon, S3C2410_CLKCON);
}

/* enable and disable calls for use with the clk struct */

static int clk_null_enable(struct clk *clk, int enable)
{
	return 0;
}

int s3c24xx_clkcon_enable(struct clk *clk, int enable)
{
	s3c24xx_clk_enable(clk->ctrlbit, enable);
	return 0;
}

/* Clock API calls */

struct clk *clk_get(struct device *dev, const char *id)
{
	struct clk *p;
	struct clk *clk = ERR_PTR(-ENOENT);
	int idno;

	if (dev == NULL || dev->bus != &platform_bus_type)
		idno = -1;
	else
		idno = to_platform_device(dev)->id;

	mutex_lock(&clocks_mutex);

	list_for_each_entry(p, &clocks, list) {
		if (p->id == idno &&
		    strcmp(id, p->name) == 0 &&
		    try_module_get(p->owner)) {
			clk = p;
			break;
		}
	}

	/* check for the case where a device was supplied, but the
	 * clock that was being searched for is not device specific */

	if (IS_ERR(clk)) {
		list_for_each_entry(p, &clocks, list) {
			if (p->id == -1 && strcmp(id, p->name) == 0 &&
			    try_module_get(p->owner)) {
				clk = p;
				break;
			}
		}
	}

	mutex_unlock(&clocks_mutex);
	return clk;
}

void clk_put(struct clk *clk)
{
	module_put(clk->owner);
}

int clk_enable(struct clk *clk)
{
	if (IS_ERR(clk) || clk == NULL)
		return -EINVAL;

	clk_enable(clk->parent);

	mutex_lock(&clocks_mutex);

	if ((clk->usage++) == 0)
		(clk->enable)(clk, 1);

	mutex_unlock(&clocks_mutex);
	return 0;
}

void clk_disable(struct clk *clk)
{
	if (IS_ERR(clk) || clk == NULL)
		return;

	mutex_lock(&clocks_mutex);

	if ((--clk->usage) == 0)
		(clk->enable)(clk, 0);

	mutex_unlock(&clocks_mutex);
	clk_disable(clk->parent);
}


unsigned long clk_get_rate(struct clk *clk)
{
	if (IS_ERR(clk))
		return 0;

	if (clk->rate != 0)
		return clk->rate;

	while (clk->parent != NULL && clk->rate == 0)
		clk = clk->parent;

	return clk->rate;
}

long clk_round_rate(struct clk *clk, unsigned long rate)
{
	return rate;
}

int clk_set_rate(struct clk *clk, unsigned long rate)
{
	return -EINVAL;
}

struct clk *clk_get_parent(struct clk *clk)
{
	return clk->parent;
}

EXPORT_SYMBOL(clk_get);
EXPORT_SYMBOL(clk_put);
EXPORT_SYMBOL(clk_enable);
EXPORT_SYMBOL(clk_disable);
EXPORT_SYMBOL(clk_get_rate);
EXPORT_SYMBOL(clk_round_rate);
EXPORT_SYMBOL(clk_set_rate);
EXPORT_SYMBOL(clk_get_parent);

/* base clocks */

static struct clk clk_xtal = {
	.name		= "xtal",
	.id		= -1,
	.rate		= 0,
	.parent		= NULL,
	.ctrlbit	= 0,
};

static struct clk clk_f = {
	.name		= "fclk",
	.id		= -1,
	.rate		= 0,
	.parent		= NULL,
	.ctrlbit	= 0,
};

static struct clk clk_h = {
	.name		= "hclk",
	.id		= -1,
	.rate		= 0,
	.parent		= NULL,
	.ctrlbit	= 0,
};

static struct clk clk_p = {
	.name		= "pclk",
	.id		= -1,
	.rate		= 0,
	.parent		= NULL,
	.ctrlbit	= 0,
};

/* clocks that could be registered by external code */

struct clk s3c24xx_dclk0 = {
	.name		= "dclk0",
	.id		= -1,
};

struct clk s3c24xx_dclk1 = {
	.name		= "dclk1",
	.id		= -1,
};

struct clk s3c24xx_clkout0 = {
	.name		= "clkout0",
	.id		= -1,
};

struct clk s3c24xx_clkout1 = {
	.name		= "clkout1",
	.id		= -1,
};

struct clk s3c24xx_uclk = {
	.name		= "uclk",
	.id		= -1,
};


/* clock definitions */

static struct clk init_clocks[] = {
	{
		.name		= "nand",
		.id		= -1,
		.parent		= &clk_h,
		.enable		= s3c24xx_clkcon_enable,
		.ctrlbit	= S3C2410_CLKCON_NAND,
	}, {
		.name		= "lcd",
		.id		= -1,
		.parent		= &clk_h,
		.enable		= s3c24xx_clkcon_enable,
		.ctrlbit	= S3C2410_CLKCON_LCDC,
	}, {
		.name		= "usb-host",
		.id		= -1,
		.parent		= &clk_h,
		.enable		= s3c24xx_clkcon_enable,
		.ctrlbit	= S3C2410_CLKCON_USBH,
	}, {
		.name		= "usb-device",
		.id		= -1,
		.parent		= &clk_h,
		.enable		= s3c24xx_clkcon_enable,
		.ctrlbit	= S3C2410_CLKCON_USBD,
	}, {
		.name		= "timers",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s3c24xx_clkcon_enable,
		.ctrlbit	= S3C2410_CLKCON_PWMT,
	}, {
		.name		= "sdi",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s3c24xx_clkcon_enable,
		.ctrlbit	= S3C2410_CLKCON_SDI,
	}, {
		.name		= "uart",
		.id		= 0,
		.parent		= &clk_p,
		.enable		= s3c24xx_clkcon_enable,
		.ctrlbit	= S3C2410_CLKCON_UART0,
	}, {
		.name		= "uart",
		.id		= 1,
		.parent		= &clk_p,
		.enable		= s3c24xx_clkcon_enable,
		.ctrlbit	= S3C2410_CLKCON_UART1,
	}, {
		.name		= "uart",
		.id		= 2,
		.parent		= &clk_p,
		.enable		= s3c24xx_clkcon_enable,
		.ctrlbit	= S3C2410_CLKCON_UART2,
	}, {
		.name		= "gpio",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s3c24xx_clkcon_enable,
		.ctrlbit	= S3C2410_CLKCON_GPIO,
	}, {
		.name		= "rtc",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s3c24xx_clkcon_enable,
		.ctrlbit	= S3C2410_CLKCON_RTC,
	}, {
		.name		= "adc",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s3c24xx_clkcon_enable,
		.ctrlbit	= S3C2410_CLKCON_ADC,
	}, {
		.name		= "i2c",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s3c24xx_clkcon_enable,
		.ctrlbit	= S3C2410_CLKCON_IIC,
	}, {
		.name		= "iis",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s3c24xx_clkcon_enable,
		.ctrlbit	= S3C2410_CLKCON_IIS,
	}, {
		.name		= "spi",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s3c24xx_clkcon_enable,
		.ctrlbit	= S3C2410_CLKCON_SPI,
	}, {
		.name		= "watchdog",
		.id		= -1,
		.parent		= &clk_p,
		.ctrlbit	= 0,
	}
};

/* initialise the clock system */

int s3c24xx_register_clock(struct clk *clk)
{
	clk->owner = THIS_MODULE;

	if (clk->enable == NULL)
		clk->enable = clk_null_enable;

	/* if this is a standard clock, set the usage state */

	if (clk->ctrlbit) {
		unsigned long clkcon = __raw_readl(S3C2410_CLKCON);

		clk->usage = (clkcon & clk->ctrlbit) ? 1 : 0;
	}

	/* add to the list of available clocks */

	mutex_lock(&clocks_mutex);
	list_add(&clk->list, &clocks);
	mutex_unlock(&clocks_mutex);

	return 0;
}

/* initalise all the clocks */

int __init s3c24xx_setup_clocks(unsigned long xtal,
				unsigned long fclk,
				unsigned long hclk,
				unsigned long pclk)
{
	unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
	struct clk *clkp = init_clocks;
	int ptr;
	int ret;

	printk(KERN_INFO "S3C2410 Clocks, (c) 2004 Simtec Electronics\n");

	/* initialise the main system clocks */

	clk_xtal.rate = xtal;

	clk_h.rate = hclk;
	clk_p.rate = pclk;
	clk_f.rate = fclk;

	/* We must be careful disabling the clocks we are not intending to
	 * be using at boot time, as subsytems such as the LCD which do
	 * their own DMA requests to the bus can cause the system to lockup
	 * if they where in the middle of requesting bus access.
	 *
	 * Disabling the LCD clock if the LCD is active is very dangerous,
	 * and therefore the bootloader should be  careful to not enable
	 * the LCD clock if it is not needed.
	*/

	mutex_lock(&clocks_mutex);

	s3c24xx_clk_enable(S3C2410_CLKCON_NAND, 0);
	s3c24xx_clk_enable(S3C2410_CLKCON_USBH, 0);
	s3c24xx_clk_enable(S3C2410_CLKCON_USBD, 0);
	s3c24xx_clk_enable(S3C2410_CLKCON_ADC, 0);
	s3c24xx_clk_enable(S3C2410_CLKCON_IIC, 0);
	s3c24xx_clk_enable(S3C2410_CLKCON_SPI, 0);

	mutex_unlock(&clocks_mutex);

	/* assume uart clocks are correctly setup */

	/* register our clocks */

	if (s3c24xx_register_clock(&clk_xtal) < 0)
		printk(KERN_ERR "failed to register master xtal\n");

	if (s3c24xx_register_clock(&clk_f) < 0)
		printk(KERN_ERR "failed to register cpu fclk\n");

	if (s3c24xx_register_clock(&clk_h) < 0)
		printk(KERN_ERR "failed to register cpu hclk\n");

	if (s3c24xx_register_clock(&clk_p) < 0)
		printk(KERN_ERR "failed to register cpu pclk\n");

	/* register clocks from clock array */

	for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
		ret = s3c24xx_register_clock(clkp);
		if (ret < 0) {
			printk(KERN_ERR "Failed to register clock %s (%d)\n",
			       clkp->name, ret);
		}
	}

	/* show the clock-slow value */

	printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n",
	       print_mhz(xtal / ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))),
	       (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast",
	       (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
	       (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");

	return 0;
}
Commit	Line	Data
1da177e4 LT	1	/* linux/arch/arm/mach-s3c2410/clock.c
	2	*
	3	* Copyright (c) 2004-2005 Simtec Electronics
	4	* Ben Dooks <ben@simtec.co.uk>
	5	*
	6	* S3C2410 Clock control support
	7	*
	8	* Based on, and code from linux/arch/arm/mach-versatile/clock.c
	9	**
	10	** Copyright (C) 2004 ARM Limited.
	11	** Written by Deep Blue Solutions Limited.
	12	*
	13	*
	14	* This program is free software; you can redistribute it and/or modify
	15	* it under the terms of the GNU General Public License as published by
	16	* the Free Software Foundation; either version 2 of the License, or
	17	* (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	27	*/
	28
	29	#include <linux/init.h>
	30	#include <linux/module.h>
	31	#include <linux/kernel.h>
	32	#include <linux/list.h>
	33	#include <linux/errno.h>
	34	#include <linux/err.h>
d052d1be	35	#include <linux/platform_device.h>
1da177e4	36	#include <linux/sysdev.h>
1da177e4 LT	37	#include <linux/interrupt.h>
1da177e4 LT	38	#include <linux/ioport.h>
f8ce2547	39	#include <linux/clk.h>
00431707	40	#include <linux/mutex.h>
1da177e4 LT	41
1da177e4 LT	42	#include <asm/hardware.h>
1da177e4 LT	43	#include <asm/irq.h>
	44	#include <asm/io.h>
	45
1da177e4 LT	46	#include <asm/arch/regs-clock.h>
	47
	48	#include "clock.h"
	49	#include "cpu.h"
	50
	51	/* clock information */
	52
	53	static LIST_HEAD(clocks);
00431707	54	static DEFINE_MUTEX(clocks_mutex);
1da177e4 LT	55
	56	/* old functions */
	57
	58	void inline s3c24xx_clk_enable(unsigned int clocks, unsigned int enable)
	59	{
	60	unsigned long clkcon;
1da177e4 LT	61
1da177e4 LT	62	clkcon = __raw_readl(S3C2410_CLKCON);
1da177e4 LT	63
	64	if (enable)
	65	clkcon \|= clocks;
2a513ce7 BD	66	else
2a513ce7 BD	67	clkcon &= ~clocks;
1da177e4 LT	68
	69	/* ensure none of the special function bits set */
	70	clkcon &= ~(S3C2410_CLKCON_IDLE\|S3C2410_CLKCON_POWER);
	71
	72	__raw_writel(clkcon, S3C2410_CLKCON);
1da177e4 LT	73	}
	74
	75	/* enable and disable calls for use with the clk struct */
	76
	77	static int clk_null_enable(struct clk *clk, int enable)
	78	{
	79	return 0;
	80	}
	81
	82	int s3c24xx_clkcon_enable(struct clk *clk, int enable)
	83	{
	84	s3c24xx_clk_enable(clk->ctrlbit, enable);
	85	return 0;
	86	}
	87
	88	/* Clock API calls */
	89
	90	struct clk clk_get(struct device dev, const char *id)
	91	{
	92	struct clk *p;
	93	struct clk *clk = ERR_PTR(-ENOENT);
	94	int idno;
	95
c086f282 BD	96	if (dev == NULL \|\| dev->bus != &platform_bus_type)
	97	idno = -1;
	98	else
	99	idno = to_platform_device(dev)->id;
1da177e4	100
00431707	101	mutex_lock(&clocks_mutex);
1da177e4 LT	102
	103	list_for_each_entry(p, &clocks, list) {
	104	if (p->id == idno &&
	105	strcmp(id, p->name) == 0 &&
	106	try_module_get(p->owner)) {
	107	clk = p;
	108	break;
	109	}
	110	}
	111
	112	/* check for the case where a device was supplied, but the
	113	* clock that was being searched for is not device specific */
	114
	115	if (IS_ERR(clk)) {
	116	list_for_each_entry(p, &clocks, list) {
	117	if (p->id == -1 && strcmp(id, p->name) == 0 &&
	118	try_module_get(p->owner)) {
	119	clk = p;
	120	break;
	121	}
	122	}
	123	}
	124
00431707	125	mutex_unlock(&clocks_mutex);
1da177e4 LT	126	return clk;
	127	}
	128
	129	void clk_put(struct clk *clk)
	130	{
	131	module_put(clk->owner);
	132	}
	133
	134	int clk_enable(struct clk *clk)
	135	{
2a513ce7	136	if (IS_ERR(clk) \|\| clk == NULL)
1da177e4 LT	137	return -EINVAL;
1da177e4 LT	138
2a513ce7 BD	139	clk_enable(clk->parent);
	140
	141	mutex_lock(&clocks_mutex);
	142
	143	if ((clk->usage++) == 0)
	144	(clk->enable)(clk, 1);
	145
	146	mutex_unlock(&clocks_mutex);
	147	return 0;
1da177e4 LT	148	}
	149
	150	void clk_disable(struct clk *clk)
	151	{
2a513ce7 BD	152	if (IS_ERR(clk) \|\| clk == NULL)
	153	return;
	154
	155	mutex_lock(&clocks_mutex);
	156
	157	if ((--clk->usage) == 0)
1da177e4	158	(clk->enable)(clk, 0);
2a513ce7 BD	159
	160	mutex_unlock(&clocks_mutex);
	161	clk_disable(clk->parent);
1da177e4 LT	162	}
	163
	164
1da177e4 LT	165	unsigned long clk_get_rate(struct clk *clk)
	166	{
	167	if (IS_ERR(clk))
	168	return 0;
	169
	170	if (clk->rate != 0)
	171	return clk->rate;
	172
	173	while (clk->parent != NULL && clk->rate == 0)
	174	clk = clk->parent;
	175
	176	return clk->rate;
	177	}
	178
	179	long clk_round_rate(struct clk *clk, unsigned long rate)
	180	{
	181	return rate;
	182	}
	183
	184	int clk_set_rate(struct clk *clk, unsigned long rate)
	185	{
	186	return -EINVAL;
	187	}
	188
	189	struct clk clk_get_parent(struct clk clk)
	190	{
	191	return clk->parent;
	192	}
	193
	194	EXPORT_SYMBOL(clk_get);
	195	EXPORT_SYMBOL(clk_put);
	196	EXPORT_SYMBOL(clk_enable);
	197	EXPORT_SYMBOL(clk_disable);
1da177e4 LT	198	EXPORT_SYMBOL(clk_get_rate);
	199	EXPORT_SYMBOL(clk_round_rate);
	200	EXPORT_SYMBOL(clk_set_rate);
	201	EXPORT_SYMBOL(clk_get_parent);
	202
	203	/* base clocks */
	204
	205	static struct clk clk_xtal = {
	206	.name = "xtal",
	207	.id = -1,
	208	.rate = 0,
	209	.parent = NULL,
	210	.ctrlbit = 0,
	211	};
	212
	213	static struct clk clk_f = {
	214	.name = "fclk",
	215	.id = -1,
	216	.rate = 0,
	217	.parent = NULL,
	218	.ctrlbit = 0,
	219	};
	220
	221	static struct clk clk_h = {
	222	.name = "hclk",
	223	.id = -1,
	224	.rate = 0,
	225	.parent = NULL,
	226	.ctrlbit = 0,
	227	};
	228
	229	static struct clk clk_p = {
	230	.name = "pclk",
	231	.id = -1,
	232	.rate = 0,
	233	.parent = NULL,
	234	.ctrlbit = 0,
	235	};
	236
	237	/* clocks that could be registered by external code */
	238
	239	struct clk s3c24xx_dclk0 = {
	240	.name = "dclk0",
	241	.id = -1,
	242	};
	243
	244	struct clk s3c24xx_dclk1 = {
	245	.name = "dclk1",
	246	.id = -1,
	247	};
	248
	249	struct clk s3c24xx_clkout0 = {
	250	.name = "clkout0",
	251	.id = -1,
	252	};
	253
	254	struct clk s3c24xx_clkout1 = {
	255	.name = "clkout1",
	256	.id = -1,
	257	};
	258
	259	struct clk s3c24xx_uclk = {
	260	.name = "uclk",
	261	.id = -1,
262	};
263
264
265	/* clock definitions */
266
267	static struct clk init_clocks[] = {
fe38ea56 BD	268	{
	269	.name = "nand",
	270	.id = -1,
	271	.parent = &clk_h,
	272	.enable = s3c24xx_clkcon_enable,
	273	.ctrlbit = S3C2410_CLKCON_NAND,
	274	}, {
	275	.name = "lcd",
	276	.id = -1,
	277	.parent = &clk_h,
	278	.enable = s3c24xx_clkcon_enable,
	279	.ctrlbit = S3C2410_CLKCON_LCDC,
	280	}, {
	281	.name = "usb-host",
	282	.id = -1,
	283	.parent = &clk_h,
	284	.enable = s3c24xx_clkcon_enable,
	285	.ctrlbit = S3C2410_CLKCON_USBH,
	286	}, {
	287	.name = "usb-device",
	288	.id = -1,
	289	.parent = &clk_h,
	290	.enable = s3c24xx_clkcon_enable,
	291	.ctrlbit = S3C2410_CLKCON_USBD,
	292	}, {
	293	.name = "timers",
	294	.id = -1,
	295	.parent = &clk_p,
	296	.enable = s3c24xx_clkcon_enable,
	297	.ctrlbit = S3C2410_CLKCON_PWMT,
	298	}, {
	299	.name = "sdi",
	300	.id = -1,
	301	.parent = &clk_p,
	302	.enable = s3c24xx_clkcon_enable,
	303	.ctrlbit = S3C2410_CLKCON_SDI,
	304	}, {
	305	.name = "uart",
	306	.id = 0,
	307	.parent = &clk_p,
	308	.enable = s3c24xx_clkcon_enable,
	309	.ctrlbit = S3C2410_CLKCON_UART0,
	310	}, {
	311	.name = "uart",
	312	.id = 1,
	313	.parent = &clk_p,
	314	.enable = s3c24xx_clkcon_enable,
	315	.ctrlbit = S3C2410_CLKCON_UART1,
	316	}, {
	317	.name = "uart",
	318	.id = 2,
	319	.parent = &clk_p,
	320	.enable = s3c24xx_clkcon_enable,
	321	.ctrlbit = S3C2410_CLKCON_UART2,
	322	}, {
	323	.name = "gpio",
	324	.id = -1,
	325	.parent = &clk_p,
	326	.enable = s3c24xx_clkcon_enable,
	327	.ctrlbit = S3C2410_CLKCON_GPIO,
	328	}, {
	329	.name = "rtc",
	330	.id = -1,
	331	.parent = &clk_p,
332	.enable = s3c24xx_clkcon_enable,
333	.ctrlbit = S3C2410_CLKCON_RTC,
334	}, {
335	.name = "adc",
336	.id = -1,
337	.parent = &clk_p,
338	.enable = s3c24xx_clkcon_enable,
339	.ctrlbit = S3C2410_CLKCON_ADC,
340	}, {
341	.name = "i2c",
342	.id = -1,
343	.parent = &clk_p,
344	.enable = s3c24xx_clkcon_enable,
345	.ctrlbit = S3C2410_CLKCON_IIC,
346	}, {
347	.name = "iis",
348	.id = -1,
349	.parent = &clk_p,
350	.enable = s3c24xx_clkcon_enable,
351	.ctrlbit = S3C2410_CLKCON_IIS,
352	}, {
353	.name = "spi",
354	.id = -1,
355	.parent = &clk_p,
356	.enable = s3c24xx_clkcon_enable,
357	.ctrlbit = S3C2410_CLKCON_SPI,
358	}, {
359	.name = "watchdog",
360	.id = -1,
361	.parent = &clk_p,
362	.ctrlbit = 0,
1da177e4 LT	363	}
	364	};
	365
	366	/* initialise the clock system */
	367
	368	int s3c24xx_register_clock(struct clk *clk)
	369	{
	370	clk->owner = THIS_MODULE;
1da177e4 LT	371
	372	if (clk->enable == NULL)
	373	clk->enable = clk_null_enable;
	374
2a513ce7 BD	375	/* if this is a standard clock, set the usage state */
	376
	377	if (clk->ctrlbit) {
	378	unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
	379
	380	clk->usage = (clkcon & clk->ctrlbit) ? 1 : 0;
	381	}
	382
1da177e4 LT	383	/* add to the list of available clocks */
1da177e4 LT	384
00431707	385	mutex_lock(&clocks_mutex);
1da177e4	386	list_add(&clk->list, &clocks);
00431707	387	mutex_unlock(&clocks_mutex);
1da177e4 LT	388
	389	return 0;
	390	}
	391
	392	/* initalise all the clocks */
	393
	394	int __init s3c24xx_setup_clocks(unsigned long xtal,
	395	unsigned long fclk,
	396	unsigned long hclk,
	397	unsigned long pclk)
	398	{
d6b0bf21	399	unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
1da177e4 LT	400	struct clk *clkp = init_clocks;
	401	int ptr;
	402	int ret;
	403
	404	printk(KERN_INFO "S3C2410 Clocks, (c) 2004 Simtec Electronics\n");
	405
	406	/* initialise the main system clocks */
	407
	408	clk_xtal.rate = xtal;
	409
	410	clk_h.rate = hclk;
	411	clk_p.rate = pclk;
	412	clk_f.rate = fclk;
	413
fe38ea56 BD	414	/* We must be careful disabling the clocks we are not intending to
	415	* be using at boot time, as subsytems such as the LCD which do
	416	* their own DMA requests to the bus can cause the system to lockup
	417	* if they where in the middle of requesting bus access.
1da177e4	418	*
fe38ea56 BD	419	* Disabling the LCD clock if the LCD is active is very dangerous,
	420	* and therefore the bootloader should be careful to not enable
	421	* the LCD clock if it is not needed.
	422	*/
1da177e4	423
2a513ce7 BD	424	mutex_lock(&clocks_mutex);
2a513ce7 BD	425
1da177e4 LT	426	s3c24xx_clk_enable(S3C2410_CLKCON_NAND, 0);
	427	s3c24xx_clk_enable(S3C2410_CLKCON_USBH, 0);
	428	s3c24xx_clk_enable(S3C2410_CLKCON_USBD, 0);
	429	s3c24xx_clk_enable(S3C2410_CLKCON_ADC, 0);
	430	s3c24xx_clk_enable(S3C2410_CLKCON_IIC, 0);
	431	s3c24xx_clk_enable(S3C2410_CLKCON_SPI, 0);
	432
2a513ce7 BD	433	mutex_unlock(&clocks_mutex);
2a513ce7 BD	434
1da177e4 LT	435	/* assume uart clocks are correctly setup */
	436
	437	/* register our clocks */
	438
	439	if (s3c24xx_register_clock(&clk_xtal) < 0)
	440	printk(KERN_ERR "failed to register master xtal\n");
	441
	442	if (s3c24xx_register_clock(&clk_f) < 0)
	443	printk(KERN_ERR "failed to register cpu fclk\n");
	444
	445	if (s3c24xx_register_clock(&clk_h) < 0)
	446	printk(KERN_ERR "failed to register cpu hclk\n");
	447
	448	if (s3c24xx_register_clock(&clk_p) < 0)
	449	printk(KERN_ERR "failed to register cpu pclk\n");
	450
	451	/* register clocks from clock array */
	452
	453	for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
	454	ret = s3c24xx_register_clock(clkp);
	455	if (ret < 0) {
	456	printk(KERN_ERR "Failed to register clock %s (%d)\n",
	457	clkp->name, ret);
	458	}
	459	}
	460
d6b0bf21 BD	461	/* show the clock-slow value */
	462
	463	printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n",
	464	print_mhz(xtal / ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))),
	465	(clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast",
	466	(clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
	467	(clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");
	468
1da177e4 LT	469	return 0;
1da177e4 LT	470	}