[deliverable/linux.git] / arch / arm / mach-s3c2410 / include / mach / dma.h

/* arch/arm/mach-s3c2410/include/mach/dma.h
 *
 * Copyright (C) 2003-2006 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * Samsung S3C24XX DMA support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H __FILE__

#include <linux/sysdev.h>

#define MAX_DMA_TRANSFER_SIZE   0x100000 /* Data Unit is half word  */

/* We use `virtual` dma channels to hide the fact we have only a limited
 * number of DMA channels, and not of all of them (dependent on the device)
 * can be attached to any DMA source. We therefore let the DMA core handle
 * the allocation of hardware channels to clients.
*/

enum dma_ch {
	DMACH_XD0,
	DMACH_XD1,
	DMACH_SDI,
	DMACH_SPI0,
	DMACH_SPI1,
	DMACH_UART0,
	DMACH_UART1,
	DMACH_UART2,
	DMACH_TIMER,
	DMACH_I2S_IN,
	DMACH_I2S_OUT,
	DMACH_PCM_IN,
	DMACH_PCM_OUT,
	DMACH_MIC_IN,
	DMACH_USB_EP1,
	DMACH_USB_EP2,
	DMACH_USB_EP3,
	DMACH_USB_EP4,
	DMACH_UART0_SRC2,	/* s3c2412 second uart sources */
	DMACH_UART1_SRC2,
	DMACH_UART2_SRC2,
	DMACH_UART3,		/* s3c2443 has extra uart */
	DMACH_UART3_SRC2,
	DMACH_MAX,		/* the end entry */
};

static inline bool samsung_dma_has_circular(void)
{
	return false;
}

static inline bool samsung_dma_is_dmadev(void)
{
	return false;
}

#include <plat/dma.h>

#define DMACH_LOW_LEVEL	(1<<28)	/* use this to specifiy hardware ch no */

/* we have 4 dma channels */
#if !defined(CONFIG_CPU_S3C2443) && !defined(CONFIG_CPU_S3C2416)
#define S3C_DMA_CHANNELS		(4)
#else
#define S3C_DMA_CHANNELS		(6)
#endif

/* types */

enum s3c2410_dma_state {
	S3C2410_DMA_IDLE,
	S3C2410_DMA_RUNNING,
	S3C2410_DMA_PAUSED
};

/* enum s3c2410_dma_loadst
 *
 * This represents the state of the DMA engine, wrt to the loaded / running
 * transfers. Since we don't have any way of knowing exactly the state of
 * the DMA transfers, we need to know the state to make decisions on wether
 * we can
 *
 * S3C2410_DMA_NONE
 *
 * There are no buffers loaded (the channel should be inactive)
 *
 * S3C2410_DMA_1LOADED
 *
 * There is one buffer loaded, however it has not been confirmed to be
 * loaded by the DMA engine. This may be because the channel is not
 * yet running, or the DMA driver decided that it was too costly to
 * sit and wait for it to happen.
 *
 * S3C2410_DMA_1RUNNING
 *
 * The buffer has been confirmed running, and not finisged
 *
 * S3C2410_DMA_1LOADED_1RUNNING
 *
 * There is a buffer waiting to be loaded by the DMA engine, and one
 * currently running.
*/

enum s3c2410_dma_loadst {
	S3C2410_DMALOAD_NONE,
	S3C2410_DMALOAD_1LOADED,
	S3C2410_DMALOAD_1RUNNING,
	S3C2410_DMALOAD_1LOADED_1RUNNING,
};


/* flags */

#define S3C2410_DMAF_SLOW         (1<<0)   /* slow, so don't worry about
					    * waiting for reloads */
#define S3C2410_DMAF_AUTOSTART    (1<<1)   /* auto-start if buffer queued */

#define S3C2410_DMAF_CIRCULAR	(1 << 2)	/* no circular dma support */

/* dma buffer */

struct s3c2410_dma_buf;

/* s3c2410_dma_buf
 *
 * internally used buffer structure to describe a queued or running
 * buffer.
*/

struct s3c2410_dma_buf {
	struct s3c2410_dma_buf	*next;
	int			 magic;		/* magic */
	int			 size;		/* buffer size in bytes */
	dma_addr_t		 data;		/* start of DMA data */
	dma_addr_t		 ptr;		/* where the DMA got to [1] */
	void			*id;		/* client's id */
};

/* [1] is this updated for both recv/send modes? */

struct s3c2410_dma_stats {
	unsigned long		loads;
	unsigned long		timeout_longest;
	unsigned long		timeout_shortest;
	unsigned long		timeout_avg;
	unsigned long		timeout_failed;
};

struct s3c2410_dma_map;

/* struct s3c2410_dma_chan
 *
 * full state information for each DMA channel
*/

struct s3c2410_dma_chan {
	/* channel state flags and information */
	unsigned char		 number;      /* number of this dma channel */
	unsigned char		 in_use;      /* channel allocated */
	unsigned char		 irq_claimed; /* irq claimed for channel */
	unsigned char		 irq_enabled; /* irq enabled for channel */
	unsigned char		 xfer_unit;   /* size of an transfer */

	/* channel state */

	enum s3c2410_dma_state	 state;
	enum s3c2410_dma_loadst	 load_state;
	struct s3c2410_dma_client *client;

	/* channel configuration */
	enum dma_data_direction	 source;
	enum dma_ch		 req_ch;
	unsigned long		 dev_addr;
	unsigned long		 load_timeout;
	unsigned int		 flags;		/* channel flags */

	struct s3c24xx_dma_map	*map;		/* channel hw maps */

	/* channel's hardware position and configuration */
	void __iomem		*regs;		/* channels registers */
	void __iomem		*addr_reg;	/* data address register */
	unsigned int		 irq;		/* channel irq */
	unsigned long		 dcon;		/* default value of DCON */

	/* driver handles */
	s3c2410_dma_cbfn_t	 callback_fn;	/* buffer done callback */
	s3c2410_dma_opfn_t	 op_fn;		/* channel op callback */

	/* stats gathering */
	struct s3c2410_dma_stats *stats;
	struct s3c2410_dma_stats  stats_store;

	/* buffer list and information */
	struct s3c2410_dma_buf	*curr;		/* current dma buffer */
	struct s3c2410_dma_buf	*next;		/* next buffer to load */
	struct s3c2410_dma_buf	*end;		/* end of queue */

	/* system device */
	struct sys_device	dev;
};

typedef unsigned long dma_device_t;

#endif /* __ASM_ARCH_DMA_H */
Commit	Line	Data
a09e64fb	1	/* arch/arm/mach-s3c2410/include/mach/dma.h
1da177e4	2	*
ccae941e	3	* Copyright (C) 2003-2006 Simtec Electronics
1da177e4 LT	4	* Ben Dooks <ben@simtec.co.uk>
1da177e4 LT	5	*
44dc9404	6	* Samsung S3C24XX DMA support
1da177e4 LT	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
1da177e4 LT	11	*/
	12
	13	#ifndef __ASM_ARCH_DMA_H
	14	#define __ASM_ARCH_DMA_H __FILE__
	15
1da177e4	16	#include <linux/sysdev.h>
1da177e4	17
1da177e4 LT	18	#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
1da177e4 LT	19
505788cc	20	/* We use `virtual` dma channels to hide the fact we have only a limited
25985edc	21	* number of DMA channels, and not of all of them (dependent on the device)
505788cc BD	22	* can be attached to any DMA source. We therefore let the DMA core handle
	23	* the allocation of hardware channels to clients.
	24	*/
	25
	26	enum dma_ch {
	27	DMACH_XD0,
	28	DMACH_XD1,
	29	DMACH_SDI,
	30	DMACH_SPI0,
	31	DMACH_SPI1,
	32	DMACH_UART0,
	33	DMACH_UART1,
	34	DMACH_UART2,
	35	DMACH_TIMER,
	36	DMACH_I2S_IN,
	37	DMACH_I2S_OUT,
	38	DMACH_PCM_IN,
	39	DMACH_PCM_OUT,
	40	DMACH_MIC_IN,
	41	DMACH_USB_EP1,
	42	DMACH_USB_EP2,
	43	DMACH_USB_EP3,
	44	DMACH_USB_EP4,
34348012 BD	45	DMACH_UART0_SRC2, /* s3c2412 second uart sources */
	46	DMACH_UART1_SRC2,
	47	DMACH_UART2_SRC2,
15e4db7b BD	48	DMACH_UART3, /* s3c2443 has extra uart */
15e4db7b BD	49	DMACH_UART3_SRC2,
505788cc BD	50	DMACH_MAX, /* the end entry */
	51	};
	52
344b4c48 BK	53	static inline bool samsung_dma_has_circular(void)
	54	{
	55	return false;
	56	}
	57
c4e16625 BK	58	static inline bool samsung_dma_is_dmadev(void)
	59	{
	60	return false;
	61	}
	62
	63	#include <plat/dma.h>
	64
505788cc BD	65	#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
505788cc BD	66
1da177e4	67	/* we have 4 dma channels */
7cfdee9f	68	#if !defined(CONFIG_CPU_S3C2443) && !defined(CONFIG_CPU_S3C2416)
97c1b145	69	#define S3C_DMA_CHANNELS (4)
15e4db7b	70	#else
97c1b145	71	#define S3C_DMA_CHANNELS (6)
15e4db7b	72	#endif
1da177e4 LT	73
	74	/* types */
	75
f105a7df	76	enum s3c2410_dma_state {
1da177e4 LT	77	S3C2410_DMA_IDLE,
	78	S3C2410_DMA_RUNNING,
	79	S3C2410_DMA_PAUSED
f105a7df	80	};
1da177e4	81
f105a7df	82	/* enum s3c2410_dma_loadst
1da177e4 LT	83	*
	84	* This represents the state of the DMA engine, wrt to the loaded / running
	85	* transfers. Since we don't have any way of knowing exactly the state of
	86	* the DMA transfers, we need to know the state to make decisions on wether
	87	* we can
	88	*
	89	* S3C2410_DMA_NONE
	90	*
	91	* There are no buffers loaded (the channel should be inactive)
	92	*
	93	* S3C2410_DMA_1LOADED
	94	*
	95	* There is one buffer loaded, however it has not been confirmed to be
	96	* loaded by the DMA engine. This may be because the channel is not
	97	* yet running, or the DMA driver decided that it was too costly to
	98	* sit and wait for it to happen.
	99	*
	100	* S3C2410_DMA_1RUNNING
	101	*
	102	* The buffer has been confirmed running, and not finisged
	103	*
	104	* S3C2410_DMA_1LOADED_1RUNNING
	105	*
	106	* There is a buffer waiting to be loaded by the DMA engine, and one
	107	* currently running.
	108	*/
	109
f105a7df	110	enum s3c2410_dma_loadst {
1da177e4 LT	111	S3C2410_DMALOAD_NONE,
	112	S3C2410_DMALOAD_1LOADED,
	113	S3C2410_DMALOAD_1RUNNING,
	114	S3C2410_DMALOAD_1LOADED_1RUNNING,
f105a7df	115	};
1da177e4	116
1da177e4	117
1da177e4 LT	118	/* flags */
	119
	120	#define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about
	121	* waiting for reloads */
	122	#define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */
	123
e3d80248 BD	124	#define S3C2410_DMAF_CIRCULAR (1 << 2) /* no circular dma support */
e3d80248 BD	125
1da177e4 LT	126	/* dma buffer */
1da177e4 LT	127
c133c290	128	struct s3c2410_dma_buf;
1da177e4	129
c133c290	130	/* s3c2410_dma_buf
1da177e4 LT	131	*
	132	* internally used buffer structure to describe a queued or running
	133	* buffer.
	134	*/
	135
f105a7df	136	struct s3c2410_dma_buf {
57bcdafc BD	137	struct s3c2410_dma_buf *next;
	138	int magic; /* magic */
	139	int size; /* buffer size in bytes */
	140	dma_addr_t data; /* start of DMA data */
	141	dma_addr_t ptr; /* where the DMA got to [1] */
	142	void id; / client's id */
1da177e4 LT	143	};
	144
	145	/* [1] is this updated for both recv/send modes? */
	146
f105a7df	147	struct s3c2410_dma_stats {
57bcdafc BD	148	unsigned long loads;
	149	unsigned long timeout_longest;
	150	unsigned long timeout_shortest;
	151	unsigned long timeout_avg;
	152	unsigned long timeout_failed;
1da177e4 LT	153	};
1da177e4 LT	154
505788cc BD	155	struct s3c2410_dma_map;
505788cc BD	156
f105a7df	157	/* struct s3c2410_dma_chan
1da177e4 LT	158	*
	159	* full state information for each DMA channel
	160	*/
	161
f105a7df	162	struct s3c2410_dma_chan {
1da177e4	163	/* channel state flags and information */
57bcdafc BD	164	unsigned char number; /* number of this dma channel */
	165	unsigned char in_use; /* channel allocated */
	166	unsigned char irq_claimed; /* irq claimed for channel */
	167	unsigned char irq_enabled; /* irq enabled for channel */
	168	unsigned char xfer_unit; /* size of an transfer */
1da177e4 LT	169
	170	/* channel state */
	171
57bcdafc BD	172	enum s3c2410_dma_state state;
	173	enum s3c2410_dma_loadst load_state;
	174	struct s3c2410_dma_client *client;
1da177e4 LT	175
1da177e4 LT	176	/* channel configuration */
51ddf31d	177	enum dma_data_direction source;
8970ef47	178	enum dma_ch req_ch;
57bcdafc BD	179	unsigned long dev_addr;
	180	unsigned long load_timeout;
	181	unsigned int flags; /* channel flags */
1da177e4	182
505788cc BD	183	struct s3c24xx_dma_map map; / channel hw maps */
505788cc BD	184
1da177e4	185	/* channel's hardware position and configuration */
57bcdafc BD	186	void __iomem regs; / channels registers */
	187	void __iomem addr_reg; / data address register */
	188	unsigned int irq; /* channel irq */
	189	unsigned long dcon; /* default value of DCON */
1da177e4 LT	190
1da177e4 LT	191	/* driver handles */
57bcdafc BD	192	s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */
57bcdafc BD	193	s3c2410_dma_opfn_t op_fn; /* channel op callback */
1da177e4 LT	194
1da177e4 LT	195	/* stats gathering */
57bcdafc BD	196	struct s3c2410_dma_stats *stats;
57bcdafc BD	197	struct s3c2410_dma_stats stats_store;
1da177e4 LT	198
1da177e4 LT	199	/* buffer list and information */
57bcdafc BD	200	struct s3c2410_dma_buf curr; / current dma buffer */
	201	struct s3c2410_dma_buf next; / next buffer to load */
	202	struct s3c2410_dma_buf end; / end of queue */
1da177e4 LT	203
	204	/* system device */
	205	struct sys_device dev;
	206	};
	207
1da177e4 LT	208	typedef unsigned long dma_device_t;
1da177e4 LT	209
1da177e4	210	#endif /* __ASM_ARCH_DMA_H */