Commit | Line | Data |
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a09e64fb | 1 | /* arch/arm/mach-s3c2410/include/mach/regs-gpio.h |
1da177e4 LT |
2 | * |
3 | * Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk> | |
4 | * http://www.simtec.co.uk/products/SWLINUX/ | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * S3C2410 GPIO register definitions | |
1da177e4 LT |
11 | */ |
12 | ||
13 | ||
14 | #ifndef __ASM_ARCH_REGS_GPIO_H | |
66bfa2f0 | 15 | #define __ASM_ARCH_REGS_GPIO_H |
1da177e4 | 16 | |
67c2addc | 17 | #include <mach/gpio-nrs.h> |
1da177e4 | 18 | |
0ca5bc3d LCVR |
19 | #ifdef CONFIG_CPU_S3C2400 |
20 | #define S3C24XX_GPIO_BASE(x) S3C2400_GPIO_BASE(x) | |
21 | #define S3C24XX_MISCCR S3C2400_MISCCR | |
22 | #else | |
23 | #define S3C24XX_GPIO_BASE(x) S3C2410_GPIO_BASE(x) | |
68d9ab39 | 24 | #define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80) |
0ca5bc3d LCVR |
25 | #endif /* CONFIG_CPU_S3C2400 */ |
26 | ||
27 | ||
28 | /* S3C2400 doesn't have a 1:1 mapping to S3C2410 gpio base pins */ | |
29 | ||
30 | #define S3C2400_BANKNUM(pin) (((pin) & ~31) / 32) | |
31 | #define S3C2400_BASEA2B(pin) ((((pin) & ~31) >> 2)) | |
32 | #define S3C2400_BASEC2H(pin) ((S3C2400_BANKNUM(pin) * 10) + \ | |
33 | (2 * (S3C2400_BANKNUM(pin)-2))) | |
34 | ||
35 | #define S3C2400_GPIO_BASE(pin) (pin < S3C2410_GPIO_BANKC ? \ | |
36 | S3C2400_BASEA2B(pin)+S3C24XX_VA_GPIO : \ | |
37 | S3C2400_BASEC2H(pin)+S3C24XX_VA_GPIO) | |
38 | ||
39 | ||
1da177e4 LT |
40 | #define S3C2410_GPIO_BASE(pin) ((((pin) & ~31) >> 1) + S3C24XX_VA_GPIO) |
41 | #define S3C2410_GPIO_OFFSET(pin) ((pin) & 31) | |
42 | ||
43 | /* general configuration options */ | |
44 | ||
45 | #define S3C2410_GPIO_LEAVE (0xFFFFFFFF) | |
6c3c5bb3 | 46 | #define S3C2410_GPIO_INPUT (0xFFFFFFF0) /* not available on A */ |
42d3a120 BD |
47 | #define S3C2410_GPIO_OUTPUT (0xFFFFFFF1) |
48 | #define S3C2410_GPIO_IRQ (0xFFFFFFF2) /* not available for all */ | |
6c3c5bb3 | 49 | #define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* bank A => addr/cs/nand */ |
42d3a120 | 50 | #define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */ |
1da177e4 | 51 | |
68d9ab39 BD |
52 | /* register address for the GPIO registers. |
53 | * S3C24XX_GPIOREG2 is for the second set of registers in the | |
54 | * GPIO which move between s3c2410 and s3c2412 type systems */ | |
1da177e4 LT |
55 | |
56 | #define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO) | |
68d9ab39 BD |
57 | #define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2) |
58 | ||
59 | ||
60 | /* configure GPIO ports A..G */ | |
1da177e4 | 61 | |
192cdc58 LCVR |
62 | /* port A - S3C2410: 22bits, zero in bit X makes pin X output |
63 | * S3C2400: 18bits, zero in bit X makes pin X output | |
1da177e4 LT |
64 | * 1 makes port special function, this is default |
65 | */ | |
66 | #define S3C2410_GPACON S3C2410_GPIOREG(0x00) | |
67 | #define S3C2410_GPADAT S3C2410_GPIOREG(0x04) | |
68 | ||
192cdc58 LCVR |
69 | #define S3C2400_GPACON S3C2410_GPIOREG(0x00) |
70 | #define S3C2400_GPADAT S3C2410_GPIOREG(0x04) | |
71 | ||
1da177e4 LT |
72 | #define S3C2410_GPA0_ADDR0 (1<<0) |
73 | ||
1da177e4 LT |
74 | #define S3C2410_GPA1_ADDR16 (1<<1) |
75 | ||
1da177e4 LT |
76 | #define S3C2410_GPA2_ADDR17 (1<<2) |
77 | ||
1da177e4 LT |
78 | #define S3C2410_GPA3_ADDR18 (1<<3) |
79 | ||
1da177e4 LT |
80 | #define S3C2410_GPA4_ADDR19 (1<<4) |
81 | ||
1da177e4 LT |
82 | #define S3C2410_GPA5_ADDR20 (1<<5) |
83 | ||
1da177e4 LT |
84 | #define S3C2410_GPA6_ADDR21 (1<<6) |
85 | ||
1da177e4 LT |
86 | #define S3C2410_GPA7_ADDR22 (1<<7) |
87 | ||
1da177e4 LT |
88 | #define S3C2410_GPA8_ADDR23 (1<<8) |
89 | ||
1da177e4 LT |
90 | #define S3C2410_GPA9_ADDR24 (1<<9) |
91 | ||
1da177e4 | 92 | #define S3C2410_GPA10_ADDR25 (1<<10) |
192cdc58 | 93 | #define S3C2400_GPA10_SCKE (1<<10) |
1da177e4 | 94 | |
1da177e4 | 95 | #define S3C2410_GPA11_ADDR26 (1<<11) |
192cdc58 | 96 | #define S3C2400_GPA11_nCAS0 (1<<11) |
1da177e4 | 97 | |
1da177e4 | 98 | #define S3C2410_GPA12_nGCS1 (1<<12) |
192cdc58 | 99 | #define S3C2400_GPA12_nCAS1 (1<<12) |
1da177e4 | 100 | |
1da177e4 | 101 | #define S3C2410_GPA13_nGCS2 (1<<13) |
192cdc58 | 102 | #define S3C2400_GPA13_nGCS1 (1<<13) |
1da177e4 | 103 | |
1da177e4 | 104 | #define S3C2410_GPA14_nGCS3 (1<<14) |
192cdc58 | 105 | #define S3C2400_GPA14_nGCS2 (1<<14) |
1da177e4 | 106 | |
1da177e4 | 107 | #define S3C2410_GPA15_nGCS4 (1<<15) |
192cdc58 | 108 | #define S3C2400_GPA15_nGCS3 (1<<15) |
1da177e4 | 109 | |
1da177e4 | 110 | #define S3C2410_GPA16_nGCS5 (1<<16) |
192cdc58 | 111 | #define S3C2400_GPA16_nGCS4 (1<<16) |
1da177e4 | 112 | |
1da177e4 | 113 | #define S3C2410_GPA17_CLE (1<<17) |
192cdc58 | 114 | #define S3C2400_GPA17_nGCS5 (1<<17) |
1da177e4 | 115 | |
1da177e4 LT |
116 | #define S3C2410_GPA18_ALE (1<<18) |
117 | ||
1da177e4 LT |
118 | #define S3C2410_GPA19_nFWE (1<<19) |
119 | ||
1da177e4 LT |
120 | #define S3C2410_GPA20_nFRE (1<<20) |
121 | ||
1da177e4 LT |
122 | #define S3C2410_GPA21_nRSTOUT (1<<21) |
123 | ||
1da177e4 LT |
124 | #define S3C2410_GPA22_nFCE (1<<22) |
125 | ||
192cdc58 | 126 | /* 0x08 and 0x0c are reserved on S3C2410 */ |
1da177e4 | 127 | |
192cdc58 LCVR |
128 | /* S3C2410: |
129 | * GPB is 10 IO pins, each configured by 2 bits each in GPBCON. | |
1da177e4 | 130 | * 00 = input, 01 = output, 10=special function, 11=reserved |
192cdc58 LCVR |
131 | |
132 | * S3C2400: | |
133 | * GPB is 16 IO pins, each configured by 2 bits each in GPBCON. | |
134 | * 00 = input, 01 = output, 10=data, 11=special function | |
135 | ||
1da177e4 LT |
136 | * bit 0,1 = pin 0, 2,3= pin 1... |
137 | * | |
138 | * CPBUP = pull up resistor control, 1=disabled, 0=enabled | |
139 | */ | |
140 | ||
141 | #define S3C2410_GPBCON S3C2410_GPIOREG(0x10) | |
142 | #define S3C2410_GPBDAT S3C2410_GPIOREG(0x14) | |
143 | #define S3C2410_GPBUP S3C2410_GPIOREG(0x18) | |
144 | ||
192cdc58 LCVR |
145 | #define S3C2400_GPBCON S3C2410_GPIOREG(0x08) |
146 | #define S3C2400_GPBDAT S3C2410_GPIOREG(0x0C) | |
147 | #define S3C2400_GPBUP S3C2410_GPIOREG(0x10) | |
148 | ||
6619d58a | 149 | /* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */ |
1da177e4 | 150 | |
1da177e4 | 151 | #define S3C2410_GPB0_TOUT0 (0x02 << 0) |
192cdc58 | 152 | #define S3C2400_GPB0_DATA16 (0x02 << 0) |
1da177e4 | 153 | |
1da177e4 | 154 | #define S3C2410_GPB1_TOUT1 (0x02 << 2) |
192cdc58 | 155 | #define S3C2400_GPB1_DATA17 (0x02 << 2) |
1da177e4 | 156 | |
1da177e4 | 157 | #define S3C2410_GPB2_TOUT2 (0x02 << 4) |
192cdc58 LCVR |
158 | #define S3C2400_GPB2_DATA18 (0x02 << 4) |
159 | #define S3C2400_GPB2_TCLK1 (0x03 << 4) | |
1da177e4 | 160 | |
1da177e4 | 161 | #define S3C2410_GPB3_TOUT3 (0x02 << 6) |
192cdc58 LCVR |
162 | #define S3C2400_GPB3_DATA19 (0x02 << 6) |
163 | #define S3C2400_GPB3_TXD1 (0x03 << 6) | |
1da177e4 | 164 | |
1da177e4 | 165 | #define S3C2410_GPB4_TCLK0 (0x02 << 8) |
192cdc58 | 166 | #define S3C2400_GPB4_DATA20 (0x02 << 8) |
1da177e4 | 167 | #define S3C2410_GPB4_MASK (0x03 << 8) |
192cdc58 LCVR |
168 | #define S3C2400_GPB4_RXD1 (0x03 << 8) |
169 | #define S3C2400_GPB4_MASK (0x03 << 8) | |
1da177e4 | 170 | |
1da177e4 | 171 | #define S3C2410_GPB5_nXBACK (0x02 << 10) |
6619d58a | 172 | #define S3C2443_GPB5_XBACK (0x03 << 10) |
192cdc58 LCVR |
173 | #define S3C2400_GPB5_DATA21 (0x02 << 10) |
174 | #define S3C2400_GPB5_nCTS1 (0x03 << 10) | |
1da177e4 | 175 | |
1da177e4 | 176 | #define S3C2410_GPB6_nXBREQ (0x02 << 12) |
6619d58a | 177 | #define S3C2443_GPB6_XBREQ (0x03 << 12) |
192cdc58 LCVR |
178 | #define S3C2400_GPB6_DATA22 (0x02 << 12) |
179 | #define S3C2400_GPB6_nRTS1 (0x03 << 12) | |
1da177e4 | 180 | |
1da177e4 | 181 | #define S3C2410_GPB7_nXDACK1 (0x02 << 14) |
6619d58a | 182 | #define S3C2443_GPB7_XDACK1 (0x03 << 14) |
192cdc58 | 183 | #define S3C2400_GPB7_DATA23 (0x02 << 14) |
1da177e4 | 184 | |
1da177e4 | 185 | #define S3C2410_GPB8_nXDREQ1 (0x02 << 16) |
192cdc58 | 186 | #define S3C2400_GPB8_DATA24 (0x02 << 16) |
1da177e4 | 187 | |
1da177e4 | 188 | #define S3C2410_GPB9_nXDACK0 (0x02 << 18) |
6619d58a | 189 | #define S3C2443_GPB9_XDACK0 (0x03 << 18) |
192cdc58 LCVR |
190 | #define S3C2400_GPB9_DATA25 (0x02 << 18) |
191 | #define S3C2400_GPB9_I2SSDI (0x03 << 18) | |
1da177e4 | 192 | |
1da177e4 | 193 | #define S3C2410_GPB10_nXDRE0 (0x02 << 20) |
6619d58a | 194 | #define S3C2443_GPB10_XDREQ0 (0x03 << 20) |
192cdc58 LCVR |
195 | #define S3C2400_GPB10_DATA26 (0x02 << 20) |
196 | #define S3C2400_GPB10_nSS (0x03 << 20) | |
197 | ||
192cdc58 LCVR |
198 | #define S3C2400_GPB11_INP (0x00 << 22) |
199 | #define S3C2400_GPB11_OUTP (0x01 << 22) | |
200 | #define S3C2400_GPB11_DATA27 (0x02 << 22) | |
201 | ||
192cdc58 LCVR |
202 | #define S3C2400_GPB12_INP (0x00 << 24) |
203 | #define S3C2400_GPB12_OUTP (0x01 << 24) | |
204 | #define S3C2400_GPB12_DATA28 (0x02 << 24) | |
205 | ||
192cdc58 LCVR |
206 | #define S3C2400_GPB13_INP (0x00 << 26) |
207 | #define S3C2400_GPB13_OUTP (0x01 << 26) | |
208 | #define S3C2400_GPB13_DATA29 (0x02 << 26) | |
209 | ||
192cdc58 LCVR |
210 | #define S3C2400_GPB14_INP (0x00 << 28) |
211 | #define S3C2400_GPB14_OUTP (0x01 << 28) | |
212 | #define S3C2400_GPB14_DATA30 (0x02 << 28) | |
213 | ||
192cdc58 LCVR |
214 | #define S3C2400_GPB15_INP (0x00 << 30) |
215 | #define S3C2400_GPB15_OUTP (0x01 << 30) | |
216 | #define S3C2400_GPB15_DATA31 (0x02 << 30) | |
217 | ||
218 | #define S3C2410_GPB_PUPDIS(x) (1<<(x)) | |
1da177e4 LT |
219 | |
220 | /* Port C consits of 16 GPIO/Special function | |
221 | * | |
222 | * almost identical setup to port b, but the special functions are mostly | |
223 | * to do with the video system's sync/etc. | |
224 | */ | |
225 | ||
226 | #define S3C2410_GPCCON S3C2410_GPIOREG(0x20) | |
227 | #define S3C2410_GPCDAT S3C2410_GPIOREG(0x24) | |
228 | #define S3C2410_GPCUP S3C2410_GPIOREG(0x28) | |
229 | ||
192cdc58 LCVR |
230 | #define S3C2400_GPCCON S3C2410_GPIOREG(0x14) |
231 | #define S3C2400_GPCDAT S3C2410_GPIOREG(0x18) | |
232 | #define S3C2400_GPCUP S3C2410_GPIOREG(0x1C) | |
233 | ||
1da177e4 | 234 | #define S3C2410_GPC0_LEND (0x02 << 0) |
192cdc58 | 235 | #define S3C2400_GPC0_VD0 (0x02 << 0) |
1da177e4 | 236 | |
1da177e4 | 237 | #define S3C2410_GPC1_VCLK (0x02 << 2) |
192cdc58 | 238 | #define S3C2400_GPC1_VD1 (0x02 << 2) |
1da177e4 | 239 | |
1da177e4 | 240 | #define S3C2410_GPC2_VLINE (0x02 << 4) |
192cdc58 | 241 | #define S3C2400_GPC2_VD2 (0x02 << 4) |
1da177e4 | 242 | |
1da177e4 | 243 | #define S3C2410_GPC3_VFRAME (0x02 << 6) |
192cdc58 | 244 | #define S3C2400_GPC3_VD3 (0x02 << 6) |
1da177e4 | 245 | |
1da177e4 | 246 | #define S3C2410_GPC4_VM (0x02 << 8) |
192cdc58 | 247 | #define S3C2400_GPC4_VD4 (0x02 << 8) |
1da177e4 | 248 | |
1da177e4 | 249 | #define S3C2410_GPC5_LCDVF0 (0x02 << 10) |
192cdc58 | 250 | #define S3C2400_GPC5_VD5 (0x02 << 10) |
1da177e4 | 251 | |
1da177e4 | 252 | #define S3C2410_GPC6_LCDVF1 (0x02 << 12) |
192cdc58 | 253 | #define S3C2400_GPC6_VD6 (0x02 << 12) |
1da177e4 | 254 | |
1da177e4 | 255 | #define S3C2410_GPC7_LCDVF2 (0x02 << 14) |
192cdc58 | 256 | #define S3C2400_GPC7_VD7 (0x02 << 14) |
1da177e4 | 257 | |
1da177e4 | 258 | #define S3C2410_GPC8_VD0 (0x02 << 16) |
192cdc58 | 259 | #define S3C2400_GPC8_VD8 (0x02 << 16) |
1da177e4 | 260 | |
1da177e4 | 261 | #define S3C2410_GPC9_VD1 (0x02 << 18) |
192cdc58 | 262 | #define S3C2400_GPC9_VD9 (0x02 << 18) |
1da177e4 | 263 | |
1da177e4 | 264 | #define S3C2410_GPC10_VD2 (0x02 << 20) |
192cdc58 | 265 | #define S3C2400_GPC10_VD10 (0x02 << 20) |
1da177e4 | 266 | |
1da177e4 | 267 | #define S3C2410_GPC11_VD3 (0x02 << 22) |
192cdc58 | 268 | #define S3C2400_GPC11_VD11 (0x02 << 22) |
1da177e4 | 269 | |
1da177e4 | 270 | #define S3C2410_GPC12_VD4 (0x02 << 24) |
192cdc58 | 271 | #define S3C2400_GPC12_VD12 (0x02 << 24) |
1da177e4 | 272 | |
1da177e4 | 273 | #define S3C2410_GPC13_VD5 (0x02 << 26) |
192cdc58 | 274 | #define S3C2400_GPC13_VD13 (0x02 << 26) |
1da177e4 | 275 | |
1da177e4 | 276 | #define S3C2410_GPC14_VD6 (0x02 << 28) |
192cdc58 | 277 | #define S3C2400_GPC14_VD14 (0x02 << 28) |
1da177e4 | 278 | |
1da177e4 | 279 | #define S3C2410_GPC15_VD7 (0x02 << 30) |
192cdc58 LCVR |
280 | #define S3C2400_GPC15_VD15 (0x02 << 30) |
281 | ||
282 | #define S3C2410_GPC_PUPDIS(x) (1<<(x)) | |
1da177e4 | 283 | |
192cdc58 LCVR |
284 | /* |
285 | * S3C2410: Port D consists of 16 GPIO/Special function | |
1da177e4 LT |
286 | * |
287 | * almost identical setup to port b, but the special functions are mostly | |
288 | * to do with the video system's data. | |
192cdc58 LCVR |
289 | * |
290 | * S3C2400: Port D consists of 11 GPIO/Special function | |
291 | * | |
292 | * almost identical setup to port c | |
1da177e4 LT |
293 | */ |
294 | ||
295 | #define S3C2410_GPDCON S3C2410_GPIOREG(0x30) | |
296 | #define S3C2410_GPDDAT S3C2410_GPIOREG(0x34) | |
297 | #define S3C2410_GPDUP S3C2410_GPIOREG(0x38) | |
298 | ||
192cdc58 LCVR |
299 | #define S3C2400_GPDCON S3C2410_GPIOREG(0x20) |
300 | #define S3C2400_GPDDAT S3C2410_GPIOREG(0x24) | |
301 | #define S3C2400_GPDUP S3C2410_GPIOREG(0x28) | |
302 | ||
1da177e4 | 303 | #define S3C2410_GPD0_VD8 (0x02 << 0) |
192cdc58 | 304 | #define S3C2400_GPD0_VFRAME (0x02 << 0) |
96ce2385 | 305 | #define S3C2442_GPD0_nSPICS1 (0x03 << 0) |
1da177e4 | 306 | |
1da177e4 | 307 | #define S3C2410_GPD1_VD9 (0x02 << 2) |
192cdc58 | 308 | #define S3C2400_GPD1_VM (0x02 << 2) |
96ce2385 | 309 | #define S3C2442_GPD1_SPICLK1 (0x03 << 2) |
1da177e4 | 310 | |
1da177e4 | 311 | #define S3C2410_GPD2_VD10 (0x02 << 4) |
192cdc58 | 312 | #define S3C2400_GPD2_VLINE (0x02 << 4) |
1da177e4 | 313 | |
1da177e4 | 314 | #define S3C2410_GPD3_VD11 (0x02 << 6) |
192cdc58 | 315 | #define S3C2400_GPD3_VCLK (0x02 << 6) |
1da177e4 | 316 | |
1da177e4 | 317 | #define S3C2410_GPD4_VD12 (0x02 << 8) |
192cdc58 | 318 | #define S3C2400_GPD4_LEND (0x02 << 8) |
1da177e4 | 319 | |
1da177e4 | 320 | #define S3C2410_GPD5_VD13 (0x02 << 10) |
192cdc58 | 321 | #define S3C2400_GPD5_TOUT0 (0x02 << 10) |
1da177e4 | 322 | |
1da177e4 | 323 | #define S3C2410_GPD6_VD14 (0x02 << 12) |
192cdc58 | 324 | #define S3C2400_GPD6_TOUT1 (0x02 << 12) |
1da177e4 | 325 | |
1da177e4 | 326 | #define S3C2410_GPD7_VD15 (0x02 << 14) |
192cdc58 | 327 | #define S3C2400_GPD7_TOUT2 (0x02 << 14) |
1da177e4 | 328 | |
1da177e4 | 329 | #define S3C2410_GPD8_VD16 (0x02 << 16) |
192cdc58 | 330 | #define S3C2400_GPD8_TOUT3 (0x02 << 16) |
1da177e4 | 331 | |
1da177e4 | 332 | #define S3C2410_GPD9_VD17 (0x02 << 18) |
192cdc58 LCVR |
333 | #define S3C2400_GPD9_TCLK0 (0x02 << 18) |
334 | #define S3C2410_GPD9_MASK (0x03 << 18) | |
1da177e4 | 335 | |
1da177e4 | 336 | #define S3C2410_GPD10_VD18 (0x02 << 20) |
192cdc58 | 337 | #define S3C2400_GPD10_nWAIT (0x02 << 20) |
1da177e4 | 338 | |
1da177e4 LT |
339 | #define S3C2410_GPD11_VD19 (0x02 << 22) |
340 | ||
1da177e4 LT |
341 | #define S3C2410_GPD12_VD20 (0x02 << 24) |
342 | ||
1da177e4 LT |
343 | #define S3C2410_GPD13_VD21 (0x02 << 26) |
344 | ||
1da177e4 | 345 | #define S3C2410_GPD14_VD22 (0x02 << 28) |
de56a2f9 | 346 | #define S3C2410_GPD14_nSS1 (0x03 << 28) |
1da177e4 | 347 | |
1da177e4 | 348 | #define S3C2410_GPD15_VD23 (0x02 << 30) |
de56a2f9 | 349 | #define S3C2410_GPD15_nSS0 (0x03 << 30) |
1da177e4 | 350 | |
192cdc58 LCVR |
351 | #define S3C2410_GPD_PUPDIS(x) (1<<(x)) |
352 | ||
353 | /* S3C2410: | |
354 | * Port E consists of 16 GPIO/Special function | |
1da177e4 LT |
355 | * |
356 | * again, the same as port B, but dealing with I2S, SDI, and | |
357 | * more miscellaneous functions | |
192cdc58 LCVR |
358 | * |
359 | * S3C2400: | |
360 | * Port E consists of 12 GPIO/Special function | |
361 | * | |
362 | * GPIO / interrupt inputs | |
1da177e4 LT |
363 | */ |
364 | ||
365 | #define S3C2410_GPECON S3C2410_GPIOREG(0x40) | |
366 | #define S3C2410_GPEDAT S3C2410_GPIOREG(0x44) | |
367 | #define S3C2410_GPEUP S3C2410_GPIOREG(0x48) | |
368 | ||
192cdc58 LCVR |
369 | #define S3C2400_GPECON S3C2410_GPIOREG(0x2C) |
370 | #define S3C2400_GPEDAT S3C2410_GPIOREG(0x30) | |
371 | #define S3C2400_GPEUP S3C2410_GPIOREG(0x34) | |
372 | ||
1da177e4 | 373 | #define S3C2410_GPE0_I2SLRCK (0x02 << 0) |
6619d58a | 374 | #define S3C2443_GPE0_AC_nRESET (0x03 << 0) |
192cdc58 | 375 | #define S3C2400_GPE0_EINT0 (0x02 << 0) |
1da177e4 LT |
376 | #define S3C2410_GPE0_MASK (0x03 << 0) |
377 | ||
1da177e4 | 378 | #define S3C2410_GPE1_I2SSCLK (0x02 << 2) |
6619d58a | 379 | #define S3C2443_GPE1_AC_SYNC (0x03 << 2) |
192cdc58 LCVR |
380 | #define S3C2400_GPE1_EINT1 (0x02 << 2) |
381 | #define S3C2400_GPE1_nSS (0x03 << 2) | |
1da177e4 LT |
382 | #define S3C2410_GPE1_MASK (0x03 << 2) |
383 | ||
1da177e4 | 384 | #define S3C2410_GPE2_CDCLK (0x02 << 4) |
6619d58a | 385 | #define S3C2443_GPE2_AC_BITCLK (0x03 << 4) |
192cdc58 LCVR |
386 | #define S3C2400_GPE2_EINT2 (0x02 << 4) |
387 | #define S3C2400_GPE2_I2SSDI (0x03 << 4) | |
1da177e4 | 388 | |
1da177e4 | 389 | #define S3C2410_GPE3_I2SSDI (0x02 << 6) |
6619d58a | 390 | #define S3C2443_GPE3_AC_SDI (0x03 << 6) |
192cdc58 LCVR |
391 | #define S3C2400_GPE3_EINT3 (0x02 << 6) |
392 | #define S3C2400_GPE3_nCTS1 (0x03 << 6) | |
1da177e4 LT |
393 | #define S3C2410_GPE3_nSS0 (0x03 << 6) |
394 | #define S3C2410_GPE3_MASK (0x03 << 6) | |
395 | ||
1da177e4 | 396 | #define S3C2410_GPE4_I2SSDO (0x02 << 8) |
6619d58a | 397 | #define S3C2443_GPE4_AC_SDO (0x03 << 8) |
192cdc58 LCVR |
398 | #define S3C2400_GPE4_EINT4 (0x02 << 8) |
399 | #define S3C2400_GPE4_nRTS1 (0x03 << 8) | |
1da177e4 LT |
400 | #define S3C2410_GPE4_I2SSDI (0x03 << 8) |
401 | #define S3C2410_GPE4_MASK (0x03 << 8) | |
402 | ||
1da177e4 | 403 | #define S3C2410_GPE5_SDCLK (0x02 << 10) |
6619d58a | 404 | #define S3C2443_GPE5_SD1_CLK (0x02 << 10) |
192cdc58 LCVR |
405 | #define S3C2400_GPE5_EINT5 (0x02 << 10) |
406 | #define S3C2400_GPE5_TCLK1 (0x03 << 10) | |
1da177e4 | 407 | |
1da177e4 | 408 | #define S3C2410_GPE6_SDCMD (0x02 << 12) |
6619d58a BD |
409 | #define S3C2443_GPE6_SD1_CMD (0x02 << 12) |
410 | #define S3C2443_GPE6_AC_BITCLK (0x03 << 12) | |
192cdc58 | 411 | #define S3C2400_GPE6_EINT6 (0x02 << 12) |
1da177e4 | 412 | |
1da177e4 | 413 | #define S3C2410_GPE7_SDDAT0 (0x02 << 14) |
6619d58a BD |
414 | #define S3C2443_GPE5_SD1_DAT0 (0x02 << 14) |
415 | #define S3C2443_GPE7_AC_SDI (0x03 << 14) | |
192cdc58 | 416 | #define S3C2400_GPE7_EINT7 (0x02 << 14) |
1da177e4 | 417 | |
1da177e4 | 418 | #define S3C2410_GPE8_SDDAT1 (0x02 << 16) |
6619d58a BD |
419 | #define S3C2443_GPE8_SD1_DAT1 (0x02 << 16) |
420 | #define S3C2443_GPE8_AC_SDO (0x03 << 16) | |
192cdc58 | 421 | #define S3C2400_GPE8_nXDACK0 (0x02 << 16) |
1da177e4 | 422 | |
1da177e4 | 423 | #define S3C2410_GPE9_SDDAT2 (0x02 << 18) |
6619d58a BD |
424 | #define S3C2443_GPE9_SD1_DAT2 (0x02 << 18) |
425 | #define S3C2443_GPE9_AC_SYNC (0x03 << 18) | |
192cdc58 LCVR |
426 | #define S3C2400_GPE9_nXDACK1 (0x02 << 18) |
427 | #define S3C2400_GPE9_nXBACK (0x03 << 18) | |
1da177e4 | 428 | |
1da177e4 | 429 | #define S3C2410_GPE10_SDDAT3 (0x02 << 20) |
6619d58a BD |
430 | #define S3C2443_GPE10_SD1_DAT3 (0x02 << 20) |
431 | #define S3C2443_GPE10_AC_nRESET (0x03 << 20) | |
192cdc58 | 432 | #define S3C2400_GPE10_nXDREQ0 (0x02 << 20) |
1da177e4 | 433 | |
1da177e4 | 434 | #define S3C2410_GPE11_SPIMISO0 (0x02 << 22) |
192cdc58 LCVR |
435 | #define S3C2400_GPE11_nXDREQ1 (0x02 << 22) |
436 | #define S3C2400_GPE11_nXBREQ (0x03 << 22) | |
1da177e4 | 437 | |
1da177e4 LT |
438 | #define S3C2410_GPE12_SPIMOSI0 (0x02 << 24) |
439 | ||
1da177e4 LT |
440 | #define S3C2410_GPE13_SPICLK0 (0x02 << 26) |
441 | ||
1da177e4 LT |
442 | #define S3C2410_GPE14_IICSCL (0x02 << 28) |
443 | #define S3C2410_GPE14_MASK (0x03 << 28) | |
444 | ||
1da177e4 LT |
445 | #define S3C2410_GPE15_IICSDA (0x02 << 30) |
446 | #define S3C2410_GPE15_MASK (0x03 << 30) | |
447 | ||
448 | #define S3C2440_GPE0_ACSYNC (0x03 << 0) | |
449 | #define S3C2440_GPE1_ACBITCLK (0x03 << 2) | |
450 | #define S3C2440_GPE2_ACRESET (0x03 << 4) | |
451 | #define S3C2440_GPE3_ACIN (0x03 << 6) | |
452 | #define S3C2440_GPE4_ACOUT (0x03 << 8) | |
453 | ||
454 | #define S3C2410_GPE_PUPDIS(x) (1<<(x)) | |
455 | ||
192cdc58 LCVR |
456 | /* S3C2410: |
457 | * Port F consists of 8 GPIO/Special function | |
1da177e4 LT |
458 | * |
459 | * GPIO / interrupt inputs | |
460 | * | |
461 | * GPFCON has 2 bits for each of the input pins on port F | |
462 | * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined | |
463 | * | |
464 | * pull up works like all other ports. | |
192cdc58 LCVR |
465 | * |
466 | * S3C2400: | |
467 | * Port F consists of 7 GPIO/Special function | |
468 | * | |
469 | * GPIO/serial/misc pins | |
1da177e4 LT |
470 | */ |
471 | ||
472 | #define S3C2410_GPFCON S3C2410_GPIOREG(0x50) | |
473 | #define S3C2410_GPFDAT S3C2410_GPIOREG(0x54) | |
474 | #define S3C2410_GPFUP S3C2410_GPIOREG(0x58) | |
475 | ||
192cdc58 LCVR |
476 | #define S3C2400_GPFCON S3C2410_GPIOREG(0x38) |
477 | #define S3C2400_GPFDAT S3C2410_GPIOREG(0x3C) | |
478 | #define S3C2400_GPFUP S3C2410_GPIOREG(0x40) | |
479 | ||
1da177e4 | 480 | #define S3C2410_GPF0_EINT0 (0x02 << 0) |
192cdc58 | 481 | #define S3C2400_GPF0_RXD0 (0x02 << 0) |
1da177e4 | 482 | |
1da177e4 | 483 | #define S3C2410_GPF1_EINT1 (0x02 << 2) |
192cdc58 LCVR |
484 | #define S3C2400_GPF1_RXD1 (0x02 << 2) |
485 | #define S3C2400_GPF1_IICSDA (0x03 << 2) | |
1da177e4 | 486 | |
1da177e4 | 487 | #define S3C2410_GPF2_EINT2 (0x02 << 4) |
192cdc58 | 488 | #define S3C2400_GPF2_TXD0 (0x02 << 4) |
1da177e4 | 489 | |
1da177e4 | 490 | #define S3C2410_GPF3_EINT3 (0x02 << 6) |
192cdc58 LCVR |
491 | #define S3C2400_GPF3_TXD1 (0x02 << 6) |
492 | #define S3C2400_GPF3_IICSCL (0x03 << 6) | |
1da177e4 | 493 | |
1da177e4 | 494 | #define S3C2410_GPF4_EINT4 (0x02 << 8) |
192cdc58 LCVR |
495 | #define S3C2400_GPF4_nRTS0 (0x02 << 8) |
496 | #define S3C2400_GPF4_nXBACK (0x03 << 8) | |
1da177e4 | 497 | |
1da177e4 | 498 | #define S3C2410_GPF5_EINT5 (0x02 << 10) |
192cdc58 LCVR |
499 | #define S3C2400_GPF5_nCTS0 (0x02 << 10) |
500 | #define S3C2400_GPF5_nXBREQ (0x03 << 10) | |
1da177e4 | 501 | |
1da177e4 | 502 | #define S3C2410_GPF6_EINT6 (0x02 << 12) |
192cdc58 | 503 | #define S3C2400_GPF6_CLKOUT (0x02 << 12) |
1da177e4 | 504 | |
1da177e4 LT |
505 | #define S3C2410_GPF7_EINT7 (0x02 << 14) |
506 | ||
192cdc58 LCVR |
507 | #define S3C2410_GPF_PUPDIS(x) (1<<(x)) |
508 | ||
509 | /* S3C2410: | |
510 | * Port G consists of 8 GPIO/IRQ/Special function | |
1da177e4 LT |
511 | * |
512 | * GPGCON has 2 bits for each of the input pins on port F | |
513 | * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func | |
514 | * | |
515 | * pull up works like all other ports. | |
192cdc58 LCVR |
516 | * |
517 | * S3C2400: | |
518 | * Port G consists of 10 GPIO/Special function | |
1da177e4 LT |
519 | */ |
520 | ||
521 | #define S3C2410_GPGCON S3C2410_GPIOREG(0x60) | |
522 | #define S3C2410_GPGDAT S3C2410_GPIOREG(0x64) | |
523 | #define S3C2410_GPGUP S3C2410_GPIOREG(0x68) | |
524 | ||
192cdc58 LCVR |
525 | #define S3C2400_GPGCON S3C2410_GPIOREG(0x44) |
526 | #define S3C2400_GPGDAT S3C2410_GPIOREG(0x48) | |
527 | #define S3C2400_GPGUP S3C2410_GPIOREG(0x4C) | |
528 | ||
1da177e4 | 529 | #define S3C2410_GPG0_EINT8 (0x02 << 0) |
192cdc58 | 530 | #define S3C2400_GPG0_I2SLRCK (0x02 << 0) |
1da177e4 | 531 | |
1da177e4 | 532 | #define S3C2410_GPG1_EINT9 (0x02 << 2) |
192cdc58 | 533 | #define S3C2400_GPG1_I2SSCLK (0x02 << 2) |
1da177e4 | 534 | |
1da177e4 | 535 | #define S3C2410_GPG2_EINT10 (0x02 << 4) |
de56a2f9 | 536 | #define S3C2410_GPG2_nSS0 (0x03 << 4) |
192cdc58 | 537 | #define S3C2400_GPG2_CDCLK (0x02 << 4) |
1da177e4 | 538 | |
1da177e4 | 539 | #define S3C2410_GPG3_EINT11 (0x02 << 6) |
de56a2f9 | 540 | #define S3C2410_GPG3_nSS1 (0x03 << 6) |
192cdc58 LCVR |
541 | #define S3C2400_GPG3_I2SSDO (0x02 << 6) |
542 | #define S3C2400_GPG3_I2SSDI (0x03 << 6) | |
1da177e4 | 543 | |
1da177e4 | 544 | #define S3C2410_GPG4_EINT12 (0x02 << 8) |
192cdc58 LCVR |
545 | #define S3C2400_GPG4_MMCCLK (0x02 << 8) |
546 | #define S3C2400_GPG4_I2SSDI (0x03 << 8) | |
1da177e4 | 547 | #define S3C2410_GPG4_LCDPWREN (0x03 << 8) |
6619d58a | 548 | #define S3C2443_GPG4_LCDPWRDN (0x03 << 8) |
1da177e4 | 549 | |
1da177e4 | 550 | #define S3C2410_GPG5_EINT13 (0x02 << 10) |
192cdc58 LCVR |
551 | #define S3C2400_GPG5_MMCCMD (0x02 << 10) |
552 | #define S3C2400_GPG5_IICSDA (0x03 << 10) | |
6619d58a | 553 | #define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */ |
1da177e4 | 554 | |
1da177e4 | 555 | #define S3C2410_GPG6_EINT14 (0x02 << 12) |
192cdc58 LCVR |
556 | #define S3C2400_GPG6_MMCDAT (0x02 << 12) |
557 | #define S3C2400_GPG6_IICSCL (0x03 << 12) | |
1da177e4 LT |
558 | #define S3C2410_GPG6_SPIMOSI1 (0x03 << 12) |
559 | ||
1da177e4 LT |
560 | #define S3C2410_GPG7_EINT15 (0x02 << 14) |
561 | #define S3C2410_GPG7_SPICLK1 (0x03 << 14) | |
192cdc58 LCVR |
562 | #define S3C2400_GPG7_SPIMISO (0x02 << 14) |
563 | #define S3C2400_GPG7_IICSDA (0x03 << 14) | |
1da177e4 | 564 | |
1da177e4 | 565 | #define S3C2410_GPG8_EINT16 (0x02 << 16) |
192cdc58 LCVR |
566 | #define S3C2400_GPG8_SPIMOSI (0x02 << 16) |
567 | #define S3C2400_GPG8_IICSCL (0x03 << 16) | |
1da177e4 | 568 | |
1da177e4 | 569 | #define S3C2410_GPG9_EINT17 (0x02 << 18) |
192cdc58 LCVR |
570 | #define S3C2400_GPG9_SPICLK (0x02 << 18) |
571 | #define S3C2400_GPG9_MMCCLK (0x03 << 18) | |
1da177e4 | 572 | |
1da177e4 LT |
573 | #define S3C2410_GPG10_EINT18 (0x02 << 20) |
574 | ||
1da177e4 LT |
575 | #define S3C2410_GPG11_EINT19 (0x02 << 22) |
576 | #define S3C2410_GPG11_TCLK1 (0x03 << 22) | |
6619d58a | 577 | #define S3C2443_GPG11_CF_nIREQ (0x03 << 22) |
1da177e4 | 578 | |
1da177e4 LT |
579 | #define S3C2410_GPG12_EINT20 (0x02 << 24) |
580 | #define S3C2410_GPG12_XMON (0x03 << 24) | |
96ce2385 | 581 | #define S3C2442_GPG12_nSPICS0 (0x03 << 24) |
6619d58a | 582 | #define S3C2443_GPG12_nINPACK (0x03 << 24) |
1da177e4 | 583 | |
1da177e4 LT |
584 | #define S3C2410_GPG13_EINT21 (0x02 << 26) |
585 | #define S3C2410_GPG13_nXPON (0x03 << 26) | |
6619d58a | 586 | #define S3C2443_GPG13_CF_nREG (0x03 << 26) |
1da177e4 | 587 | |
1da177e4 LT |
588 | #define S3C2410_GPG14_EINT22 (0x02 << 28) |
589 | #define S3C2410_GPG14_YMON (0x03 << 28) | |
6619d58a | 590 | #define S3C2443_GPG14_CF_RESET (0x03 << 28) |
1da177e4 | 591 | |
1da177e4 LT |
592 | #define S3C2410_GPG15_EINT23 (0x02 << 30) |
593 | #define S3C2410_GPG15_nYPON (0x03 << 30) | |
6619d58a | 594 | #define S3C2443_GPG15_CF_PWR (0x03 << 30) |
1da177e4 LT |
595 | |
596 | #define S3C2410_GPG_PUPDIS(x) (1<<(x)) | |
597 | ||
598 | /* Port H consists of11 GPIO/serial/Misc pins | |
599 | * | |
600 | * GPGCON has 2 bits for each of the input pins on port F | |
601 | * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func | |
602 | * | |
603 | * pull up works like all other ports. | |
604 | */ | |
605 | ||
606 | #define S3C2410_GPHCON S3C2410_GPIOREG(0x70) | |
607 | #define S3C2410_GPHDAT S3C2410_GPIOREG(0x74) | |
608 | #define S3C2410_GPHUP S3C2410_GPIOREG(0x78) | |
609 | ||
1da177e4 LT |
610 | #define S3C2410_GPH0_nCTS0 (0x02 << 0) |
611 | ||
1da177e4 LT |
612 | #define S3C2410_GPH1_nRTS0 (0x02 << 2) |
613 | ||
1da177e4 LT |
614 | #define S3C2410_GPH2_TXD0 (0x02 << 4) |
615 | ||
1da177e4 LT |
616 | #define S3C2410_GPH3_RXD0 (0x02 << 6) |
617 | ||
1da177e4 LT |
618 | #define S3C2410_GPH4_TXD1 (0x02 << 8) |
619 | ||
1da177e4 LT |
620 | #define S3C2410_GPH5_RXD1 (0x02 << 10) |
621 | ||
1da177e4 LT |
622 | #define S3C2410_GPH6_TXD2 (0x02 << 12) |
623 | #define S3C2410_GPH6_nRTS1 (0x03 << 12) | |
624 | ||
1da177e4 LT |
625 | #define S3C2410_GPH7_RXD2 (0x02 << 14) |
626 | #define S3C2410_GPH7_nCTS1 (0x03 << 14) | |
627 | ||
1da177e4 LT |
628 | #define S3C2410_GPH8_UCLK (0x02 << 16) |
629 | ||
1da177e4 | 630 | #define S3C2410_GPH9_CLKOUT0 (0x02 << 18) |
96ce2385 | 631 | #define S3C2442_GPH9_nSPICS0 (0x03 << 18) |
1da177e4 | 632 | |
1da177e4 LT |
633 | #define S3C2410_GPH10_CLKOUT1 (0x02 << 20) |
634 | ||
68d9ab39 BD |
635 | /* The S3C2412 and S3C2413 move the GPJ register set to after |
636 | * GPH, which means all registers after 0x80 are now offset by 0x10 | |
637 | * for the 2412/2413 from the 2410/2440/2442 | |
638 | */ | |
639 | ||
1da177e4 | 640 | /* miscellaneous control */ |
192cdc58 | 641 | #define S3C2400_MISCCR S3C2410_GPIOREG(0x54) |
1da177e4 LT |
642 | #define S3C2410_MISCCR S3C2410_GPIOREG(0x80) |
643 | #define S3C2410_DCLKCON S3C2410_GPIOREG(0x84) | |
644 | ||
68d9ab39 BD |
645 | #define S3C24XX_DCLKCON S3C24XX_GPIOREG2(0x84) |
646 | ||
1da177e4 LT |
647 | /* see clock.h for dclk definitions */ |
648 | ||
649 | /* pullup control on databus */ | |
192cdc58 | 650 | #define S3C2410_MISCCR_SPUCR_HEN (0<<0) |
1da177e4 | 651 | #define S3C2410_MISCCR_SPUCR_HDIS (1<<0) |
192cdc58 | 652 | #define S3C2410_MISCCR_SPUCR_LEN (0<<1) |
1da177e4 LT |
653 | #define S3C2410_MISCCR_SPUCR_LDIS (1<<1) |
654 | ||
192cdc58 LCVR |
655 | #define S3C2400_MISCCR_SPUCR_LEN (0<<0) |
656 | #define S3C2400_MISCCR_SPUCR_LDIS (1<<0) | |
657 | #define S3C2400_MISCCR_SPUCR_HEN (0<<1) | |
658 | #define S3C2400_MISCCR_SPUCR_HDIS (1<<1) | |
659 | ||
660 | #define S3C2400_MISCCR_HZ_STOPEN (0<<2) | |
661 | #define S3C2400_MISCCR_HZ_STOPPREV (1<<2) | |
662 | ||
663 | #define S3C2410_MISCCR_USBDEV (0<<3) | |
1da177e4 LT |
664 | #define S3C2410_MISCCR_USBHOST (1<<3) |
665 | ||
666 | #define S3C2410_MISCCR_CLK0_MPLL (0<<4) | |
667 | #define S3C2410_MISCCR_CLK0_UPLL (1<<4) | |
668 | #define S3C2410_MISCCR_CLK0_FCLK (2<<4) | |
669 | #define S3C2410_MISCCR_CLK0_HCLK (3<<4) | |
670 | #define S3C2410_MISCCR_CLK0_PCLK (4<<4) | |
671 | #define S3C2410_MISCCR_CLK0_DCLK0 (5<<4) | |
3fc3e1c0 | 672 | #define S3C2410_MISCCR_CLK0_MASK (7<<4) |
1da177e4 | 673 | |
68d9ab39 BD |
674 | #define S3C2412_MISCCR_CLK0_RTC (2<<4) |
675 | ||
1da177e4 LT |
676 | #define S3C2410_MISCCR_CLK1_MPLL (0<<8) |
677 | #define S3C2410_MISCCR_CLK1_UPLL (1<<8) | |
678 | #define S3C2410_MISCCR_CLK1_FCLK (2<<8) | |
679 | #define S3C2410_MISCCR_CLK1_HCLK (3<<8) | |
680 | #define S3C2410_MISCCR_CLK1_PCLK (4<<8) | |
681 | #define S3C2410_MISCCR_CLK1_DCLK1 (5<<8) | |
3fc3e1c0 | 682 | #define S3C2410_MISCCR_CLK1_MASK (7<<8) |
1da177e4 | 683 | |
68d9ab39 BD |
684 | #define S3C2412_MISCCR_CLK1_CLKsrc (0<<8) |
685 | ||
1da177e4 LT |
686 | #define S3C2410_MISCCR_USBSUSPND0 (1<<12) |
687 | #define S3C2410_MISCCR_USBSUSPND1 (1<<13) | |
688 | ||
689 | #define S3C2410_MISCCR_nRSTCON (1<<16) | |
690 | ||
691 | #define S3C2410_MISCCR_nEN_SCLK0 (1<<17) | |
692 | #define S3C2410_MISCCR_nEN_SCLK1 (1<<18) | |
68d9ab39 | 693 | #define S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */ |
1da177e4 LT |
694 | #define S3C2410_MISCCR_SDSLEEP (7<<17) |
695 | ||
696 | /* external interrupt control... */ | |
697 | /* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7 | |
698 | * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15 | |
699 | * S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23 | |
700 | * | |
701 | * note S3C2410_EXTINT2 has filtering options for EINT16..EINT23 | |
702 | * | |
703 | * Samsung datasheet p9-25 | |
704 | */ | |
192cdc58 | 705 | #define S3C2400_EXTINT0 S3C2410_GPIOREG(0x58) |
1da177e4 LT |
706 | #define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88) |
707 | #define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C) | |
708 | #define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90) | |
709 | ||
68d9ab39 BD |
710 | #define S3C24XX_EXTINT0 S3C24XX_GPIOREG2(0x88) |
711 | #define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C) | |
712 | #define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90) | |
713 | ||
1da177e4 LT |
714 | /* interrupt filtering conrrol for EINT16..EINT23 */ |
715 | #define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94) | |
716 | #define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98) | |
717 | #define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C) | |
718 | #define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0) | |
719 | ||
68d9ab39 BD |
720 | #define S3C24XX_EINFLT0 S3C24XX_GPIOREG2(0x94) |
721 | #define S3C24XX_EINFLT1 S3C24XX_GPIOREG2(0x98) | |
722 | #define S3C24XX_EINFLT2 S3C24XX_GPIOREG2(0x9C) | |
723 | #define S3C24XX_EINFLT3 S3C24XX_GPIOREG2(0xA0) | |
724 | ||
1da177e4 LT |
725 | /* values for interrupt filtering */ |
726 | #define S3C2410_EINTFLT_PCLK (0x00) | |
727 | #define S3C2410_EINTFLT_EXTCLK (1<<7) | |
728 | #define S3C2410_EINTFLT_WIDTHMSK(x) ((x) & 0x3f) | |
729 | ||
730 | /* removed EINTxxxx defs from here, not meant for this */ | |
731 | ||
732 | /* GSTATUS have miscellaneous information in them | |
733 | * | |
68d9ab39 | 734 | * These move between s3c2410 and s3c2412 style systems. |
1da177e4 LT |
735 | */ |
736 | ||
737 | #define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC) | |
738 | #define S3C2410_GSTATUS1 S3C2410_GPIOREG(0x0B0) | |
739 | #define S3C2410_GSTATUS2 S3C2410_GPIOREG(0x0B4) | |
740 | #define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8) | |
741 | #define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC) | |
742 | ||
68d9ab39 BD |
743 | #define S3C2412_GSTATUS0 S3C2410_GPIOREG(0x0BC) |
744 | #define S3C2412_GSTATUS1 S3C2410_GPIOREG(0x0C0) | |
745 | #define S3C2412_GSTATUS2 S3C2410_GPIOREG(0x0C4) | |
746 | #define S3C2412_GSTATUS3 S3C2410_GPIOREG(0x0C8) | |
747 | #define S3C2412_GSTATUS4 S3C2410_GPIOREG(0x0CC) | |
748 | ||
749 | #define S3C24XX_GSTATUS0 S3C24XX_GPIOREG2(0x0AC) | |
750 | #define S3C24XX_GSTATUS1 S3C24XX_GPIOREG2(0x0B0) | |
751 | #define S3C24XX_GSTATUS2 S3C24XX_GPIOREG2(0x0B4) | |
752 | #define S3C24XX_GSTATUS3 S3C24XX_GPIOREG2(0x0B8) | |
753 | #define S3C24XX_GSTATUS4 S3C24XX_GPIOREG2(0x0BC) | |
754 | ||
1da177e4 LT |
755 | #define S3C2410_GSTATUS0_nWAIT (1<<3) |
756 | #define S3C2410_GSTATUS0_NCON (1<<2) | |
757 | #define S3C2410_GSTATUS0_RnB (1<<1) | |
758 | #define S3C2410_GSTATUS0_nBATTFLT (1<<0) | |
759 | ||
760 | #define S3C2410_GSTATUS1_IDMASK (0xffff0000) | |
761 | #define S3C2410_GSTATUS1_2410 (0x32410000) | |
68d9ab39 | 762 | #define S3C2410_GSTATUS1_2412 (0x32412001) |
1da177e4 | 763 | #define S3C2410_GSTATUS1_2440 (0x32440000) |
96ce2385 | 764 | #define S3C2410_GSTATUS1_2442 (0x32440aaa) |
1da177e4 LT |
765 | |
766 | #define S3C2410_GSTATUS2_WTRESET (1<<2) | |
767 | #define S3C2410_GSTATUS2_OFFRESET (1<<1) | |
768 | #define S3C2410_GSTATUS2_PONRESET (1<<0) | |
769 | ||
192cdc58 LCVR |
770 | /* open drain control register */ |
771 | #define S3C2400_OPENCR S3C2410_GPIOREG(0x50) | |
772 | ||
773 | #define S3C2400_OPENCR_OPC_RXD1DIS (0<<0) | |
774 | #define S3C2400_OPENCR_OPC_RXD1EN (1<<0) | |
775 | #define S3C2400_OPENCR_OPC_TXD1DIS (0<<1) | |
776 | #define S3C2400_OPENCR_OPC_TXD1EN (1<<1) | |
777 | #define S3C2400_OPENCR_OPC_CMDDIS (0<<2) | |
778 | #define S3C2400_OPENCR_OPC_CMDEN (1<<2) | |
779 | #define S3C2400_OPENCR_OPC_DATDIS (0<<3) | |
780 | #define S3C2400_OPENCR_OPC_DATEN (1<<3) | |
781 | #define S3C2400_OPENCR_OPC_MISODIS (0<<4) | |
782 | #define S3C2400_OPENCR_OPC_MISOEN (1<<4) | |
783 | #define S3C2400_OPENCR_OPC_MOSIDIS (0<<5) | |
784 | #define S3C2400_OPENCR_OPC_MOSIEN (1<<5) | |
785 | ||
68d9ab39 BD |
786 | /* 2412/2413 sleep configuration registers */ |
787 | ||
788 | #define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C) | |
789 | #define S3C2412_GPCSLPCON S3C2410_GPIOREG(0x2C) | |
790 | #define S3C2412_GPDSLPCON S3C2410_GPIOREG(0x3C) | |
68d9ab39 BD |
791 | #define S3C2412_GPFSLPCON S3C2410_GPIOREG(0x5C) |
792 | #define S3C2412_GPGSLPCON S3C2410_GPIOREG(0x6C) | |
793 | #define S3C2412_GPHSLPCON S3C2410_GPIOREG(0x7C) | |
794 | ||
795 | /* definitions for each pin bit */ | |
67d729ad BD |
796 | #define S3C2412_GPIO_SLPCON_LOW ( 0x00 ) |
797 | #define S3C2412_GPIO_SLPCON_HIGH ( 0x01 ) | |
798 | #define S3C2412_GPIO_SLPCON_IN ( 0x02 ) | |
799 | #define S3C2412_GPIO_SLPCON_PULL ( 0x03 ) | |
800 | ||
68d9ab39 | 801 | #define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2)) |
700dc2b5 | 802 | #define S3C2412_SLPCON_HIGH(x) ( 0x01 << ((x) * 2)) |
68d9ab39 | 803 | #define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2)) |
700dc2b5 BD |
804 | #define S3C2412_SLPCON_PULL(x) ( 0x03 << ((x) * 2)) |
805 | #define S3C2412_SLPCON_EINT(x) ( 0x02 << ((x) * 2)) /* only IRQ pins */ | |
68d9ab39 BD |
806 | #define S3C2412_SLPCON_MASK(x) ( 0x03 << ((x) * 2)) |
807 | ||
700dc2b5 BD |
808 | #define S3C2412_SLPCON_ALL_LOW (0x0) |
809 | #define S3C2412_SLPCON_ALL_HIGH (0x11111111 | 0x44444444) | |
810 | #define S3C2412_SLPCON_ALL_IN (0x22222222 | 0x88888888) | |
811 | #define S3C2412_SLPCON_ALL_PULL (0x33333333) | |
812 | ||
1da177e4 LT |
813 | #endif /* __ASM_ARCH_REGS_GPIO_H */ |
814 |