Commit | Line | Data |
---|---|---|
7efb833d BD |
1 | /* linux/arch/arm/mach-s3c2410/mach-anubis.c |
2 | * | |
3 | * Copyright (c) 2003-2005 Simtec Electronics | |
4 | * http://armlinux.simtec.co.uk/ | |
5 | * Ben Dooks <ben@simtec.co.uk> | |
6 | * | |
7 | * | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * Modifications: | |
14 | * 02-May-2005 BJD Copied from mach-bast.c | |
15 | */ | |
16 | ||
17 | #include <linux/kernel.h> | |
18 | #include <linux/types.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/list.h> | |
21 | #include <linux/timer.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/device.h> | |
24 | ||
25 | #include <asm/mach/arch.h> | |
26 | #include <asm/mach/map.h> | |
27 | #include <asm/mach/irq.h> | |
28 | ||
29 | #include <asm/arch/anubis-map.h> | |
30 | #include <asm/arch/anubis-irq.h> | |
31 | #include <asm/arch/anubis-cpld.h> | |
32 | ||
33 | #include <asm/hardware.h> | |
34 | #include <asm/io.h> | |
35 | #include <asm/irq.h> | |
36 | #include <asm/mach-types.h> | |
37 | ||
38 | #include <asm/arch/regs-serial.h> | |
39 | #include <asm/arch/regs-gpio.h> | |
40 | #include <asm/arch/regs-mem.h> | |
41 | #include <asm/arch/regs-lcd.h> | |
42 | #include <asm/arch/nand.h> | |
43 | ||
44 | #include <linux/mtd/mtd.h> | |
45 | #include <linux/mtd/nand.h> | |
46 | #include <linux/mtd/nand_ecc.h> | |
47 | #include <linux/mtd/partitions.h> | |
48 | ||
49 | #include "clock.h" | |
50 | #include "devs.h" | |
51 | #include "cpu.h" | |
52 | ||
53 | #define COPYRIGHT ", (c) 2005 Simtec Electronics" | |
54 | ||
55 | static struct map_desc anubis_iodesc[] __initdata = { | |
56 | /* ISA IO areas */ | |
57 | ||
58 | { (u32)S3C24XX_VA_ISA_BYTE, 0x0, SZ_16M, MT_DEVICE }, | |
59 | { (u32)S3C24XX_VA_ISA_WORD, 0x0, SZ_16M, MT_DEVICE }, | |
60 | ||
61 | /* we could possibly compress the next set down into a set of smaller tables | |
62 | * pagetables, but that would mean using an L2 section, and it still means | |
63 | * we cannot actually feed the same register to an LDR due to 16K spacing | |
64 | */ | |
65 | ||
66 | /* CPLD control registers */ | |
67 | ||
68 | { (u32)ANUBIS_VA_CTRL1, ANUBIS_PA_CTRL1, SZ_4K, MT_DEVICE }, | |
69 | { (u32)ANUBIS_VA_CTRL2, ANUBIS_PA_CTRL2, SZ_4K, MT_DEVICE }, | |
70 | ||
71 | /* IDE drives */ | |
72 | ||
73 | { (u32)ANUBIS_IDEPRI, S3C2410_CS3, SZ_1M, MT_DEVICE }, | |
74 | { (u32)ANUBIS_IDEPRIAUX, S3C2410_CS3+(1<<26), SZ_1M, MT_DEVICE }, | |
75 | ||
76 | { (u32)ANUBIS_IDESEC, S3C2410_CS4, SZ_1M, MT_DEVICE }, | |
77 | { (u32)ANUBIS_IDESECAUX, S3C2410_CS4+(1<<26), SZ_1M, MT_DEVICE }, | |
78 | }; | |
79 | ||
80 | #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK | |
81 | #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB | |
82 | #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE | |
83 | ||
84 | static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = { | |
85 | [0] = { | |
86 | .name = "uclk", | |
87 | .divisor = 1, | |
88 | .min_baud = 0, | |
89 | .max_baud = 0, | |
90 | }, | |
91 | [1] = { | |
92 | .name = "pclk", | |
93 | .divisor = 1, | |
94 | .min_baud = 0, | |
95 | .max_baud = 0. | |
96 | } | |
97 | }; | |
98 | ||
99 | ||
100 | static struct s3c2410_uartcfg anubis_uartcfgs[] = { | |
101 | [0] = { | |
102 | .hwport = 0, | |
103 | .flags = 0, | |
104 | .ucon = UCON, | |
105 | .ulcon = ULCON, | |
106 | .ufcon = UFCON, | |
107 | .clocks = anubis_serial_clocks, | |
108 | .clocks_size = ARRAY_SIZE(anubis_serial_clocks) | |
109 | }, | |
110 | [1] = { | |
111 | .hwport = 2, | |
112 | .flags = 0, | |
113 | .ucon = UCON, | |
114 | .ulcon = ULCON, | |
115 | .ufcon = UFCON, | |
116 | .clocks = anubis_serial_clocks, | |
117 | .clocks_size = ARRAY_SIZE(anubis_serial_clocks) | |
118 | }, | |
119 | }; | |
120 | ||
121 | /* NAND Flash on Anubis board */ | |
122 | ||
123 | static int external_map[] = { 2 }; | |
124 | static int chip0_map[] = { 0 }; | |
125 | static int chip1_map[] = { 1 }; | |
126 | ||
127 | struct mtd_partition anubis_default_nand_part[] = { | |
128 | [0] = { | |
129 | .name = "Boot Agent", | |
130 | .size = SZ_16K, | |
131 | .offset = 0 | |
132 | }, | |
133 | [1] = { | |
134 | .name = "/boot", | |
135 | .size = SZ_4M - SZ_16K, | |
136 | .offset = SZ_16K, | |
137 | }, | |
138 | [2] = { | |
139 | .name = "user1", | |
140 | .offset = SZ_4M, | |
141 | .size = SZ_32M - SZ_4M, | |
142 | }, | |
143 | [3] = { | |
144 | .name = "user2", | |
145 | .offset = SZ_32M, | |
146 | .size = MTDPART_SIZ_FULL, | |
147 | } | |
148 | }; | |
149 | ||
150 | /* the Anubis has 3 selectable slots for nand-flash, the two | |
151 | * on-board chip areas, as well as the external slot. | |
152 | * | |
153 | * Note, there is no current hot-plug support for the External | |
154 | * socket. | |
155 | */ | |
156 | ||
157 | static struct s3c2410_nand_set anubis_nand_sets[] = { | |
158 | [1] = { | |
159 | .name = "External", | |
160 | .nr_chips = 1, | |
161 | .nr_map = external_map, | |
162 | .nr_partitions = ARRAY_SIZE(anubis_default_nand_part), | |
163 | .partitions = anubis_default_nand_part | |
164 | }, | |
165 | [0] = { | |
166 | .name = "chip0", | |
167 | .nr_chips = 1, | |
168 | .nr_map = chip0_map, | |
169 | .nr_partitions = ARRAY_SIZE(anubis_default_nand_part), | |
170 | .partitions = anubis_default_nand_part | |
171 | }, | |
172 | [2] = { | |
173 | .name = "chip1", | |
174 | .nr_chips = 1, | |
175 | .nr_map = chip1_map, | |
176 | .nr_partitions = ARRAY_SIZE(anubis_default_nand_part), | |
177 | .partitions = anubis_default_nand_part | |
178 | }, | |
179 | }; | |
180 | ||
181 | static void anubis_nand_select(struct s3c2410_nand_set *set, int slot) | |
182 | { | |
183 | unsigned int tmp; | |
184 | ||
185 | slot = set->nr_map[slot] & 3; | |
186 | ||
187 | pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n", | |
188 | slot, set, set->nr_map); | |
189 | ||
190 | tmp = __raw_readb(ANUBIS_VA_CTRL1); | |
191 | tmp &= ~ANUBIS_CTRL1_NANDSEL; | |
192 | tmp |= slot; | |
193 | ||
194 | pr_debug("anubis_nand: ctrl1 now %02x\n", tmp); | |
195 | ||
196 | __raw_writeb(tmp, ANUBIS_VA_CTRL1); | |
197 | } | |
198 | ||
199 | static struct s3c2410_platform_nand anubis_nand_info = { | |
200 | .tacls = 25, | |
201 | .twrph0 = 80, | |
202 | .twrph1 = 80, | |
203 | .nr_sets = ARRAY_SIZE(anubis_nand_sets), | |
204 | .sets = anubis_nand_sets, | |
205 | .select_chip = anubis_nand_select, | |
206 | }; | |
207 | ||
208 | ||
209 | /* Standard Anubis devices */ | |
210 | ||
211 | static struct platform_device *anubis_devices[] __initdata = { | |
212 | &s3c_device_usb, | |
213 | &s3c_device_wdt, | |
214 | &s3c_device_adc, | |
215 | &s3c_device_i2c, | |
216 | &s3c_device_rtc, | |
217 | &s3c_device_nand, | |
218 | }; | |
219 | ||
220 | static struct clk *anubis_clocks[] = { | |
221 | &s3c24xx_dclk0, | |
222 | &s3c24xx_dclk1, | |
223 | &s3c24xx_clkout0, | |
224 | &s3c24xx_clkout1, | |
225 | &s3c24xx_uclk, | |
226 | }; | |
227 | ||
228 | static struct s3c24xx_board anubis_board __initdata = { | |
229 | .devices = anubis_devices, | |
230 | .devices_count = ARRAY_SIZE(anubis_devices), | |
231 | .clocks = anubis_clocks, | |
232 | .clocks_count = ARRAY_SIZE(anubis_clocks) | |
233 | }; | |
234 | ||
235 | void __init anubis_map_io(void) | |
236 | { | |
237 | /* initialise the clocks */ | |
238 | ||
239 | s3c24xx_dclk0.parent = NULL; | |
240 | s3c24xx_dclk0.rate = 12*1000*1000; | |
241 | ||
242 | s3c24xx_dclk1.parent = NULL; | |
243 | s3c24xx_dclk1.rate = 24*1000*1000; | |
244 | ||
245 | s3c24xx_clkout0.parent = &s3c24xx_dclk0; | |
246 | s3c24xx_clkout1.parent = &s3c24xx_dclk1; | |
247 | ||
248 | s3c24xx_uclk.parent = &s3c24xx_clkout1; | |
249 | ||
250 | s3c_device_nand.dev.platform_data = &anubis_nand_info; | |
251 | ||
252 | s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc)); | |
253 | s3c24xx_init_clocks(0); | |
254 | s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs)); | |
255 | s3c24xx_set_board(&anubis_board); | |
256 | ||
257 | /* ensure that the GPIO is setup */ | |
258 | s3c2410_gpio_setpin(S3C2410_GPA0, 1); | |
259 | } | |
260 | ||
261 | MACHINE_START(ANUBIS, "Simtec-Anubis") | |
262 | /* Maintainer: Ben Dooks <ben@simtec.co.uk> */ | |
263 | .phys_ram = S3C2410_SDRAM_PA, | |
264 | .phys_io = S3C2410_PA_UART, | |
265 | .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, | |
266 | .boot_params = S3C2410_SDRAM_PA + 0x100, | |
267 | .map_io = anubis_map_io, | |
268 | .init_irq = s3c24xx_init_irq, | |
269 | .timer = &s3c24xx_timer, | |
270 | MACHINE_END |