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[ARM] 3559/1: S3C2442: core and serial port
[deliverable/linux.git] / arch / arm / mach-s3c2410 / mach-anubis.c
CommitLineData
7efb833d
BD		 1/* linux/arch/arm/mach-s3c2410/mach-anubis.c
2 *
3 * Copyright (c) 2003-2005 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Modifications:
14 * 02-May-2005 BJD Copied from mach-bast.c
5fe10ab1 15 * 20-Sep-2005 BJD Added static to non-exported items
7efb833d
BD		 16*/
17
18#include <linux/kernel.h>
19#include <linux/types.h>
20#include <linux/interrupt.h>
21#include <linux/list.h>
22#include <linux/timer.h>
23#include <linux/init.h>
d052d1be 24#include <linux/platform_device.h>
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BD		 25
26#include <asm/mach/arch.h>
27#include <asm/mach/map.h>
28#include <asm/mach/irq.h>
29
30#include <asm/arch/anubis-map.h>
31#include <asm/arch/anubis-irq.h>
32#include <asm/arch/anubis-cpld.h>
33
34#include <asm/hardware.h>
35#include <asm/io.h>
36#include <asm/irq.h>
37#include <asm/mach-types.h>
38
39#include <asm/arch/regs-serial.h>
40#include <asm/arch/regs-gpio.h>
41#include <asm/arch/regs-mem.h>
42#include <asm/arch/regs-lcd.h>
43#include <asm/arch/nand.h>
44
45#include <linux/mtd/mtd.h>
46#include <linux/mtd/nand.h>
47#include <linux/mtd/nand_ecc.h>
48#include <linux/mtd/partitions.h>
49
50#include "clock.h"
51#include "devs.h"
52#include "cpu.h"
53
54#define COPYRIGHT ", (c) 2005 Simtec Electronics"
55
56static struct map_desc anubis_iodesc[] __initdata = {
57 /* ISA IO areas */
58
8dd52311
BD		 59 {
60 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
61 .pfn = __phys_to_pfn(0x0),
62 .length = SZ_4M,
63 .type = MT_DEVICE
64 }, {
65 .virtual = (u32)S3C24XX_VA_ISA_WORD,
66 .pfn = __phys_to_pfn(0x0),
67 .length = SZ_4M, MT_DEVICE
68 },
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BD		 69
70 /* we could possibly compress the next set down into a set of smaller tables
71 * pagetables, but that would mean using an L2 section, and it still means
72 * we cannot actually feed the same register to an LDR due to 16K spacing
73 */
74
75 /* CPLD control registers */
76
8dd52311
BD		 77 {
78 .virtual = (u32)ANUBIS_VA_CTRL1,
79 .pfn = __phys_to_pfn(ANUBIS_PA_CTRL1),
80 .length = SZ_4K,
81 .type = MT_DEVICE
82 }, {
83 .virtual = (u32)ANUBIS_VA_CTRL2,
84 .pfn = __phys_to_pfn(ANUBIS_PA_CTRL2),
85 .length = SZ_4K,
86 .type =MT_DEVICE
87 },
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BD		 88
89 /* IDE drives */
90
8dd52311
BD		 91 {
92 .virtual = (u32)ANUBIS_IDEPRI,
93 .pfn = __phys_to_pfn(S3C2410_CS3),
94 .length = SZ_1M,
95 .type = MT_DEVICE
96 }, {
97 .virtual = (u32)ANUBIS_IDEPRIAUX,
98 .pfn = __phys_to_pfn(S3C2410_CS3+(1<<26)),
99 .length = SZ_1M,
100 .type = MT_DEVICE
101 }, {
102 .virtual = (u32)ANUBIS_IDESEC,
103 .pfn = __phys_to_pfn(S3C2410_CS4),
104 .length = SZ_1M,
105 .type = MT_DEVICE
106 }, {
107 .virtual = (u32)ANUBIS_IDESECAUX,
108 .pfn = __phys_to_pfn(S3C2410_CS4+(1<<26)),
109 .length = SZ_1M,
110 .type = MT_DEVICE
111 },
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BD		 112};
113
114#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
115#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
116#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
117
118static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = {
119 [0] = {
120 .name = "uclk",
121 .divisor = 1,
122 .min_baud = 0,
123 .max_baud = 0,
124 },
125 [1] = {
126 .name = "pclk",
127 .divisor = 1,
128 .min_baud = 0,
129 .max_baud = 0.
130 }
131};
132
133
66a9b49a 134static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
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BD		 135 [0] = {
136 .hwport = 0,
137 .flags = 0,
138 .ucon = UCON,
139 .ulcon = ULCON,
140 .ufcon = UFCON,
141 .clocks = anubis_serial_clocks,
142 .clocks_size = ARRAY_SIZE(anubis_serial_clocks)
143 },
144 [1] = {
145 .hwport = 2,
146 .flags = 0,
147 .ucon = UCON,
148 .ulcon = ULCON,
149 .ufcon = UFCON,
150 .clocks = anubis_serial_clocks,
151 .clocks_size = ARRAY_SIZE(anubis_serial_clocks)
152 },
153};
154
155/* NAND Flash on Anubis board */
156
157static int external_map[] = { 2 };
158static int chip0_map[] = { 0 };
159static int chip1_map[] = { 1 };
160
9f693d7b 161static struct mtd_partition anubis_default_nand_part[] = {
7efb833d
BD		 162 [0] = {
163 .name = "Boot Agent",
164 .size = SZ_16K,
165 .offset = 0
166 },
167 [1] = {
168 .name = "/boot",
169 .size = SZ_4M - SZ_16K,
170 .offset = SZ_16K,
171 },
172 [2] = {
173 .name = "user1",
174 .offset = SZ_4M,
175 .size = SZ_32M - SZ_4M,
176 },
177 [3] = {
178 .name = "user2",
179 .offset = SZ_32M,
180 .size = MTDPART_SIZ_FULL,
181 }
182};
183
184/* the Anubis has 3 selectable slots for nand-flash, the two
185 * on-board chip areas, as well as the external slot.
186 *
187 * Note, there is no current hot-plug support for the External
188 * socket.
189*/
190
191static struct s3c2410_nand_set anubis_nand_sets[] = {
192 [1] = {
193 .name = "External",
194 .nr_chips = 1,
195 .nr_map = external_map,
196 .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
197 .partitions = anubis_default_nand_part
198 },
199 [0] = {
200 .name = "chip0",
201 .nr_chips = 1,
202 .nr_map = chip0_map,
203 .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
204 .partitions = anubis_default_nand_part
205 },
206 [2] = {
207 .name = "chip1",
208 .nr_chips = 1,
209 .nr_map = chip1_map,
210 .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
211 .partitions = anubis_default_nand_part
212 },
213};
214
215static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
216{
217 unsigned int tmp;
218
219 slot = set->nr_map[slot] & 3;
220
221 pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
222 slot, set, set->nr_map);
223
224 tmp = __raw_readb(ANUBIS_VA_CTRL1);
225 tmp &= ~ANUBIS_CTRL1_NANDSEL;
226 tmp |= slot;
227
228 pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);
229
230 __raw_writeb(tmp, ANUBIS_VA_CTRL1);
231}
232
233static struct s3c2410_platform_nand anubis_nand_info = {
234 .tacls = 25,
661e6acf
BD		 235 .twrph0 = 55,
236 .twrph1 = 40,
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BD		 237 .nr_sets = ARRAY_SIZE(anubis_nand_sets),
238 .sets = anubis_nand_sets,
239 .select_chip = anubis_nand_select,
240};
241
242
243/* Standard Anubis devices */
244
245static struct platform_device *anubis_devices[] __initdata = {
246 &s3c_device_usb,
247 &s3c_device_wdt,
248 &s3c_device_adc,
249 &s3c_device_i2c,
250 &s3c_device_rtc,
251 &s3c_device_nand,
252};
253
254static struct clk *anubis_clocks[] = {
255 &s3c24xx_dclk0,
256 &s3c24xx_dclk1,
257 &s3c24xx_clkout0,
258 &s3c24xx_clkout1,
259 &s3c24xx_uclk,
260};
261
262static struct s3c24xx_board anubis_board __initdata = {
263 .devices = anubis_devices,
264 .devices_count = ARRAY_SIZE(anubis_devices),
265 .clocks = anubis_clocks,
266 .clocks_count = ARRAY_SIZE(anubis_clocks)
267};
268
5fe10ab1 269static void __init anubis_map_io(void)
7efb833d
BD		 270{
271 /* initialise the clocks */
272
273 s3c24xx_dclk0.parent = NULL;
274 s3c24xx_dclk0.rate = 12*1000*1000;
275
276 s3c24xx_dclk1.parent = NULL;
277 s3c24xx_dclk1.rate = 24*1000*1000;
278
279 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
280 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
281
282 s3c24xx_uclk.parent = &s3c24xx_clkout1;
283
284 s3c_device_nand.dev.platform_data = &anubis_nand_info;
285
286 s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
287 s3c24xx_init_clocks(0);
288 s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
289 s3c24xx_set_board(&anubis_board);
290
291 /* ensure that the GPIO is setup */
292 s3c2410_gpio_setpin(S3C2410_GPA0, 1);
293}
294
295MACHINE_START(ANUBIS, "Simtec-Anubis")
296 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
7efb833d
BD		 297 .phys_io = S3C2410_PA_UART,
298 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
299 .boot_params = S3C2410_SDRAM_PA + 0x100,
300 .map_io = anubis_map_io,
301 .init_irq = s3c24xx_init_irq,
302 .timer = &s3c24xx_timer,
303MACHINE_END
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