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Create platform_device.h to contain all the platform device details.
[deliverable/linux.git] / arch / arm / mach-s3c2410 / mach-anubis.c
CommitLineData
7efb833d
BD		 1/* linux/arch/arm/mach-s3c2410/mach-anubis.c
2 *
3 * Copyright (c) 2003-2005 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Modifications:
14 * 02-May-2005 BJD Copied from mach-bast.c
5fe10ab1 15 * 20-Sep-2005 BJD Added static to non-exported items
7efb833d
BD		 16*/
17
18#include <linux/kernel.h>
19#include <linux/types.h>
20#include <linux/interrupt.h>
21#include <linux/list.h>
22#include <linux/timer.h>
23#include <linux/init.h>
d052d1be 24#include <linux/platform_device.h>
7efb833d
BD		 25
26#include <asm/mach/arch.h>
27#include <asm/mach/map.h>
28#include <asm/mach/irq.h>
29
30#include <asm/arch/anubis-map.h>
31#include <asm/arch/anubis-irq.h>
32#include <asm/arch/anubis-cpld.h>
33
34#include <asm/hardware.h>
35#include <asm/io.h>
36#include <asm/irq.h>
37#include <asm/mach-types.h>
38
39#include <asm/arch/regs-serial.h>
40#include <asm/arch/regs-gpio.h>
41#include <asm/arch/regs-mem.h>
42#include <asm/arch/regs-lcd.h>
43#include <asm/arch/nand.h>
44
45#include <linux/mtd/mtd.h>
46#include <linux/mtd/nand.h>
47#include <linux/mtd/nand_ecc.h>
48#include <linux/mtd/partitions.h>
49
50#include "clock.h"
51#include "devs.h"
52#include "cpu.h"
53
54#define COPYRIGHT ", (c) 2005 Simtec Electronics"
55
56static struct map_desc anubis_iodesc[] __initdata = {
57 /* ISA IO areas */
58
59 { (u32)S3C24XX_VA_ISA_BYTE, 0x0, SZ_16M, MT_DEVICE },
60 { (u32)S3C24XX_VA_ISA_WORD, 0x0, SZ_16M, MT_DEVICE },
61
62 /* we could possibly compress the next set down into a set of smaller tables
63 * pagetables, but that would mean using an L2 section, and it still means
64 * we cannot actually feed the same register to an LDR due to 16K spacing
65 */
66
67 /* CPLD control registers */
68
69 { (u32)ANUBIS_VA_CTRL1, ANUBIS_PA_CTRL1, SZ_4K, MT_DEVICE },
70 { (u32)ANUBIS_VA_CTRL2, ANUBIS_PA_CTRL2, SZ_4K, MT_DEVICE },
71
72 /* IDE drives */
73
74 { (u32)ANUBIS_IDEPRI, S3C2410_CS3, SZ_1M, MT_DEVICE },
75 { (u32)ANUBIS_IDEPRIAUX, S3C2410_CS3+(1<<26), SZ_1M, MT_DEVICE },
76
77 { (u32)ANUBIS_IDESEC, S3C2410_CS4, SZ_1M, MT_DEVICE },
78 { (u32)ANUBIS_IDESECAUX, S3C2410_CS4+(1<<26), SZ_1M, MT_DEVICE },
79};
80
81#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
82#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
83#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
84
85static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = {
86 [0] = {
87 .name = "uclk",
88 .divisor = 1,
89 .min_baud = 0,
90 .max_baud = 0,
91 },
92 [1] = {
93 .name = "pclk",
94 .divisor = 1,
95 .min_baud = 0,
96 .max_baud = 0.
97 }
98};
99
100
101static struct s3c2410_uartcfg anubis_uartcfgs[] = {
102 [0] = {
103 .hwport = 0,
104 .flags = 0,
105 .ucon = UCON,
106 .ulcon = ULCON,
107 .ufcon = UFCON,
108 .clocks = anubis_serial_clocks,
109 .clocks_size = ARRAY_SIZE(anubis_serial_clocks)
110 },
111 [1] = {
112 .hwport = 2,
113 .flags = 0,
114 .ucon = UCON,
115 .ulcon = ULCON,
116 .ufcon = UFCON,
117 .clocks = anubis_serial_clocks,
118 .clocks_size = ARRAY_SIZE(anubis_serial_clocks)
119 },
120};
121
122/* NAND Flash on Anubis board */
123
124static int external_map[] = { 2 };
125static int chip0_map[] = { 0 };
126static int chip1_map[] = { 1 };
127
9f693d7b 128static struct mtd_partition anubis_default_nand_part[] = {
7efb833d
BD		 129 [0] = {
130 .name = "Boot Agent",
131 .size = SZ_16K,
132 .offset = 0
133 },
134 [1] = {
135 .name = "/boot",
136 .size = SZ_4M - SZ_16K,
137 .offset = SZ_16K,
138 },
139 [2] = {
140 .name = "user1",
141 .offset = SZ_4M,
142 .size = SZ_32M - SZ_4M,
143 },
144 [3] = {
145 .name = "user2",
146 .offset = SZ_32M,
147 .size = MTDPART_SIZ_FULL,
148 }
149};
150
151/* the Anubis has 3 selectable slots for nand-flash, the two
152 * on-board chip areas, as well as the external slot.
153 *
154 * Note, there is no current hot-plug support for the External
155 * socket.
156*/
157
158static struct s3c2410_nand_set anubis_nand_sets[] = {
159 [1] = {
160 .name = "External",
161 .nr_chips = 1,
162 .nr_map = external_map,
163 .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
164 .partitions = anubis_default_nand_part
165 },
166 [0] = {
167 .name = "chip0",
168 .nr_chips = 1,
169 .nr_map = chip0_map,
170 .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
171 .partitions = anubis_default_nand_part
172 },
173 [2] = {
174 .name = "chip1",
175 .nr_chips = 1,
176 .nr_map = chip1_map,
177 .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
178 .partitions = anubis_default_nand_part
179 },
180};
181
182static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
183{
184 unsigned int tmp;
185
186 slot = set->nr_map[slot] & 3;
187
188 pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
189 slot, set, set->nr_map);
190
191 tmp = __raw_readb(ANUBIS_VA_CTRL1);
192 tmp &= ~ANUBIS_CTRL1_NANDSEL;
193 tmp |= slot;
194
195 pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);
196
197 __raw_writeb(tmp, ANUBIS_VA_CTRL1);
198}
199
200static struct s3c2410_platform_nand anubis_nand_info = {
201 .tacls = 25,
202 .twrph0 = 80,
203 .twrph1 = 80,
204 .nr_sets = ARRAY_SIZE(anubis_nand_sets),
205 .sets = anubis_nand_sets,
206 .select_chip = anubis_nand_select,
207};
208
209
210/* Standard Anubis devices */
211
212static struct platform_device *anubis_devices[] __initdata = {
213 &s3c_device_usb,
214 &s3c_device_wdt,
215 &s3c_device_adc,
216 &s3c_device_i2c,
217 &s3c_device_rtc,
218 &s3c_device_nand,
219};
220
221static struct clk *anubis_clocks[] = {
222 &s3c24xx_dclk0,
223 &s3c24xx_dclk1,
224 &s3c24xx_clkout0,
225 &s3c24xx_clkout1,
226 &s3c24xx_uclk,
227};
228
229static struct s3c24xx_board anubis_board __initdata = {
230 .devices = anubis_devices,
231 .devices_count = ARRAY_SIZE(anubis_devices),
232 .clocks = anubis_clocks,
233 .clocks_count = ARRAY_SIZE(anubis_clocks)
234};
235
5fe10ab1 236static void __init anubis_map_io(void)
7efb833d
BD		 237{
238 /* initialise the clocks */
239
240 s3c24xx_dclk0.parent = NULL;
241 s3c24xx_dclk0.rate = 12*1000*1000;
242
243 s3c24xx_dclk1.parent = NULL;
244 s3c24xx_dclk1.rate = 24*1000*1000;
245
246 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
247 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
248
249 s3c24xx_uclk.parent = &s3c24xx_clkout1;
250
251 s3c_device_nand.dev.platform_data = &anubis_nand_info;
252
253 s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
254 s3c24xx_init_clocks(0);
255 s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
256 s3c24xx_set_board(&anubis_board);
257
258 /* ensure that the GPIO is setup */
259 s3c2410_gpio_setpin(S3C2410_GPA0, 1);
260}
261
262MACHINE_START(ANUBIS, "Simtec-Anubis")
263 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
264 .phys_ram = S3C2410_SDRAM_PA,
265 .phys_io = S3C2410_PA_UART,
266 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
267 .boot_params = S3C2410_SDRAM_PA + 0x100,
268 .map_io = anubis_map_io,
269 .init_irq = s3c24xx_init_irq,
270 .timer = &s3c24xx_timer,
271MACHINE_END
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