[deliverable/linux.git] / arch / arm / mach-s3c2410 / mach-bast.c

/* linux/arch/arm/mach-s3c2410/mach-bast.c
 *
 * Copyright 2003-2008 Simtec Electronics
 *   Ben Dooks <ben@simtec.co.uk>
 *
 * http://www.simtec.co.uk/products/EB2410ITX/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/syscore_ops.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/dm9000.h>
#include <linux/ata_platform.h>
#include <linux/i2c.h>
#include <linux/io.h>

#include <net/ax88796.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <mach/bast-map.h>
#include <mach/bast-irq.h>
#include <mach/bast-cpld.h>

#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>

//#include <asm/debug-ll.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>

#include <plat/hwmon.h>
#include <plat/nand.h>
#include <plat/iic.h>
#include <mach/fb.h>

#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>

#include <linux/serial_8250.h>

#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/cpu-freq.h>
#include <plat/gpio-cfg.h>
#include <plat/audio-simtec.h>

#include "usb-simtec.h"
#include "nor-simtec.h"

#define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"

/* macros for virtual address mods for the io space entries */
#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
#define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
#define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
#define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)

/* macros to modify the physical addresses for io space */

#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))

static struct map_desc bast_iodesc[] __initdata = {
  /* ISA IO areas */
  {
	  .virtual	= (u32)S3C24XX_VA_ISA_BYTE,
	  .pfn		= PA_CS2(BAST_PA_ISAIO),
	  .length	= SZ_16M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)S3C24XX_VA_ISA_WORD,
	  .pfn		= PA_CS3(BAST_PA_ISAIO),
	  .length	= SZ_16M,
	  .type		= MT_DEVICE,
  },
  /* bast CPLD control registers, and external interrupt controls */
  {
	  .virtual	= (u32)BAST_VA_CTRL1,
	  .pfn		= __phys_to_pfn(BAST_PA_CTRL1),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_CTRL2,
	  .pfn		= __phys_to_pfn(BAST_PA_CTRL2),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_CTRL3,
	  .pfn		= __phys_to_pfn(BAST_PA_CTRL3),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_CTRL4,
	  .pfn		= __phys_to_pfn(BAST_PA_CTRL4),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  },
  /* PC104 IRQ mux */
  {
	  .virtual	= (u32)BAST_VA_PC104_IRQREQ,
	  .pfn		= __phys_to_pfn(BAST_PA_PC104_IRQREQ),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_PC104_IRQRAW,
	  .pfn		= __phys_to_pfn(BAST_PA_PC104_IRQRAW),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_PC104_IRQMASK,
	  .pfn		= __phys_to_pfn(BAST_PA_PC104_IRQMASK),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  },

  /* peripheral space... one for each of fast/slow/byte/16bit */
  /* note, ide is only decoded in word space, even though some registers
   * are only 8bit */

  /* slow, byte */
  { VA_C2(BAST_VA_ISAIO),   PA_CS2(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
  { VA_C2(BAST_VA_ISAMEM),  PA_CS2(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
  { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },

  /* slow, word */
  { VA_C3(BAST_VA_ISAIO),   PA_CS3(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
  { VA_C3(BAST_VA_ISAMEM),  PA_CS3(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
  { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },

  /* fast, byte */
  { VA_C4(BAST_VA_ISAIO),   PA_CS4(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
  { VA_C4(BAST_VA_ISAMEM),  PA_CS4(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
  { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },

  /* fast, word */
  { VA_C5(BAST_VA_ISAIO),   PA_CS5(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
  { VA_C5(BAST_VA_ISAMEM),  PA_CS5(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
  { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
};

#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE

static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
	[0] = {
		.name		= "uclk",
		.divisor	= 1,
		.min_baud	= 0,
		.max_baud	= 0,
	},
	[1] = {
		.name		= "pclk",
		.divisor	= 1,
		.min_baud	= 0,
		.max_baud	= 0,
	}
};


static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
	[0] = {
		.hwport	     = 0,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = bast_serial_clocks,
		.clocks_size = ARRAY_SIZE(bast_serial_clocks),
	},
	[1] = {
		.hwport	     = 1,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = bast_serial_clocks,
		.clocks_size = ARRAY_SIZE(bast_serial_clocks),
	},
	/* port 2 is not actually used */
	[2] = {
		.hwport	     = 2,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = bast_serial_clocks,
		.clocks_size = ARRAY_SIZE(bast_serial_clocks),
	}
};

/* NAND Flash on BAST board */

#ifdef CONFIG_PM
static int bast_pm_suspend(void)
{
	/* ensure that an nRESET is not generated on resume. */
	gpio_direction_output(S3C2410_GPA(21), 1);
	return 0;
}

static void bast_pm_resume(void)
{
	s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
}

#else
#define bast_pm_suspend NULL
#define bast_pm_resume NULL
#endif

static struct syscore_ops bast_pm_syscore_ops = {
	.suspend	= bast_pm_suspend,
	.resume		= bast_pm_resume,
};

static int smartmedia_map[] = { 0 };
static int chip0_map[] = { 1 };
static int chip1_map[] = { 2 };
static int chip2_map[] = { 3 };

static struct mtd_partition __initdata bast_default_nand_part[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_16K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_16K,
		.offset	= SZ_16K,
	},
	[2] = {
		.name	= "user",
		.offset	= SZ_4M,
		.size	= MTDPART_SIZ_FULL,
	}
};

/* the bast has 4 selectable slots for nand-flash, the three
 * on-board chip areas, as well as the external SmartMedia
 * slot.
 *
 * Note, there is no current hot-plug support for the SmartMedia
 * socket.
*/

static struct s3c2410_nand_set __initdata bast_nand_sets[] = {
	[0] = {
		.name		= "SmartMedia",
		.nr_chips	= 1,
		.nr_map		= smartmedia_map,
		.options        = NAND_SCAN_SILENT_NODEV,
		.nr_partitions	= ARRAY_SIZE(bast_default_nand_part),
		.partitions	= bast_default_nand_part,
	},
	[1] = {
		.name		= "chip0",
		.nr_chips	= 1,
		.nr_map		= chip0_map,
		.nr_partitions	= ARRAY_SIZE(bast_default_nand_part),
		.partitions	= bast_default_nand_part,
	},
	[2] = {
		.name		= "chip1",
		.nr_chips	= 1,
		.nr_map		= chip1_map,
		.options        = NAND_SCAN_SILENT_NODEV,
		.nr_partitions	= ARRAY_SIZE(bast_default_nand_part),
		.partitions	= bast_default_nand_part,
	},
	[3] = {
		.name		= "chip2",
		.nr_chips	= 1,
		.nr_map		= chip2_map,
		.options        = NAND_SCAN_SILENT_NODEV,
		.nr_partitions	= ARRAY_SIZE(bast_default_nand_part),
		.partitions	= bast_default_nand_part,
	}
};

static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
{
	unsigned int tmp;

	slot = set->nr_map[slot] & 3;

	pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
		 slot, set, set->nr_map);

	tmp = __raw_readb(BAST_VA_CTRL2);
	tmp &= BAST_CPLD_CTLR2_IDERST;
	tmp |= slot;
	tmp |= BAST_CPLD_CTRL2_WNAND;

	pr_debug("bast_nand: ctrl2 now %02x\n", tmp);

	__raw_writeb(tmp, BAST_VA_CTRL2);
}

static struct s3c2410_platform_nand __initdata bast_nand_info = {
	.tacls		= 30,
	.twrph0		= 60,
	.twrph1		= 60,
	.nr_sets	= ARRAY_SIZE(bast_nand_sets),
	.sets		= bast_nand_sets,
	.select_chip	= bast_nand_select,
};

/* DM9000 */

static struct resource bast_dm9k_resource[] = {
	[0] = {
		.start = S3C2410_CS5 + BAST_PA_DM9000,
		.end   = S3C2410_CS5 + BAST_PA_DM9000 + 3,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
		.end   = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
		.flags = IORESOURCE_MEM,
	},
	[2] = {
		.start = IRQ_DM9000,
		.end   = IRQ_DM9000,
		.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
	}

};

/* for the moment we limit ourselves to 16bit IO until some
 * better IO routines can be written and tested
*/

static struct dm9000_plat_data bast_dm9k_platdata = {
	.flags		= DM9000_PLATF_16BITONLY,
};

static struct platform_device bast_device_dm9k = {
	.name		= "dm9000",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(bast_dm9k_resource),
	.resource	= bast_dm9k_resource,
	.dev		= {
		.platform_data = &bast_dm9k_platdata,
	}
};

/* serial devices */

#define SERIAL_BASE  (S3C2410_CS2 + BAST_PA_SUPERIO)
#define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
#define SERIAL_CLK   (1843200)

static struct plat_serial8250_port bast_sio_data[] = {
	[0] = {
		.mapbase	= SERIAL_BASE + 0x2f8,
		.irq		= IRQ_PCSERIAL1,
		.flags		= SERIAL_FLAGS,
		.iotype		= UPIO_MEM,
		.regshift	= 0,
		.uartclk	= SERIAL_CLK,
	},
	[1] = {
		.mapbase	= SERIAL_BASE + 0x3f8,
		.irq		= IRQ_PCSERIAL2,
		.flags		= SERIAL_FLAGS,
		.iotype		= UPIO_MEM,
		.regshift	= 0,
		.uartclk	= SERIAL_CLK,
	},
	{ }
};

static struct platform_device bast_sio = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM,
	.dev			= {
		.platform_data	= &bast_sio_data,
	},
};

/* we have devices on the bus which cannot work much over the
 * standard 100KHz i2c bus frequency
*/

static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
	.flags		= 0,
	.slave_addr	= 0x10,
	.frequency	= 100*1000,
};

/* Asix AX88796 10/100 ethernet controller */

static struct ax_plat_data bast_asix_platdata = {
	.flags		= AXFLG_MAC_FROMDEV,
	.wordlength	= 2,
	.dcr_val	= 0x48,
	.rcr_val	= 0x40,
};

static struct resource bast_asix_resource[] = {
	[0] = {
		.start = S3C2410_CS5 + BAST_PA_ASIXNET,
		.end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
		.end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
		.flags = IORESOURCE_MEM,
	},
	[2] = {
		.start = IRQ_ASIX,
		.end   = IRQ_ASIX,
		.flags = IORESOURCE_IRQ
	}
};

static struct platform_device bast_device_asix = {
	.name		= "ax88796",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(bast_asix_resource),
	.resource	= bast_asix_resource,
	.dev		= {
		.platform_data = &bast_asix_platdata
	}
};

/* Asix AX88796 10/100 ethernet controller parallel port */

static struct resource bast_asixpp_resource[] = {
	[0] = {
		.start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20),
		.end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1,
		.flags = IORESOURCE_MEM,
	}
};

static struct platform_device bast_device_axpp = {
	.name		= "ax88796-pp",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(bast_asixpp_resource),
	.resource	= bast_asixpp_resource,
};

/* LCD/VGA controller */

static struct s3c2410fb_display __initdata bast_lcd_info[] = {
	{
		.type		= S3C2410_LCDCON1_TFT,
		.width		= 640,
		.height		= 480,

		.pixclock	= 33333,
		.xres		= 640,
		.yres		= 480,
		.bpp		= 4,
		.left_margin	= 40,
		.right_margin	= 20,
		.hsync_len	= 88,
		.upper_margin	= 30,
		.lower_margin	= 32,
		.vsync_len	= 3,

		.lcdcon5	= 0x00014b02,
	},
	{
		.type		= S3C2410_LCDCON1_TFT,
		.width		= 640,
		.height		= 480,

		.pixclock	= 33333,
		.xres		= 640,
		.yres		= 480,
		.bpp		= 8,
		.left_margin	= 40,
		.right_margin	= 20,
		.hsync_len	= 88,
		.upper_margin	= 30,
		.lower_margin	= 32,
		.vsync_len	= 3,

		.lcdcon5	= 0x00014b02,
	},
	{
		.type		= S3C2410_LCDCON1_TFT,
		.width		= 640,
		.height		= 480,

		.pixclock	= 33333,
		.xres		= 640,
		.yres		= 480,
		.bpp		= 16,
		.left_margin	= 40,
		.right_margin	= 20,
		.hsync_len	= 88,
		.upper_margin	= 30,
		.lower_margin	= 32,
		.vsync_len	= 3,

		.lcdcon5	= 0x00014b02,
	},
};

/* LCD/VGA controller */

static struct s3c2410fb_mach_info __initdata bast_fb_info = {

	.displays = bast_lcd_info,
	.num_displays = ARRAY_SIZE(bast_lcd_info),
	.default_display = 1,
};

/* I2C devices fitted. */

static struct i2c_board_info bast_i2c_devs[] __initdata = {
	{
		I2C_BOARD_INFO("tlv320aic23", 0x1a),
	}, {
		I2C_BOARD_INFO("simtec-pmu", 0x6b),
	}, {
		I2C_BOARD_INFO("ch7013", 0x75),
	},
};

static struct s3c_hwmon_pdata bast_hwmon_info = {
	/* LCD contrast (0-6.6V) */
	.in[0] = &(struct s3c_hwmon_chcfg) {
		.name		= "lcd-contrast",
		.mult		= 3300,
		.div		= 512,
	},
	/* LED current feedback */
	.in[1] = &(struct s3c_hwmon_chcfg) {
		.name		= "led-feedback",
		.mult		= 3300,
		.div		= 1024,
	},
	/* LCD feedback (0-6.6V) */
	.in[2] = &(struct s3c_hwmon_chcfg) {
		.name		= "lcd-feedback",
		.mult		= 3300,
		.div		= 512,
	},
	/* Vcore (1.8-2.0V), Vref 3.3V  */
	.in[3] = &(struct s3c_hwmon_chcfg) {
		.name		= "vcore",
		.mult		= 3300,
		.div		= 1024,
	},
};

/* Standard BAST devices */
// cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0

static struct platform_device *bast_devices[] __initdata = {
	&s3c_device_ohci,
	&s3c_device_lcd,
	&s3c_device_wdt,
	&s3c_device_i2c0,
 	&s3c_device_rtc,
	&s3c_device_nand,
	&s3c_device_adc,
	&s3c_device_hwmon,
	&bast_device_dm9k,
	&bast_device_asix,
	&bast_device_axpp,
	&bast_sio,
};

static struct clk *bast_clocks[] __initdata = {
	&s3c24xx_dclk0,
	&s3c24xx_dclk1,
	&s3c24xx_clkout0,
	&s3c24xx_clkout1,
	&s3c24xx_uclk,
};

static struct s3c_cpufreq_board __initdata bast_cpufreq = {
	.refresh	= 7800, /* 7.8usec */
	.auto_io	= 1,
	.need_io	= 1,
};

static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = {
	.have_mic	= 1,
	.have_lout	= 1,
};

static void __init bast_map_io(void)
{
	/* initialise the clocks */

	s3c24xx_dclk0.parent = &clk_upll;
	s3c24xx_dclk0.rate   = 12*1000*1000;

	s3c24xx_dclk1.parent = &clk_upll;
	s3c24xx_dclk1.rate   = 24*1000*1000;

	s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
	s3c24xx_clkout1.parent  = &s3c24xx_dclk1;

	s3c24xx_uclk.parent  = &s3c24xx_clkout1;

	s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));

	s3c_hwmon_set_platdata(&bast_hwmon_info);

	s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
	s3c24xx_init_clocks(0);
	s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
}

static void __init bast_init(void)
{
	register_syscore_ops(&bast_pm_syscore_ops);

	s3c_i2c0_set_platdata(&bast_i2c_info);
	s3c_nand_set_platdata(&bast_nand_info);
	s3c24xx_fb_set_platdata(&bast_fb_info);
	platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));

	i2c_register_board_info(0, bast_i2c_devs,
				ARRAY_SIZE(bast_i2c_devs));

	usb_simtec_init();
	nor_simtec_init();
	simtec_audio_add(NULL, true, &bast_audio);

	WARN_ON(gpio_request(S3C2410_GPA(21), "bast nreset"));
	
	s3c_cpufreq_setboard(&bast_cpufreq);
}

MACHINE_START(BAST, "Simtec-BAST")
	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
	.boot_params	= S3C2410_SDRAM_PA + 0x100,
	.map_io		= bast_map_io,
	.init_irq	= s3c24xx_init_irq,
	.init_machine	= bast_init,
	.timer		= &s3c24xx_timer,
MACHINE_END
Commit	Line	Data
1da177e4 LT	1	/* linux/arch/arm/mach-s3c2410/mach-bast.c
1da177e4 LT	2	*
ccae941e	3	* Copyright 2003-2008 Simtec Electronics
1da177e4 LT	4	* Ben Dooks <ben@simtec.co.uk>
	5	*
	6	* http://www.simtec.co.uk/products/EB2410ITX/
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
1da177e4 LT	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/types.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/list.h>
	17	#include <linux/timer.h>
	18	#include <linux/init.h>
ec976d6e	19	#include <linux/gpio.h>
bb072c3c	20	#include <linux/syscore_ops.h>
b6d1f542	21	#include <linux/serial_core.h>
d052d1be	22	#include <linux/platform_device.h>
d97a666f	23	#include <linux/dm9000.h>
b7a12d19	24	#include <linux/ata_platform.h>
042cf0f2	25	#include <linux/i2c.h>
fced80c7	26	#include <linux/io.h>
1da177e4	27
5ce4b1fe BD	28	#include <net/ax88796.h>
5ce4b1fe BD	29
1da177e4 LT	30	#include <asm/mach/arch.h>
	31	#include <asm/mach/map.h>
	32	#include <asm/mach/irq.h>
	33
a09e64fb RK	34	#include <mach/bast-map.h>
	35	#include <mach/bast-irq.h>
	36	#include <mach/bast-cpld.h>
1da177e4	37
a09e64fb	38	#include <mach/hardware.h>
1da177e4 LT	39	#include <asm/irq.h>
	40	#include <asm/mach-types.h>
	41
	42	//#include <asm/debug-ll.h>
a2b7ba9c	43	#include <plat/regs-serial.h>
a09e64fb RK	44	#include <mach/regs-gpio.h>
	45	#include <mach/regs-mem.h>
	46	#include <mach/regs-lcd.h>
58c8d570	47
885f9ebe	48	#include <plat/hwmon.h>
7926b5a3	49	#include <plat/nand.h>
9498cb79	50	#include <plat/iic.h>
a09e64fb	51	#include <mach/fb.h>
1da177e4 LT	52
	53	#include <linux/mtd/mtd.h>
	54	#include <linux/mtd/nand.h>
	55	#include <linux/mtd/nand_ecc.h>
	56	#include <linux/mtd/partitions.h>
	57
65cc3370 BD	58	#include <linux/serial_8250.h>
65cc3370 BD	59
d5120ae7	60	#include <plat/clock.h>
a2b7ba9c BD	61	#include <plat/devs.h>
a2b7ba9c BD	62	#include <plat/cpu.h>
ca0b4901	63	#include <plat/cpu-freq.h>
40b956f0	64	#include <plat/gpio-cfg.h>
4d3a3469	65	#include <plat/audio-simtec.h>
9d529c6e	66
1da177e4	67	#include "usb-simtec.h"
9d529c6e	68	#include "nor-simtec.h"
1da177e4	69
ccae941e	70	#define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
1da177e4 LT	71
	72	/* macros for virtual address mods for the io space entries */
	73	#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
	74	#define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
	75	#define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
	76	#define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
	77
	78	/* macros to modify the physical addresses for io space */
	79
1d23b65d BD	80	#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
	81	#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
	82	#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
	83	#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
1da177e4 LT	84
	85	static struct map_desc bast_iodesc[] __initdata = {
	86	/* ISA IO areas */
1d23b65d BD	87	{
	88	.virtual = (u32)S3C24XX_VA_ISA_BYTE,
	89	.pfn = PA_CS2(BAST_PA_ISAIO),
	90	.length = SZ_16M,
	91	.type = MT_DEVICE,
	92	}, {
	93	.virtual = (u32)S3C24XX_VA_ISA_WORD,
	94	.pfn = PA_CS3(BAST_PA_ISAIO),
	95	.length = SZ_16M,
	96	.type = MT_DEVICE,
	97	},
1da177e4	98	/* bast CPLD control registers, and external interrupt controls */
1d23b65d BD	99	{
	100	.virtual = (u32)BAST_VA_CTRL1,
	101	.pfn = __phys_to_pfn(BAST_PA_CTRL1),
	102	.length = SZ_1M,
	103	.type = MT_DEVICE,
	104	}, {
	105	.virtual = (u32)BAST_VA_CTRL2,
	106	.pfn = __phys_to_pfn(BAST_PA_CTRL2),
	107	.length = SZ_1M,
	108	.type = MT_DEVICE,
	109	}, {
	110	.virtual = (u32)BAST_VA_CTRL3,
	111	.pfn = __phys_to_pfn(BAST_PA_CTRL3),
	112	.length = SZ_1M,
	113	.type = MT_DEVICE,
	114	}, {
	115	.virtual = (u32)BAST_VA_CTRL4,
	116	.pfn = __phys_to_pfn(BAST_PA_CTRL4),
	117	.length = SZ_1M,
	118	.type = MT_DEVICE,
	119	},
1da177e4	120	/* PC104 IRQ mux */
1d23b65d BD	121	{
	122	.virtual = (u32)BAST_VA_PC104_IRQREQ,
	123	.pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
	124	.length = SZ_1M,
	125	.type = MT_DEVICE,
	126	}, {
	127	.virtual = (u32)BAST_VA_PC104_IRQRAW,
	128	.pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
	129	.length = SZ_1M,
	130	.type = MT_DEVICE,
	131	}, {
	132	.virtual = (u32)BAST_VA_PC104_IRQMASK,
	133	.pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
	134	.length = SZ_1M,
	135	.type = MT_DEVICE,
	136	},
1da177e4 LT	137
	138	/* peripheral space... one for each of fast/slow/byte/16bit */
	139	/* note, ide is only decoded in word space, even though some registers
	140	* are only 8bit */
	141
	142	/* slow, byte */
	143	{ VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
	144	{ VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4	145	{ VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4 LT	146
	147	/* slow, word */
	148	{ VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
	149	{ VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4	150	{ VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4 LT	151
	152	/* fast, byte */
	153	{ VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
	154	{ VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4	155	{ VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4 LT	156
	157	/* fast, word */
	158	{ VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
	159	{ VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4	160	{ VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4 LT	161	};
	162
	163	#define UCON S3C2410_UCON_DEFAULT \| S3C2410_UCON_UCLK
	164	#define ULCON S3C2410_LCON_CS8 \| S3C2410_LCON_PNONE \| S3C2410_LCON_STOPB
	165	#define UFCON S3C2410_UFCON_RXTRIG8 \| S3C2410_UFCON_FIFOMODE
	166
	167	static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
	168	[0] = {
	169	.name = "uclk",
	170	.divisor = 1,
	171	.min_baud = 0,
	172	.max_baud = 0,
	173	},
	174	[1] = {
	175	.name = "pclk",
	176	.divisor = 1,
	177	.min_baud = 0,
b526bf23	178	.max_baud = 0,
1da177e4 LT	179	}
	180	};
	181
	182
66a9b49a	183	static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
1da177e4 LT	184	[0] = {
	185	.hwport = 0,
	186	.flags = 0,
	187	.ucon = UCON,
	188	.ulcon = ULCON,
	189	.ufcon = UFCON,
	190	.clocks = bast_serial_clocks,
b526bf23	191	.clocks_size = ARRAY_SIZE(bast_serial_clocks),
1da177e4 LT	192	},
	193	[1] = {
	194	.hwport = 1,
	195	.flags = 0,
	196	.ucon = UCON,
	197	.ulcon = ULCON,
	198	.ufcon = UFCON,
	199	.clocks = bast_serial_clocks,
b526bf23	200	.clocks_size = ARRAY_SIZE(bast_serial_clocks),
1da177e4 LT	201	},
	202	/* port 2 is not actually used */
	203	[2] = {
	204	.hwport = 2,
	205	.flags = 0,
	206	.ucon = UCON,
	207	.ulcon = ULCON,
	208	.ufcon = UFCON,
	209	.clocks = bast_serial_clocks,
b526bf23	210	.clocks_size = ARRAY_SIZE(bast_serial_clocks),
1da177e4 LT	211	}
	212	};
	213
1da177e4 LT	214	/* NAND Flash on BAST board */
1da177e4 LT	215
6ddc4b07	216	#ifdef CONFIG_PM
bb072c3c	217	static int bast_pm_suspend(void)
6ddc4b07 BD	218	{
6ddc4b07 BD	219	/* ensure that an nRESET is not generated on resume. */
408c8b8c	220	gpio_direction_output(S3C2410_GPA(21), 1);
6ddc4b07 BD	221	return 0;
	222	}
	223
bb072c3c	224	static void bast_pm_resume(void)
6ddc4b07	225	{
40b956f0	226	s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
6ddc4b07 BD	227	}
	228
	229	#else
	230	#define bast_pm_suspend NULL
	231	#define bast_pm_resume NULL
	232	#endif
	233
bb072c3c	234	static struct syscore_ops bast_pm_syscore_ops = {
6ddc4b07 BD	235	.suspend = bast_pm_suspend,
	236	.resume = bast_pm_resume,
	237	};
	238
1da177e4 LT	239	static int smartmedia_map[] = { 0 };
	240	static int chip0_map[] = { 1 };
	241	static int chip1_map[] = { 2 };
	242	static int chip2_map[] = { 3 };
	243
2a3a1804	244	static struct mtd_partition __initdata bast_default_nand_part[] = {
1da177e4 LT	245	[0] = {
	246	.name = "Boot Agent",
	247	.size = SZ_16K,
b526bf23	248	.offset = 0,
1da177e4 LT	249	},
	250	[1] = {
	251	.name = "/boot",
	252	.size = SZ_4M - SZ_16K,
	253	.offset = SZ_16K,
	254	},
	255	[2] = {
	256	.name = "user",
	257	.offset = SZ_4M,
	258	.size = MTDPART_SIZ_FULL,
	259	}
	260	};
	261
	262	/* the bast has 4 selectable slots for nand-flash, the three
	263	* on-board chip areas, as well as the external SmartMedia
	264	* slot.
	265	*
	266	* Note, there is no current hot-plug support for the SmartMedia
	267	* socket.
	268	*/
	269
2a3a1804	270	static struct s3c2410_nand_set __initdata bast_nand_sets[] = {
1da177e4 LT	271	[0] = {
	272	.name = "SmartMedia",
	273	.nr_chips = 1,
	274	.nr_map = smartmedia_map,
d3ef7ee4	275	.options = NAND_SCAN_SILENT_NODEV,
1da177e4	276	.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
b526bf23	277	.partitions = bast_default_nand_part,
1da177e4 LT	278	},
	279	[1] = {
	280	.name = "chip0",
	281	.nr_chips = 1,
	282	.nr_map = chip0_map,
	283	.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
b526bf23	284	.partitions = bast_default_nand_part,
1da177e4 LT	285	},
	286	[2] = {
	287	.name = "chip1",
	288	.nr_chips = 1,
	289	.nr_map = chip1_map,
d3ef7ee4	290	.options = NAND_SCAN_SILENT_NODEV,
1da177e4	291	.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
b526bf23	292	.partitions = bast_default_nand_part,
1da177e4 LT	293	},
	294	[3] = {
	295	.name = "chip2",
	296	.nr_chips = 1,
	297	.nr_map = chip2_map,
d3ef7ee4	298	.options = NAND_SCAN_SILENT_NODEV,
1da177e4	299	.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
b526bf23	300	.partitions = bast_default_nand_part,
1da177e4 LT	301	}
	302	};
	303
	304	static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
	305	{
	306	unsigned int tmp;
	307
	308	slot = set->nr_map[slot] & 3;
	309
	310	pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
	311	slot, set, set->nr_map);
	312
	313	tmp = __raw_readb(BAST_VA_CTRL2);
	314	tmp &= BAST_CPLD_CTLR2_IDERST;
	315	tmp \|= slot;
	316	tmp \|= BAST_CPLD_CTRL2_WNAND;
	317
	318	pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
	319
	320	__raw_writeb(tmp, BAST_VA_CTRL2);
	321	}
	322
2a3a1804	323	static struct s3c2410_platform_nand __initdata bast_nand_info = {
b048dbf4 BD	324	.tacls = 30,
	325	.twrph0 = 60,
	326	.twrph1 = 60,
1da177e4 LT	327	.nr_sets = ARRAY_SIZE(bast_nand_sets),
	328	.sets = bast_nand_sets,
	329	.select_chip = bast_nand_select,
	330	};
	331
d97a666f BD	332	/* DM9000 */
	333
	334	static struct resource bast_dm9k_resource[] = {
	335	[0] = {
	336	.start = S3C2410_CS5 + BAST_PA_DM9000,
	337	.end = S3C2410_CS5 + BAST_PA_DM9000 + 3,
b526bf23	338	.flags = IORESOURCE_MEM,
d97a666f BD	339	},
	340	[1] = {
	341	.start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
	342	.end = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
b526bf23	343	.flags = IORESOURCE_MEM,
d97a666f BD	344	},
	345	[2] = {
	346	.start = IRQ_DM9000,
	347	.end = IRQ_DM9000,
9cf345e3	348	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_HIGHLEVEL,
d97a666f BD	349	}
	350
	351	};
	352
	353	/* for the moment we limit ourselves to 16bit IO until some
	354	* better IO routines can be written and tested
	355	*/
	356
9f693d7b	357	static struct dm9000_plat_data bast_dm9k_platdata = {
b526bf23	358	.flags = DM9000_PLATF_16BITONLY,
d97a666f BD	359	};
	360
	361	static struct platform_device bast_device_dm9k = {
	362	.name = "dm9000",
	363	.id = 0,
	364	.num_resources = ARRAY_SIZE(bast_dm9k_resource),
	365	.resource = bast_dm9k_resource,
	366	.dev = {
	367	.platform_data = &bast_dm9k_platdata,
	368	}
	369	};
	370
65cc3370 BD	371	/* serial devices */
	372
	373	#define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO)
	374	#define SERIAL_FLAGS (UPF_BOOT_AUTOCONF \| UPF_IOREMAP \| UPF_SHARE_IRQ)
	375	#define SERIAL_CLK (1843200)
	376
	377	static struct plat_serial8250_port bast_sio_data[] = {
	378	[0] = {
	379	.mapbase = SERIAL_BASE + 0x2f8,
	380	.irq = IRQ_PCSERIAL1,
	381	.flags = SERIAL_FLAGS,
	382	.iotype = UPIO_MEM,
	383	.regshift = 0,
	384	.uartclk = SERIAL_CLK,
	385	},
	386	[1] = {
	387	.mapbase = SERIAL_BASE + 0x3f8,
	388	.irq = IRQ_PCSERIAL2,
	389	.flags = SERIAL_FLAGS,
	390	.iotype = UPIO_MEM,
	391	.regshift = 0,
	392	.uartclk = SERIAL_CLK,
	393	},
	394	{ }
	395	};
	396
	397	static struct platform_device bast_sio = {
	398	.name = "serial8250",
6df29deb	399	.id = PLAT8250_DEV_PLATFORM,
65cc3370 BD	400	.dev = {
	401	.platform_data = &bast_sio_data,
	402	},
	403	};
1da177e4	404
1fcf8448 BD	405	/* we have devices on the bus which cannot work much over the
	406	* standard 100KHz i2c bus frequency
	407	*/
	408
3e1b776c	409	static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
1fcf8448 BD	410	.flags = 0,
1fcf8448 BD	411	.slave_addr = 0x10,
c564e6ae	412	.frequency = 100*1000,
1fcf8448 BD	413	};
1fcf8448 BD	414
5ce4b1fe BD	415	/* Asix AX88796 10/100 ethernet controller */
	416
	417	static struct ax_plat_data bast_asix_platdata = {
	418	.flags = AXFLG_MAC_FROMDEV,
	419	.wordlength = 2,
	420	.dcr_val = 0x48,
	421	.rcr_val = 0x40,
	422	};
	423
	424	static struct resource bast_asix_resource[] = {
	425	[0] = {
	426	.start = S3C2410_CS5 + BAST_PA_ASIXNET,
	427	.end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1,
	428	.flags = IORESOURCE_MEM,
	429	},
	430	[1] = {
	431	.start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
	432	.end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
	433	.flags = IORESOURCE_MEM,
	434	},
	435	[2] = {
	436	.start = IRQ_ASIX,
	437	.end = IRQ_ASIX,
	438	.flags = IORESOURCE_IRQ
	439	}
	440	};
	441
	442	static struct platform_device bast_device_asix = {
	443	.name = "ax88796",
	444	.id = 0,
	445	.num_resources = ARRAY_SIZE(bast_asix_resource),
	446	.resource = bast_asix_resource,
	447	.dev = {
	448	.platform_data = &bast_asix_platdata
	449	}
	450	};
	451
	452	/* Asix AX88796 10/100 ethernet controller parallel port */
	453
	454	static struct resource bast_asixpp_resource[] = {
	455	[0] = {
	456	.start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20),
	457	.end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1,
	458	.flags = IORESOURCE_MEM,
	459	}
	460	};
	461
	462	static struct platform_device bast_device_axpp = {
	463	.name = "ax88796-pp",
	464	.id = 0,
	465	.num_resources = ARRAY_SIZE(bast_asixpp_resource),
	466	.resource = bast_asixpp_resource,
	467	};
	468
	469	/* LCD/VGA controller */
58c8d570	470
09fe75f6 KH	471	static struct s3c2410fb_display __initdata bast_lcd_info[] = {
09fe75f6 KH	472	{
1f411537	473	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	474	.width = 640,
09fe75f6 KH	475	.height = 480,
5f20f69b	476
69816699	477	.pixclock = 33333,
09fe75f6 KH	478	.xres = 640,
	479	.yres = 480,
	480	.bpp = 4,
1f411537 KH	481	.left_margin = 40,
1f411537 KH	482	.right_margin = 20,
93d11f5a	483	.hsync_len = 88,
5f20f69b KH	484	.upper_margin = 30,
5f20f69b KH	485	.lower_margin = 32,
93d11f5a	486	.vsync_len = 3,
09fe75f6	487
f28ef573	488	.lcdcon5 = 0x00014b02,
58c8d570	489	},
09fe75f6	490	{
1f411537	491	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	492	.width = 640,
	493	.height = 480,
	494
69816699	495	.pixclock = 33333,
09fe75f6 KH	496	.xres = 640,
	497	.yres = 480,
	498	.bpp = 8,
1f411537 KH	499	.left_margin = 40,
1f411537 KH	500	.right_margin = 20,
93d11f5a	501	.hsync_len = 88,
5f20f69b KH	502	.upper_margin = 30,
5f20f69b KH	503	.lower_margin = 32,
93d11f5a	504	.vsync_len = 3,
09fe75f6	505
f28ef573	506	.lcdcon5 = 0x00014b02,
09fe75f6 KH	507	},
09fe75f6 KH	508	{
1f411537	509	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	510	.width = 640,
	511	.height = 480,
	512
69816699	513	.pixclock = 33333,
09fe75f6 KH	514	.xres = 640,
	515	.yres = 480,
	516	.bpp = 16,
1f411537 KH	517	.left_margin = 40,
1f411537 KH	518	.right_margin = 20,
93d11f5a	519	.hsync_len = 88,
5f20f69b KH	520	.upper_margin = 30,
5f20f69b KH	521	.lower_margin = 32,
93d11f5a	522	.vsync_len = 3,
09fe75f6	523
f28ef573	524	.lcdcon5 = 0x00014b02,
09fe75f6 KH	525	},
09fe75f6 KH	526	};
58c8d570	527
09fe75f6 KH	528	/* LCD/VGA controller */
	529
	530	static struct s3c2410fb_mach_info __initdata bast_fb_info = {
	531
	532	.displays = bast_lcd_info,
	533	.num_displays = ARRAY_SIZE(bast_lcd_info),
9cbae12c	534	.default_display = 1,
58c8d570 BD	535	};
58c8d570 BD	536
042cf0f2 BD	537	/* I2C devices fitted. */
	538
	539	static struct i2c_board_info bast_i2c_devs[] __initdata = {
	540	{
	541	I2C_BOARD_INFO("tlv320aic23", 0x1a),
	542	}, {
	543	I2C_BOARD_INFO("simtec-pmu", 0x6b),
	544	}, {
	545	I2C_BOARD_INFO("ch7013", 0x75),
	546	},
	547	};
b7a12d19	548
885f9ebe BD	549	static struct s3c_hwmon_pdata bast_hwmon_info = {
	550	/* LCD contrast (0-6.6V) */
	551	.in[0] = &(struct s3c_hwmon_chcfg) {
	552	.name = "lcd-contrast",
	553	.mult = 3300,
	554	.div = 512,
	555	},
	556	/* LED current feedback */
	557	.in[1] = &(struct s3c_hwmon_chcfg) {
	558	.name = "led-feedback",
	559	.mult = 3300,
	560	.div = 1024,
	561	},
	562	/* LCD feedback (0-6.6V) */
	563	.in[2] = &(struct s3c_hwmon_chcfg) {
	564	.name = "lcd-feedback",
	565	.mult = 3300,
	566	.div = 512,
	567	},
	568	/* Vcore (1.8-2.0V), Vref 3.3V */
	569	.in[3] = &(struct s3c_hwmon_chcfg) {
	570	.name = "vcore",
	571	.mult = 3300,
	572	.div = 1024,
	573	},
	574	};
	575
1da177e4	576	/* Standard BAST devices */
885f9ebe	577	// cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0
1da177e4 LT	578
1da177e4 LT	579	static struct platform_device *bast_devices[] __initdata = {
b813248c	580	&s3c_device_ohci,
1da177e4 LT	581	&s3c_device_lcd,
1da177e4 LT	582	&s3c_device_wdt,
3e1b776c	583	&s3c_device_i2c0,
1da177e4 LT	584	&s3c_device_rtc,
1da177e4 LT	585	&s3c_device_nand,
885f9ebe BD	586	&s3c_device_adc,
885f9ebe BD	587	&s3c_device_hwmon,
d97a666f	588	&bast_device_dm9k,
5ce4b1fe BD	589	&bast_device_asix,
5ce4b1fe BD	590	&bast_device_axpp,
65cc3370	591	&bast_sio,
1da177e4 LT	592	};
1da177e4 LT	593
2bc7509f	594	static struct clk *bast_clocks[] __initdata = {
1da177e4 LT	595	&s3c24xx_dclk0,
	596	&s3c24xx_dclk1,
	597	&s3c24xx_clkout0,
	598	&s3c24xx_clkout1,
	599	&s3c24xx_uclk,
	600	};
	601
ca0b4901 BD	602	static struct s3c_cpufreq_board __initdata bast_cpufreq = {
	603	.refresh = 7800, /* 7.8usec */
	604	.auto_io = 1,
	605	.need_io = 1,
	606	};
	607
4d3a3469 BD	608	static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = {
	609	.have_mic = 1,
	610	.have_lout = 1,
	611	};
	612
5fe10ab1	613	static void __init bast_map_io(void)
1da177e4 LT	614	{
	615	/* initialise the clocks */
	616
d96a9804	617	s3c24xx_dclk0.parent = &clk_upll;
1da177e4 LT	618	s3c24xx_dclk0.rate = 1210001000;
1da177e4 LT	619
d96a9804	620	s3c24xx_dclk1.parent = &clk_upll;
1da177e4 LT	621	s3c24xx_dclk1.rate = 2410001000;
	622
	623	s3c24xx_clkout0.parent = &s3c24xx_dclk0;
	624	s3c24xx_clkout1.parent = &s3c24xx_dclk1;
	625
	626	s3c24xx_uclk.parent = &s3c24xx_clkout1;
	627
ce89c206 BD	628	s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
ce89c206 BD	629
6cd82ffe	630	s3c_hwmon_set_platdata(&bast_hwmon_info);
3e1b776c	631
1da177e4 LT	632	s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
	633	s3c24xx_init_clocks(0);
	634	s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
1da177e4 LT	635	}
1da177e4 LT	636
58c8d570 BD	637	static void __init bast_init(void)
58c8d570 BD	638	{
bb072c3c	639	register_syscore_ops(&bast_pm_syscore_ops);
6ddc4b07	640
a8af6de0	641	s3c_i2c0_set_platdata(&bast_i2c_info);
2a3a1804	642	s3c_nand_set_platdata(&bast_nand_info);
09fe75f6	643	s3c24xx_fb_set_platdata(&bast_fb_info);
57e5171c	644	platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
9d529c6e	645
042cf0f2 BD	646	i2c_register_board_info(0, bast_i2c_devs,
	647	ARRAY_SIZE(bast_i2c_devs));
	648
7a05a2cb	649	usb_simtec_init();
9d529c6e	650	nor_simtec_init();
4d3a3469	651	simtec_audio_add(NULL, true, &bast_audio);
ca0b4901	652
408c8b8c BD	653	WARN_ON(gpio_request(S3C2410_GPA(21), "bast nreset"));
408c8b8c BD	654
ca0b4901	655	s3c_cpufreq_setboard(&bast_cpufreq);
58c8d570	656	}
1da177e4 LT	657
1da177e4 LT	658	MACHINE_START(BAST, "Simtec-BAST")
e9dea0c6	659	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
e9dea0c6	660	.boot_params = S3C2410_SDRAM_PA + 0x100,
f705b1ae BD	661	.map_io = bast_map_io,
f705b1ae BD	662	.init_irq = s3c24xx_init_irq,
58c8d570	663	.init_machine = bast_init,
1da177e4 LT	664	.timer = &s3c24xx_timer,
1da177e4 LT	665	MACHINE_END