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1da177e4 LT |
1 | /* linux/arch/arm/mach-s3c2410/pm.c |
2 | * | |
a21765a7 | 3 | * Copyright (c) 2006 Simtec Electronics |
1da177e4 LT |
4 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | |
a21765a7 | 6 | * S3C2410 (and compatible) Power Manager (Suspend-To-RAM) support |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
1da177e4 LT |
21 | */ |
22 | ||
1da177e4 LT |
23 | #include <linux/init.h> |
24 | #include <linux/suspend.h> | |
25 | #include <linux/errno.h> | |
26 | #include <linux/time.h> | |
a21765a7 | 27 | #include <linux/sysdev.h> |
1da177e4 | 28 | |
a09e64fb | 29 | #include <mach/hardware.h> |
1da177e4 LT |
30 | #include <asm/io.h> |
31 | ||
a21765a7 | 32 | #include <asm/mach-types.h> |
1da177e4 | 33 | |
a09e64fb RK |
34 | #include <mach/regs-gpio.h> |
35 | #include <mach/h1940.h> | |
1da177e4 | 36 | |
a2b7ba9c BD |
37 | #include <plat/cpu.h> |
38 | #include <plat/pm.h> | |
1da177e4 LT |
39 | |
40 | #ifdef CONFIG_S3C2410_PM_DEBUG | |
a21765a7 | 41 | extern void pm_dbg(const char *fmt, ...); |
1da177e4 LT |
42 | #define DBG(fmt...) pm_dbg(fmt) |
43 | #else | |
44 | #define DBG(fmt...) printk(KERN_DEBUG fmt) | |
1da177e4 LT |
45 | #endif |
46 | ||
a21765a7 | 47 | static void s3c2410_pm_prepare(void) |
1da177e4 | 48 | { |
a21765a7 | 49 | /* ensure at least GSTATUS3 has the resume address */ |
1da177e4 | 50 | |
a21765a7 | 51 | __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2410_GSTATUS3); |
1da177e4 | 52 | |
a21765a7 BD |
53 | DBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3)); |
54 | DBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4)); | |
1da177e4 | 55 | |
a21765a7 BD |
56 | if (machine_is_h1940()) { |
57 | void *base = phys_to_virt(H1940_SUSPEND_CHECK); | |
58 | unsigned long ptr; | |
59 | unsigned long calc = 0; | |
1da177e4 | 60 | |
a21765a7 | 61 | /* generate check for the bootloader to check on resume */ |
1da177e4 | 62 | |
a21765a7 BD |
63 | for (ptr = 0; ptr < 0x40000; ptr += 0x400) |
64 | calc += __raw_readl(base+ptr); | |
1da177e4 | 65 | |
a21765a7 | 66 | __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM)); |
1da177e4 LT |
67 | } |
68 | ||
a21765a7 BD |
69 | /* the RX3715 uses similar code and the same H1940 and the |
70 | * same offsets for resume and checksum pointers */ | |
1da177e4 | 71 | |
a21765a7 BD |
72 | if (machine_is_rx3715()) { |
73 | void *base = phys_to_virt(H1940_SUSPEND_CHECK); | |
74 | unsigned long ptr; | |
75 | unsigned long calc = 0; | |
1da177e4 | 76 | |
a21765a7 | 77 | /* generate check for the bootloader to check on resume */ |
1da177e4 | 78 | |
a21765a7 BD |
79 | for (ptr = 0; ptr < 0x40000; ptr += 0x4) |
80 | calc += __raw_readl(base+ptr); | |
1da177e4 | 81 | |
a21765a7 | 82 | __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM)); |
1da177e4 LT |
83 | } |
84 | ||
a21765a7 BD |
85 | if ( machine_is_aml_m5900() ) |
86 | s3c2410_gpio_setpin(S3C2410_GPF2, 1); | |
1da177e4 | 87 | |
1da177e4 LT |
88 | } |
89 | ||
a21765a7 | 90 | static int s3c2410_pm_resume(struct sys_device *dev) |
1da177e4 | 91 | { |
a21765a7 | 92 | unsigned long tmp; |
1da177e4 | 93 | |
a21765a7 | 94 | /* unset the return-from-sleep flag, to ensure reset */ |
1da177e4 | 95 | |
a21765a7 BD |
96 | tmp = __raw_readl(S3C2410_GSTATUS2); |
97 | tmp &= S3C2410_GSTATUS2_OFFRESET; | |
98 | __raw_writel(tmp, S3C2410_GSTATUS2); | |
1da177e4 | 99 | |
a21765a7 BD |
100 | if ( machine_is_aml_m5900() ) |
101 | s3c2410_gpio_setpin(S3C2410_GPF2, 0); | |
1da177e4 | 102 | |
a21765a7 | 103 | return 0; |
1da177e4 LT |
104 | } |
105 | ||
a21765a7 | 106 | static int s3c2410_pm_add(struct sys_device *dev) |
1da177e4 | 107 | { |
a21765a7 BD |
108 | pm_cpu_prep = s3c2410_pm_prepare; |
109 | pm_cpu_sleep = s3c2410_cpu_suspend; | |
1da177e4 | 110 | |
a21765a7 | 111 | return 0; |
1da177e4 LT |
112 | } |
113 | ||
a21765a7 BD |
114 | #if defined(CONFIG_CPU_S3C2410) |
115 | static struct sysdev_driver s3c2410_pm_driver = { | |
116 | .add = s3c2410_pm_add, | |
117 | .resume = s3c2410_pm_resume, | |
118 | }; | |
1da177e4 | 119 | |
a21765a7 | 120 | /* register ourselves */ |
1da177e4 | 121 | |
a21765a7 | 122 | static int __init s3c2410_pm_drvinit(void) |
1da177e4 | 123 | { |
a21765a7 | 124 | return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_pm_driver); |
1da177e4 LT |
125 | } |
126 | ||
a21765a7 BD |
127 | arch_initcall(s3c2410_pm_drvinit); |
128 | #endif | |
1da177e4 | 129 | |
a21765a7 BD |
130 | #if defined(CONFIG_CPU_S3C2440) |
131 | static struct sysdev_driver s3c2440_pm_driver = { | |
132 | .add = s3c2410_pm_add, | |
133 | .resume = s3c2410_pm_resume, | |
134 | }; | |
1da177e4 | 135 | |
a21765a7 | 136 | static int __init s3c2440_pm_drvinit(void) |
1da177e4 | 137 | { |
a21765a7 | 138 | return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_pm_driver); |
1da177e4 LT |
139 | } |
140 | ||
a21765a7 BD |
141 | arch_initcall(s3c2440_pm_drvinit); |
142 | #endif | |
1da177e4 | 143 | |
a21765a7 BD |
144 | #if defined(CONFIG_CPU_S3C2442) |
145 | static struct sysdev_driver s3c2442_pm_driver = { | |
146 | .add = s3c2410_pm_add, | |
147 | .resume = s3c2410_pm_resume, | |
1da177e4 LT |
148 | }; |
149 | ||
a21765a7 | 150 | static int __init s3c2442_pm_drvinit(void) |
1da177e4 | 151 | { |
a21765a7 | 152 | return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_pm_driver); |
1da177e4 | 153 | } |
a21765a7 BD |
154 | |
155 | arch_initcall(s3c2442_pm_drvinit); | |
156 | #endif |