Merge branch 'next-samsung-devel' into next-samsung-devel-2
[deliverable/linux.git] / arch / arm / mach-s3c2410 / s3c2410.c
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1da177e4
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1/* linux/arch/arm/mach-s3c2410/s3c2410.c
2 *
3 * Copyright (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://www.simtec.co.uk/products/EB2410ITX/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
1da177e4
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11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
1ec7269f 19#include <linux/gpio.h>
e425382e 20#include <linux/clk.h>
a341305e 21#include <linux/sysdev.h>
bb072c3c 22#include <linux/syscore_ops.h>
b6d1f542 23#include <linux/serial_core.h>
d052d1be 24#include <linux/platform_device.h>
fced80c7 25#include <linux/io.h>
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26
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29#include <asm/mach/irq.h>
30
a09e64fb 31#include <mach/hardware.h>
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32#include <asm/irq.h>
33
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34#include <plat/cpu-freq.h>
35
a09e64fb 36#include <mach/regs-clock.h>
a2b7ba9c 37#include <plat/regs-serial.h>
1da177e4 38
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BD
39#include <plat/s3c2410.h>
40#include <plat/cpu.h>
41#include <plat/devs.h>
d5120ae7 42#include <plat/clock.h>
e24b864a 43#include <plat/pll.h>
bb072c3c 44#include <plat/pm.h>
1da177e4 45
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46#include <plat/gpio-core.h>
47#include <plat/gpio-cfg.h>
48#include <plat/gpio-cfg-helpers.h>
49
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50/* Initial IO mappings */
51
52static struct map_desc s3c2410_iodesc[] __initdata = {
1da177e4 53 IODESC_ENT(CLKPWR),
1da177e4 54 IODESC_ENT(TIMER),
62ee914e 55 IODESC_ENT(WATCHDOG),
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56};
57
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58/* our uart devices */
59
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60/* uart registration process */
61
62void __init s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no)
63{
66a9b49a 64 s3c24xx_init_uartdevs("s3c2410-uart", s3c2410_uart_resources, cfg, no);
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65}
66
67/* s3c2410_map_io
68 *
69 * register the standard cpu IO areas, and any passed in from the
70 * machine specific initialisation.
71*/
72
74b265d4 73void __init s3c2410_map_io(void)
1da177e4 74{
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75 s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1up;
76 s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1up;
1ec7269f 77
1da177e4 78 iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc));
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79}
80
e425382e 81void __init_or_cpufreq s3c2410_setup_clocks(void)
1da177e4 82{
e425382e 83 struct clk *xtal_clk;
1da177e4 84 unsigned long tmp;
e425382e 85 unsigned long xtal;
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86 unsigned long fclk;
87 unsigned long hclk;
88 unsigned long pclk;
89
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90 xtal_clk = clk_get(NULL, "xtal");
91 xtal = clk_get_rate(xtal_clk);
92 clk_put(xtal_clk);
93
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94 /* now we've got our machine bits initialised, work out what
95 * clocks we've got */
96
e24b864a 97 fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal);
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98
99 tmp = __raw_readl(S3C2410_CLKDIVN);
100
101 /* work out clock scalings */
102
103 hclk = fclk / ((tmp & S3C2410_CLKDIVN_HDIVN) ? 2 : 1);
104 pclk = hclk / ((tmp & S3C2410_CLKDIVN_PDIVN) ? 2 : 1);
105
106 /* print brieft summary of clocks, etc */
107
108 printk("S3C2410: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
109 print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
110
111 /* initialise the clocks here, to allow other things like the
112 * console to use them
113 */
114
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115 s3c24xx_setup_clocks(fclk, hclk, pclk);
116}
117
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118/* fake ARMCLK for use with cpufreq, etc. */
119
120static struct clk s3c2410_armclk = {
121 .name = "armclk",
122 .parent = &clk_f,
123 .id = -1,
124};
125
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126void __init s3c2410_init_clocks(int xtal)
127{
128 s3c24xx_register_baseclocks(xtal);
129 s3c2410_setup_clocks();
99c13853 130 s3c2410_baseclk_add();
ad787595 131 s3c24xx_register_clock(&s3c2410_armclk);
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132}
133
a341305e 134struct sysdev_class s3c2410_sysclass = {
af5ca3f4 135 .name = "s3c2410-core",
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136};
137
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138/* Note, we would have liked to name this s3c2410-core, but we cannot
139 * register two sysdev_class with the same name.
140 */
141struct sysdev_class s3c2410a_sysclass = {
142 .name = "s3c2410a-core",
143};
144
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145static struct sys_device s3c2410_sysdev = {
146 .cls = &s3c2410_sysclass,
147};
148
149/* need to register class before we actually register the device, and
150 * we also need to ensure that it has been initialised before any of the
6db3eee4 151 * drivers even try to use it (even if not on an s3c2410 based system)
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152 * as a driver which may support both 2410 and 2440 may try and use it.
153*/
154
155static int __init s3c2410_core_init(void)
156{
157 return sysdev_class_register(&s3c2410_sysclass);
158}
159
160core_initcall(s3c2410_core_init);
161
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162static int __init s3c2410a_core_init(void)
163{
164 return sysdev_class_register(&s3c2410a_sysclass);
165}
166
167core_initcall(s3c2410a_core_init);
168
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169int __init s3c2410_init(void)
170{
171 printk("S3C2410: Initialising architecture\n");
172
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173 register_syscore_ops(&s3c2410_pm_syscore_ops);
174 register_syscore_ops(&s3c24xx_irq_syscore_ops);
175
a341305e 176 return sysdev_register(&s3c2410_sysdev);
1da177e4 177}
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178
179int __init s3c2410a_init(void)
180{
181 s3c2410_sysdev.cls = &s3c2410a_sysclass;
182 return s3c2410_init();
183}
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