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1 | /* linux/arch/arm/mach-s3c2410/s3c2440-clock.c |
2 | * | |
3 | * Copyright (c) 2004-2005 Simtec Electronics | |
4 | * http://armlinux.simtec.co.uk/ | |
5 | * Ben Dooks <ben@simtec.co.uk> | |
6 | * | |
7 | * S3C2440 Clock support | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <linux/init.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/kernel.h> | |
27 | #include <linux/list.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/err.h> | |
30 | #include <linux/device.h> | |
31 | #include <linux/sysdev.h> | |
32 | ||
33 | #include <linux/interrupt.h> | |
34 | #include <linux/ioport.h> | |
35 | ||
36 | #include <asm/hardware.h> | |
37 | #include <asm/atomic.h> | |
38 | #include <asm/irq.h> | |
39 | #include <asm/io.h> | |
40 | ||
41 | #include <asm/hardware/clock.h> | |
42 | #include <asm/arch/regs-clock.h> | |
43 | ||
44 | #include "clock.h" | |
45 | #include "cpu.h" | |
46 | ||
47 | /* S3C2440 extended clock support */ | |
48 | ||
49 | static struct clk s3c2440_clk_upll = { | |
50 | .name = "upll", | |
51 | .id = -1, | |
52 | }; | |
53 | ||
54 | static struct clk s3c2440_clk_cam = { | |
55 | .name = "camif", | |
56 | .id = -1, | |
57 | .enable = s3c24xx_clkcon_enable, | |
58 | .ctrlbit = S3C2440_CLKCON_CAMERA, | |
59 | }; | |
60 | ||
61 | static struct clk s3c2440_clk_ac97 = { | |
62 | .name = "ac97", | |
63 | .id = -1, | |
64 | .enable = s3c24xx_clkcon_enable, | |
65 | .ctrlbit = S3C2440_CLKCON_CAMERA, | |
66 | }; | |
67 | ||
68 | static int s3c2440_clk_add(struct sys_device *sysdev) | |
69 | { | |
70 | unsigned long upllcon = __raw_readl(S3C2410_UPLLCON); | |
71 | struct clk *clk_h; | |
72 | struct clk *clk_p; | |
73 | struct clk *clk_xtal; | |
74 | ||
75 | clk_xtal = clk_get(NULL, "xtal"); | |
76 | if (IS_ERR(clk_xtal)) { | |
77 | printk(KERN_ERR "S3C2440: Failed to get clk_xtal\n"); | |
78 | return -EINVAL; | |
79 | } | |
80 | ||
81 | s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal->rate); | |
82 | ||
83 | printk("S3C2440: Clock Support, UPLL %ld.%03ld MHz\n", | |
84 | print_mhz(s3c2440_clk_upll.rate)); | |
85 | ||
86 | clk_p = clk_get(NULL, "pclk"); | |
87 | clk_h = clk_get(NULL, "hclk"); | |
88 | ||
89 | if (IS_ERR(clk_p) || IS_ERR(clk_h)) { | |
90 | printk(KERN_ERR "S3C2440: Failed to get parent clocks\n"); | |
91 | return -EINVAL; | |
92 | } | |
93 | ||
94 | s3c2440_clk_cam.parent = clk_h; | |
95 | s3c2440_clk_ac97.parent = clk_p; | |
96 | ||
97 | s3c24xx_register_clock(&s3c2440_clk_ac97); | |
98 | s3c24xx_register_clock(&s3c2440_clk_cam); | |
99 | s3c24xx_register_clock(&s3c2440_clk_upll); | |
100 | ||
101 | clk_disable(&s3c2440_clk_ac97); | |
102 | clk_disable(&s3c2440_clk_cam); | |
103 | ||
104 | return 0; | |
105 | } | |
106 | ||
107 | static struct sysdev_driver s3c2440_clk_driver = { | |
108 | .add = s3c2440_clk_add, | |
109 | }; | |
110 | ||
111 | static __init int s3c24xx_clk_driver(void) | |
112 | { | |
113 | return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_clk_driver); | |
114 | } | |
115 | ||
116 | arch_initcall(s3c24xx_clk_driver); |